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annotate e1000_fix_and_improve_set_up_device.patch @ 76:51bea596df7f

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Start a patch for the Rx init
author Louis Opter <louis@lse.epitech.net>
date Sun, 04 Mar 2012 15:27:34 +0100
parents c076a41a753c
children
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1 # HG changeset patch
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2 # Parent 0a4c7ad60a68bfd1e797c0779bc035c20780ec9f
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3 Fix and improve the e1000::set_up_device function:
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4
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5 - The LRST and PHY_RST commands were set instead of *unset* on the
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6 control register;
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7 - Complete the initialization of the device according to the Intel
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8 manuals: unset some registers, zero out the control flow registers and
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9 the statistics registers.
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10
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11 diff --git a/rathaxes/samples/e1000/e1000.blt b/rathaxes/samples/e1000/e1000.blt
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12 --- a/rathaxes/samples/e1000/e1000.blt
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13 +++ b/rathaxes/samples/e1000/e1000.blt
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14 @@ -58,7 +58,12 @@
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15 E1000_MDIC = 0x00020, /* MDI Control - RW */
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16 E1000_IMS = 0x000D0, /* Interrupt Mask Set */
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17 E1000_IMC = 0x000D8, /* Interrupt Mask Clear */
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18 - E1000_ICR = 0x000C0 /* Interrupt Cause Read - R/clr */
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19 + E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
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20 + E1000_FCAL = 0x00028, /* Flow Control Address Low */
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21 + E1000_FCAH = 0x0002c, /* Flow Control Address High */
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22 + E1000_FCT = 0x00030, /* Flow Control Type */
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23 + E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value */
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24 + E1000_CRCERRS = 0x04000, /* CRC Error Count (base address of the statistic register spaces) */
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25 };
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26 }
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27
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28 @@ -446,11 +451,43 @@
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29 {
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30 chunk ::CALL
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31 {
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32 + /*
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33 + * This is documented in the Intel Gigabit Ethernet Controller
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34 + * Software Developper manual.
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35 + *
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36 + * Since this part is actually completely device specific it should
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37 + * not be written here. (but in the front-end).
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38 + */
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39 +
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40 + /*
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41 + * "General Configuration" (section 14.3):
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42 + *
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43 + * - CTRL.ASDE/CTRL.SLU: Let the PHY handle the speed detection &
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44 + * negociation;
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45 + * - CTRL.LRST/FRCSPD: Unset them to initiate the auto-negociation;
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46 + * - CTRL.PHY_RST: Unset it;
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47 + * - CTRL.ILOS: Unset it (ILOS is Invert Loss Of Signal);
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48 + * - CTRL.VME: Make sure it's not set to disable VLAN support;
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49 + * - Set the control flow registers to 0;
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50 + * - Finally, initialize all the statistic registers from
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51 + * E1000_CRCERRS to E1000_TSCTFC.
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52 + */
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53 rtx_e1000_register_set32(&${ctx}->hw_ctx, E1000_CTRL,
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54 E1000_CMD_ASDE |
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55 - E1000_CMD_SLU |
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56 - E1000_CMD_LRST |
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57 - E1000_CMD_PHY_RST);
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58 + E1000_CMD_SLU);
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59 + rtx_e1000_register_unset32(&${ctx}->hw_ctx, E1000_CTRL,
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60 + E1000_CMD_LRST |
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61 + E1000_CMD_FRCSPD |
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62 + E1000_CMD_PHY_RST |
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63 + E1000_CMD_ILOS |
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64 + E1000_CMD_VME);
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65 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCAH, 0);
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66 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCAL, 0);
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67 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCT, 0);
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68 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCTTV, 0);
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69 + int i = 0;
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70 + for (i = 0; i != 64; ++i)
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71 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_CRCERRS + i * 4, 0);
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72 }
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73 }
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74