Mercurial > louis > kiibohd-controller
annotate Bootloader/sim.h @ 412:e7a3be42ae1e
Debug code for interconnect cable debugging
| author | Jacob Alexander <haata@kiibohd.com> |
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| date | Sat, 20 Feb 2016 13:27:49 -0800 |
| parents | 66eccdd9ced5 |
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| rev | line source |
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1 /* Copyright (c) 2011,2012 Simon Schubert <2@0x2c.org>. |
| 341 | 2 * Modifications by Jacob Alexander 2014-2015 <haata@kiibohd.com> |
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3 * |
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4 * This program is free software: you can redistribute it and/or modify |
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5 * it under the terms of the GNU General Public License as published by |
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6 * the Free Software Foundation, either version 3 of the License, or |
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7 * (at your option) any later version. |
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8 * |
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9 * This program is distributed in the hope that it will be useful, |
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 * GNU General Public License for more details. |
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13 * |
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14 * You should have received a copy of the GNU General Public License |
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15 * along with this program. If not, see <http://www.gnu.org/licenses/>. |
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16 */ |
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17 |
| 341 | 18 #pragma once |
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19 |
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20 // ----- Local Includes ----- |
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21 |
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22 #include "mchck.h" |
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23 |
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24 |
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25 |
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26 // ----- Structs ----- |
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27 |
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28 struct SIM_t { |
| 308 | 29 struct SIM_SOPT1_t { |
| 30 UNION_STRUCT_START(32); | |
| 31 uint32_t _rsvd0 : 12; | |
| 32 enum { | |
| 33 SIM_RAMSIZE_8KB = 1, | |
| 34 SIM_RAMSIZE_16KB = 3 | |
| 35 } ramsize : 4; | |
| 36 uint32_t _rsvd1 : 2; | |
| 37 enum { | |
| 38 SIM_OSC32KSEL_SYSTEM = 0, | |
| 39 SIM_OSC32KSEL_RTC = 2, | |
| 40 SIM_OSC32KSEL_LPO = 3 | |
| 41 } osc32ksel : 2; | |
| 42 uint32_t _rsvd2 : 9; | |
| 43 uint32_t usbvstby : 1; | |
| 44 uint32_t usbsstby : 1; | |
| 45 uint32_t usbregen : 1; | |
| 46 UNION_STRUCT_END; | |
| 47 } sopt1; | |
| 48 struct SIM_SOPT1CFG_t { | |
| 49 UNION_STRUCT_START(32); | |
| 50 uint32_t _rsvd0 : 24; | |
| 51 uint32_t urwe : 1; | |
| 52 uint32_t uvswe : 1; | |
| 53 uint32_t usswe : 1; | |
| 54 uint32_t _rsvd1 : 5; | |
| 55 UNION_STRUCT_END; | |
| 56 } sopt1cfg; | |
| 57 uint32_t _pad0[(0x1004 - 0x8) / 4]; | |
| 58 struct SIM_SOPT2_t { | |
| 59 UNION_STRUCT_START(32); | |
| 60 uint32_t _rsvd0 : 4; | |
| 61 enum { | |
| 62 SIM_RTCCLKOUTSEL_1HZ = 0, | |
| 63 SIM_RTCCLKOUTSEL_32KHZ = 1 | |
| 64 } rtcclkoutsel : 1; | |
| 65 enum { | |
| 66 SIM_CLKOUTSEL_FLASH = 2, | |
| 67 SIM_CLKOUTSEL_LPO = 3, | |
| 68 SIM_CLKOUTSEL_MCG = 4, | |
| 69 SIM_CLKOUTSEL_RTC = 5, | |
| 70 SIM_CLKOUTSEL_OSC = 6 | |
| 71 } clkoutsel : 3; | |
| 72 uint32_t _rsvd1 : 3; | |
| 73 enum { | |
| 74 SIM_PTD7PAD_SINGLE = 0, | |
| 75 SIM_PTD7PAD_DOUBLE = 1 | |
| 76 } ptd7pad : 1; | |
| 77 enum { | |
| 78 SIM_TRACECLKSEL_MCG = 0, | |
| 79 SIM_TRACECLKSEL_CORE = 1 | |
| 80 } traceclksel : 1; | |
| 81 uint32_t _rsvd2 : 3; | |
| 82 enum { | |
| 83 SIM_PLLFLLSEL_FLL = 0, | |
| 84 SIM_PLLFLLSEL_PLL = 1 | |
| 85 } pllfllsel : 1; | |
| 86 uint32_t _rsvd3 : 1; | |
| 87 enum { | |
| 88 SIM_USBSRC_EXTERNAL = 0, | |
| 89 SIM_USBSRC_MCG = 1 | |
| 90 } usbsrc : 1; | |
| 91 uint32_t _rsvd4 : 13; | |
| 92 UNION_STRUCT_END; | |
| 93 } sopt2; | |
| 94 uint32_t _pad1; | |
| 95 struct SIM_SOPT4_t { | |
| 96 UNION_STRUCT_START(32); | |
| 97 enum sim_ftmflt { | |
| 98 SIM_FTMFLT_FTM = 0, | |
| 99 SIM_FTMFLT_CMP = 1 | |
| 100 } ftm0flt0 : 1; | |
| 101 enum sim_ftmflt ftm0flt1 : 1; | |
| 102 uint32_t _rsvd0 : 2; | |
| 103 enum sim_ftmflt ftm1flt0 : 1; | |
| 104 uint32_t _rsvd1 : 13; | |
| 105 enum { | |
| 106 SIM_FTMCHSRC_FTM = 0, | |
| 107 SIM_FTMCHSRC_CMP0 = 1, | |
| 108 SIM_FTMCHSRC_CMP1 = 2, | |
| 109 SIM_FTMCHSRC_USBSOF = 3 | |
| 110 } ftm1ch0src : 2; | |
| 111 uint32_t _rsvd2 : 4; | |
| 112 enum sim_ftmclksel { | |
| 113 SIM_FTMCLKSEL_CLK0 = 0, | |
| 114 SIM_FTMCLKSEL_CLK1 = 1 | |
| 115 } ftm0clksel : 1; | |
| 116 enum sim_ftmclksel ftm1clksel : 1; | |
| 117 uint32_t _rsvd3 : 2; | |
| 118 enum { | |
| 119 SIM_FTMTRGSRC_HSCMP0 = 0, | |
| 120 SIM_FTMTRGSRC_FTM1 = 1 | |
| 121 } ftm0trg0src : 1; | |
| 122 uint32_t _rsvd4 : 3; | |
| 123 UNION_STRUCT_END; | |
| 124 } sopt4; | |
| 125 struct SIM_SOPT5_t { | |
| 126 UNION_STRUCT_START(32); | |
| 127 enum sim_uarttxsrc { | |
| 128 SIM_UARTTXSRC_UART = 0, | |
| 129 SIM_UARTTXSRC_FTM = 1 | |
| 130 } uart0txsrc : 1; | |
| 131 uint32_t _rsvd0 : 1; | |
| 132 enum sim_uartrxsrc { | |
| 133 SIM_UARTRXSRC_UART = 0, | |
| 134 SIM_UARTRXSRC_CMP0 = 1, | |
| 135 SIM_UARTRXSRC_CMP1 = 2 | |
| 136 } uart0rxsrc : 2; | |
| 137 enum sim_uarttxsrc uart1txsrc : 1; | |
| 138 uint32_t _rsvd1 : 1; | |
| 139 enum sim_uartrxsrc uart1rxsrc : 2; | |
| 140 uint32_t _rsvd2 : 24; | |
| 141 UNION_STRUCT_END; | |
| 142 } sopt5; | |
| 143 uint32_t _pad2; | |
| 144 struct SIM_SOPT7_t { | |
| 145 UNION_STRUCT_START(32); | |
| 146 enum { | |
| 147 SIM_ADCTRGSEL_PDB = 0, | |
| 148 SIM_ADCTRGSEL_HSCMP0 = 1, | |
| 149 SIM_ADCTRGSEL_HSCMP1 = 2, | |
| 150 SIM_ADCTRGSEL_PIT0 = 4, | |
| 151 SIM_ADCTRGSEL_PIT1 = 5, | |
| 152 SIM_ADCTRGSEL_PIT2 = 6, | |
| 153 SIM_ADCTRGSEL_PIT3 = 7, | |
| 154 SIM_ADCTRGSEL_FTM0 = 8, | |
| 155 SIM_ADCTRGSEL_FTM1 = 9, | |
| 156 SIM_ADCTRGSEL_RTCALARM = 12, | |
| 157 SIM_ADCTRGSEL_RTCSECS = 13, | |
| 158 SIM_ADCTRGSEL_LPTIMER = 14 | |
| 159 } adc0trgsel : 4; | |
| 160 enum { | |
| 161 SIM_ADCPRETRGSEL_A = 0, | |
| 162 SIM_ADCPRETRGSEL_B = 1 | |
| 163 } adc0pretrgsel : 1; | |
| 164 uint32_t _rsvd0 : 2; | |
| 165 enum { | |
| 166 SIM_ADCALTTRGEN_PDB = 0, | |
| 167 SIM_ADCALTTRGEN_ALT = 1 | |
| 168 } adc0alttrgen : 1; | |
| 169 uint32_t _rsvd1 : 24; | |
| 170 UNION_STRUCT_END; | |
| 171 } sopt7; | |
| 172 uint32_t _pad3[(0x1024 - 0x101c) / 4]; | |
| 173 struct SIM_SDID_t { | |
| 174 UNION_STRUCT_START(32); | |
| 175 enum { | |
| 176 SIM_PINID_32 = 2, | |
| 177 SIM_PINID_48 = 4, | |
| 178 SIM_PINID_64 = 5 | |
| 179 } pinid : 4; | |
| 180 enum { | |
| 181 SIM_FAMID_K10 = 0, | |
| 182 SIM_FAMID_K20 = 1 | |
| 183 } famid : 3; | |
| 184 uint32_t _rsvd1 : 5; | |
| 185 uint32_t revid : 4; | |
| 186 uint32_t _rsvd2 : 16; | |
| 187 UNION_STRUCT_END; | |
| 188 } sdid; | |
| 189 uint32_t _pad4[(0x1034 - 0x1028) / 4]; | |
| 190 struct SIM_SCGC4_t { | |
| 191 UNION_STRUCT_START(32); | |
| 192 uint32_t _rsvd0 : 1; | |
| 193 uint32_t ewm : 1; | |
| 194 uint32_t cmt : 1; | |
| 195 uint32_t _rsvd1 : 3; | |
| 196 uint32_t i2c0 : 1; | |
| 197 uint32_t _rsvd2 : 3; | |
| 198 uint32_t uart0 : 1; | |
| 199 uint32_t uart1 : 1; | |
| 200 uint32_t uart2 : 1; | |
| 201 uint32_t _rsvd3 : 5; | |
| 202 uint32_t usbotg : 1; | |
| 203 uint32_t cmp : 1; | |
| 204 uint32_t vref : 1; | |
| 205 uint32_t _rsvd4 : 11; | |
| 206 UNION_STRUCT_END; | |
| 207 } scgc4; | |
| 208 struct SIM_SCGC5_t { | |
| 209 UNION_STRUCT_START(32); | |
| 210 uint32_t lptimer : 1; | |
| 211 uint32_t _rsvd0 : 4; | |
| 212 uint32_t tsi : 1; | |
| 213 uint32_t _rsvd1 : 3; | |
| 214 uint32_t porta : 1; | |
| 215 uint32_t portb : 1; | |
| 216 uint32_t portc : 1; | |
| 217 uint32_t portd : 1; | |
| 218 uint32_t porte : 1; | |
| 219 uint32_t _rsvd2 : 18; | |
| 220 UNION_STRUCT_END; | |
| 221 } scgc5; | |
| 222 struct SIM_SCGC6_t { | |
| 223 UNION_STRUCT_START(32); | |
| 224 uint32_t ftfl : 1; | |
| 225 uint32_t dmamux : 1; | |
| 226 uint32_t _rsvd0 : 10; | |
| 227 uint32_t spi0 : 1; | |
| 228 uint32_t _rsvd1 : 2; | |
| 229 uint32_t i2s : 1; | |
| 230 uint32_t _rsvd2 : 2; | |
| 231 uint32_t crc : 1; | |
| 232 uint32_t _rsvd3 : 2; | |
| 233 uint32_t usbdcd : 1; | |
| 234 uint32_t pdb : 1; | |
| 235 uint32_t pit : 1; | |
| 236 uint32_t ftm0 : 1; | |
| 237 uint32_t ftm1 : 1; | |
| 238 uint32_t _rsvd4 : 1; | |
| 239 uint32_t adc0 : 1; | |
| 240 uint32_t _rsvd5 : 1; | |
| 241 uint32_t rtc : 1; | |
| 242 uint32_t _rsvd6 : 2; | |
| 243 UNION_STRUCT_END; | |
| 244 } scgc6; | |
| 245 struct SIM_SCGC7_t { | |
| 246 UNION_STRUCT_START(32); | |
| 247 uint32_t _rsvd0 : 1; | |
| 248 uint32_t dma : 1; | |
| 249 uint32_t _rsvd1 : 30; | |
| 250 UNION_STRUCT_END; | |
| 251 } scgc7; | |
| 252 struct SIM_CLKDIV1_t { | |
| 253 UNION_STRUCT_START(32); | |
| 254 uint32_t _rsvd0 : 16; | |
| 255 uint32_t outdiv4 : 4; | |
| 256 uint32_t _rsvd1 : 4; | |
| 257 uint32_t outdiv2 : 4; | |
| 258 uint32_t outdiv1 : 4; | |
| 259 UNION_STRUCT_END; | |
| 260 } clkdiv1; | |
| 261 struct SIM_CLKDIV2_t { | |
| 262 UNION_STRUCT_START(32); | |
| 263 uint32_t usbfrac : 1; | |
| 264 uint32_t usbdiv : 3; | |
| 265 uint32_t _rsvd0 : 28; | |
| 266 UNION_STRUCT_END; | |
| 267 } clkdiv2; | |
| 268 struct SIM_FCFG1_t { | |
| 269 UNION_STRUCT_START(32); | |
| 270 uint32_t flashdis : 1; | |
| 271 uint32_t flashdoze : 1; | |
| 272 uint32_t _rsvd0 : 6; | |
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273 |
| 308 | 274 /* the following enum is analogous to enum |
| 275 * FTFL_FLEXNVM_PARTITION in ftfl.h, but that one is padded | |
| 276 * with four 1-bits to make an 8-bit value. | |
| 277 */ | |
| 278 enum SIM_FLEXNVM_PARTITION { | |
| 279 SIM_FLEXNVM_DATA_32_EEPROM_0 = 0x0, | |
| 280 SIM_FLEXNVM_DATA_24_EEPROM_8 = 0x1, | |
| 281 SIM_FLEXNVM_DATA_16_EEPROM_16 = 0x2, | |
| 282 SIM_FLEXNVM_DATA_8_EEPROM_24 = 0x9, | |
| 283 SIM_FLEXNVM_DATA_0_EEPROM_32 = 0x3 | |
| 284 } depart : 4; | |
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285 |
| 308 | 286 uint32_t _rsvd1 : 4; |
| 287 enum { | |
| 288 SIM_EESIZE_2KB = 3, | |
| 289 SIM_EESIZE_1KB = 4, | |
| 290 SIM_EESIZE_512B = 5, | |
| 291 SIM_EESIZE_256B = 6, | |
| 292 SIM_EESIZE_128B = 7, | |
| 293 SIM_EESIZE_64B = 8, | |
| 294 SIM_EESIZE_32B = 9, | |
| 295 SIM_EESIZE_0B = 15 | |
| 296 } eesize : 4; | |
| 297 uint32_t _rsvd2 : 4; | |
| 298 enum { | |
| 299 SIM_PFSIZE_32KB = 3, | |
| 300 SIM_PFSIZE_64KB = 5, | |
| 301 SIM_PFSIZE_128KB = 7 | |
| 302 } pfsize : 4; | |
| 303 enum { | |
| 304 SIM_NVMSIZE_0KB = 0, | |
| 305 SIM_NVMSIZE_32KB = 3 | |
| 306 } nvmsize : 4; | |
| 307 UNION_STRUCT_END; | |
| 308 } fcfg1; | |
| 309 struct SIM_FCFG2_t { | |
| 310 UNION_STRUCT_START(32); | |
| 311 uint32_t _rsvd0 : 16; | |
| 312 uint32_t maxaddr1 : 7; | |
| 313 enum { | |
| 314 SIM_PFLSH_FLEXNVM = 0, | |
| 315 SIM_PFLSH_PROGRAM = 1 | |
| 316 } pflsh : 1; | |
| 317 uint32_t maxaddr0 : 7; | |
| 318 uint32_t _rsvd1 : 1; | |
| 319 UNION_STRUCT_END; | |
| 320 } fcfg2; | |
| 321 uint32_t uidh; | |
| 322 uint32_t uidmh; | |
| 323 uint32_t uidml; | |
| 324 uint32_t uidl; | |
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325 }; |
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326 CTASSERT_SIZE_BYTE(struct SIM_t, 0x1064); |
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327 |
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328 extern volatile struct SIM_t SIM; |
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329 |