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comparison Lib/mk20dx.h @ 331:9e31d92caf12

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Initial STLcd code. - Basic screen initialization and clear is working - Currently SPI is set to a low speed for easy logic analyzer debugging
author Jacob Alexander <haata@kiibohd.com>
date Tue, 14 Apr 2015 00:40:48 -0700
parents 48e69c499057
children 772f9bea482b
comparison
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330:f4d4cad283c6 331:9e31d92caf12
1 /* Teensyduino Core Library 1 /* Teensyduino Core Library
2 * http://www.pjrc.com/teensy/ 2 * http://www.pjrc.com/teensy/
3 * Copyright (c) 2013 PJRC.COM, LLC. 3 * Copyright (c) 2013 PJRC.COM, LLC.
4 * Modified by Jacob Alexander 2014 4 * Modified by Jacob Alexander 2014-2015
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining 6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the 7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including 8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish, 9 * without limitation the rights to use, copy, modify, merge, publish,
1341 #define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag 1341 #define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag
1342 #define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag 1342 #define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag
1343 #define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag 1343 #define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag
1344 #define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag 1344 #define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag
1345 #define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag 1345 #define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag
1346 #define SPI_SR_TXCTR (uint32_t)0x0000F000 // Transmit FIFO Counter
1347 #define SPI_SR_TXNXTPTR (uint32_t)0x00000F00 // Transmit Next, Pointer
1348 #define SPI_SR_RXCTR (uint32_t)0x000000F0 // Receive FIFO Counter
1349 #define SPI_SR_POPNXTPTR (uint32_t)0x0000000F // Pop Next, Pointer
1346 #define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register 1350 #define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register
1347 #define SPI_RSER_TCF_RE (uint32_t)0x80000000 // Transmission Complete Request Enable 1351 #define SPI_RSER_TCF_RE (uint32_t)0x80000000 // Transmission Complete Request Enable
1348 #define SPI_RSER_EOQF_RE (uint32_t)0x10000000 // DSPI Finished Request Request Enable 1352 #define SPI_RSER_EOQF_RE (uint32_t)0x10000000 // DSPI Finished Request Request Enable
1349 #define SPI_RSER_TFUF_RE (uint32_t)0x08000000 // Transmit FIFO Underflow Request Enable 1353 #define SPI_RSER_TFUF_RE (uint32_t)0x08000000 // Transmit FIFO Underflow Request Enable
1350 #define SPI_RSER_TFFF_RE (uint32_t)0x02000000 // Transmit FIFO Fill Request Enable 1354 #define SPI_RSER_TFFF_RE (uint32_t)0x02000000 // Transmit FIFO Fill Request Enable