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comparison Bootloader/sim.h @ 308:ab4515606277

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Fix whitespace Use a consistent standard - Tabs in front for indenting, spaces after for anything else. This way everything stays nice and lined up while also letting users change there prefered indent level. Most of the new files from Haata where already in this format.
author Rowan Decker <Smasher816@gmail.com>
date Sun, 08 Mar 2015 18:40:01 -0700
parents b091bb09c55f
children 66eccdd9ced5
comparison
equal deleted inserted replaced
305:4617ef5e06f1 308:ab4515606277
25 25
26 26
27 // ----- Structs ----- 27 // ----- Structs -----
28 28
29 struct SIM_t { 29 struct SIM_t {
30 struct SIM_SOPT1_t { 30 struct SIM_SOPT1_t {
31 UNION_STRUCT_START(32); 31 UNION_STRUCT_START(32);
32 uint32_t _rsvd0 : 12; 32 uint32_t _rsvd0 : 12;
33 enum { 33 enum {
34 SIM_RAMSIZE_8KB = 1, 34 SIM_RAMSIZE_8KB = 1,
35 SIM_RAMSIZE_16KB = 3 35 SIM_RAMSIZE_16KB = 3
36 } ramsize : 4; 36 } ramsize : 4;
37 uint32_t _rsvd1 : 2; 37 uint32_t _rsvd1 : 2;
38 enum { 38 enum {
39 SIM_OSC32KSEL_SYSTEM = 0, 39 SIM_OSC32KSEL_SYSTEM = 0,
40 SIM_OSC32KSEL_RTC = 2, 40 SIM_OSC32KSEL_RTC = 2,
41 SIM_OSC32KSEL_LPO = 3 41 SIM_OSC32KSEL_LPO = 3
42 } osc32ksel : 2; 42 } osc32ksel : 2;
43 uint32_t _rsvd2 : 9; 43 uint32_t _rsvd2 : 9;
44 uint32_t usbvstby : 1; 44 uint32_t usbvstby : 1;
45 uint32_t usbsstby : 1; 45 uint32_t usbsstby : 1;
46 uint32_t usbregen : 1; 46 uint32_t usbregen : 1;
47 UNION_STRUCT_END; 47 UNION_STRUCT_END;
48 } sopt1; 48 } sopt1;
49 struct SIM_SOPT1CFG_t { 49 struct SIM_SOPT1CFG_t {
50 UNION_STRUCT_START(32); 50 UNION_STRUCT_START(32);
51 uint32_t _rsvd0 : 24; 51 uint32_t _rsvd0 : 24;
52 uint32_t urwe : 1; 52 uint32_t urwe : 1;
53 uint32_t uvswe : 1; 53 uint32_t uvswe : 1;
54 uint32_t usswe : 1; 54 uint32_t usswe : 1;
55 uint32_t _rsvd1 : 5; 55 uint32_t _rsvd1 : 5;
56 UNION_STRUCT_END; 56 UNION_STRUCT_END;
57 } sopt1cfg; 57 } sopt1cfg;
58 uint32_t _pad0[(0x1004 - 0x8) / 4]; 58 uint32_t _pad0[(0x1004 - 0x8) / 4];
59 struct SIM_SOPT2_t { 59 struct SIM_SOPT2_t {
60 UNION_STRUCT_START(32); 60 UNION_STRUCT_START(32);
61 uint32_t _rsvd0 : 4; 61 uint32_t _rsvd0 : 4;
62 enum { 62 enum {
63 SIM_RTCCLKOUTSEL_1HZ = 0, 63 SIM_RTCCLKOUTSEL_1HZ = 0,
64 SIM_RTCCLKOUTSEL_32KHZ = 1 64 SIM_RTCCLKOUTSEL_32KHZ = 1
65 } rtcclkoutsel : 1; 65 } rtcclkoutsel : 1;
66 enum { 66 enum {
67 SIM_CLKOUTSEL_FLASH = 2, 67 SIM_CLKOUTSEL_FLASH = 2,
68 SIM_CLKOUTSEL_LPO = 3, 68 SIM_CLKOUTSEL_LPO = 3,
69 SIM_CLKOUTSEL_MCG = 4, 69 SIM_CLKOUTSEL_MCG = 4,
70 SIM_CLKOUTSEL_RTC = 5, 70 SIM_CLKOUTSEL_RTC = 5,
71 SIM_CLKOUTSEL_OSC = 6 71 SIM_CLKOUTSEL_OSC = 6
72 } clkoutsel : 3; 72 } clkoutsel : 3;
73 uint32_t _rsvd1 : 3; 73 uint32_t _rsvd1 : 3;
74 enum { 74 enum {
75 SIM_PTD7PAD_SINGLE = 0, 75 SIM_PTD7PAD_SINGLE = 0,
76 SIM_PTD7PAD_DOUBLE = 1 76 SIM_PTD7PAD_DOUBLE = 1
77 } ptd7pad : 1; 77 } ptd7pad : 1;
78 enum { 78 enum {
79 SIM_TRACECLKSEL_MCG = 0, 79 SIM_TRACECLKSEL_MCG = 0,
80 SIM_TRACECLKSEL_CORE = 1 80 SIM_TRACECLKSEL_CORE = 1
81 } traceclksel : 1; 81 } traceclksel : 1;
82 uint32_t _rsvd2 : 3; 82 uint32_t _rsvd2 : 3;
83 enum { 83 enum {
84 SIM_PLLFLLSEL_FLL = 0, 84 SIM_PLLFLLSEL_FLL = 0,
85 SIM_PLLFLLSEL_PLL = 1 85 SIM_PLLFLLSEL_PLL = 1
86 } pllfllsel : 1; 86 } pllfllsel : 1;
87 uint32_t _rsvd3 : 1; 87 uint32_t _rsvd3 : 1;
88 enum { 88 enum {
89 SIM_USBSRC_EXTERNAL = 0, 89 SIM_USBSRC_EXTERNAL = 0,
90 SIM_USBSRC_MCG = 1 90 SIM_USBSRC_MCG = 1
91 } usbsrc : 1; 91 } usbsrc : 1;
92 uint32_t _rsvd4 : 13; 92 uint32_t _rsvd4 : 13;
93 UNION_STRUCT_END; 93 UNION_STRUCT_END;
94 } sopt2; 94 } sopt2;
95 uint32_t _pad1; 95 uint32_t _pad1;
96 struct SIM_SOPT4_t { 96 struct SIM_SOPT4_t {
97 UNION_STRUCT_START(32); 97 UNION_STRUCT_START(32);
98 enum sim_ftmflt { 98 enum sim_ftmflt {
99 SIM_FTMFLT_FTM = 0, 99 SIM_FTMFLT_FTM = 0,
100 SIM_FTMFLT_CMP = 1 100 SIM_FTMFLT_CMP = 1
101 } ftm0flt0 : 1; 101 } ftm0flt0 : 1;
102 enum sim_ftmflt ftm0flt1 : 1; 102 enum sim_ftmflt ftm0flt1 : 1;
103 uint32_t _rsvd0 : 2; 103 uint32_t _rsvd0 : 2;
104 enum sim_ftmflt ftm1flt0 : 1; 104 enum sim_ftmflt ftm1flt0 : 1;
105 uint32_t _rsvd1 : 13; 105 uint32_t _rsvd1 : 13;
106 enum { 106 enum {
107 SIM_FTMCHSRC_FTM = 0, 107 SIM_FTMCHSRC_FTM = 0,
108 SIM_FTMCHSRC_CMP0 = 1, 108 SIM_FTMCHSRC_CMP0 = 1,
109 SIM_FTMCHSRC_CMP1 = 2, 109 SIM_FTMCHSRC_CMP1 = 2,
110 SIM_FTMCHSRC_USBSOF = 3 110 SIM_FTMCHSRC_USBSOF = 3
111 } ftm1ch0src : 2; 111 } ftm1ch0src : 2;
112 uint32_t _rsvd2 : 4; 112 uint32_t _rsvd2 : 4;
113 enum sim_ftmclksel { 113 enum sim_ftmclksel {
114 SIM_FTMCLKSEL_CLK0 = 0, 114 SIM_FTMCLKSEL_CLK0 = 0,
115 SIM_FTMCLKSEL_CLK1 = 1 115 SIM_FTMCLKSEL_CLK1 = 1
116 } ftm0clksel : 1; 116 } ftm0clksel : 1;
117 enum sim_ftmclksel ftm1clksel : 1; 117 enum sim_ftmclksel ftm1clksel : 1;
118 uint32_t _rsvd3 : 2; 118 uint32_t _rsvd3 : 2;
119 enum { 119 enum {
120 SIM_FTMTRGSRC_HSCMP0 = 0, 120 SIM_FTMTRGSRC_HSCMP0 = 0,
121 SIM_FTMTRGSRC_FTM1 = 1 121 SIM_FTMTRGSRC_FTM1 = 1
122 } ftm0trg0src : 1; 122 } ftm0trg0src : 1;
123 uint32_t _rsvd4 : 3; 123 uint32_t _rsvd4 : 3;
124 UNION_STRUCT_END; 124 UNION_STRUCT_END;
125 } sopt4; 125 } sopt4;
126 struct SIM_SOPT5_t { 126 struct SIM_SOPT5_t {
127 UNION_STRUCT_START(32); 127 UNION_STRUCT_START(32);
128 enum sim_uarttxsrc { 128 enum sim_uarttxsrc {
129 SIM_UARTTXSRC_UART = 0, 129 SIM_UARTTXSRC_UART = 0,
130 SIM_UARTTXSRC_FTM = 1 130 SIM_UARTTXSRC_FTM = 1
131 } uart0txsrc : 1; 131 } uart0txsrc : 1;
132 uint32_t _rsvd0 : 1; 132 uint32_t _rsvd0 : 1;
133 enum sim_uartrxsrc { 133 enum sim_uartrxsrc {
134 SIM_UARTRXSRC_UART = 0, 134 SIM_UARTRXSRC_UART = 0,
135 SIM_UARTRXSRC_CMP0 = 1, 135 SIM_UARTRXSRC_CMP0 = 1,
136 SIM_UARTRXSRC_CMP1 = 2 136 SIM_UARTRXSRC_CMP1 = 2
137 } uart0rxsrc : 2; 137 } uart0rxsrc : 2;
138 enum sim_uarttxsrc uart1txsrc : 1; 138 enum sim_uarttxsrc uart1txsrc : 1;
139 uint32_t _rsvd1 : 1; 139 uint32_t _rsvd1 : 1;
140 enum sim_uartrxsrc uart1rxsrc : 2; 140 enum sim_uartrxsrc uart1rxsrc : 2;
141 uint32_t _rsvd2 : 24; 141 uint32_t _rsvd2 : 24;
142 UNION_STRUCT_END; 142 UNION_STRUCT_END;
143 } sopt5; 143 } sopt5;
144 uint32_t _pad2; 144 uint32_t _pad2;
145 struct SIM_SOPT7_t { 145 struct SIM_SOPT7_t {
146 UNION_STRUCT_START(32); 146 UNION_STRUCT_START(32);
147 enum { 147 enum {
148 SIM_ADCTRGSEL_PDB = 0, 148 SIM_ADCTRGSEL_PDB = 0,
149 SIM_ADCTRGSEL_HSCMP0 = 1, 149 SIM_ADCTRGSEL_HSCMP0 = 1,
150 SIM_ADCTRGSEL_HSCMP1 = 2, 150 SIM_ADCTRGSEL_HSCMP1 = 2,
151 SIM_ADCTRGSEL_PIT0 = 4, 151 SIM_ADCTRGSEL_PIT0 = 4,
152 SIM_ADCTRGSEL_PIT1 = 5, 152 SIM_ADCTRGSEL_PIT1 = 5,
153 SIM_ADCTRGSEL_PIT2 = 6, 153 SIM_ADCTRGSEL_PIT2 = 6,
154 SIM_ADCTRGSEL_PIT3 = 7, 154 SIM_ADCTRGSEL_PIT3 = 7,
155 SIM_ADCTRGSEL_FTM0 = 8, 155 SIM_ADCTRGSEL_FTM0 = 8,
156 SIM_ADCTRGSEL_FTM1 = 9, 156 SIM_ADCTRGSEL_FTM1 = 9,
157 SIM_ADCTRGSEL_RTCALARM = 12, 157 SIM_ADCTRGSEL_RTCALARM = 12,
158 SIM_ADCTRGSEL_RTCSECS = 13, 158 SIM_ADCTRGSEL_RTCSECS = 13,
159 SIM_ADCTRGSEL_LPTIMER = 14 159 SIM_ADCTRGSEL_LPTIMER = 14
160 } adc0trgsel : 4; 160 } adc0trgsel : 4;
161 enum { 161 enum {
162 SIM_ADCPRETRGSEL_A = 0, 162 SIM_ADCPRETRGSEL_A = 0,
163 SIM_ADCPRETRGSEL_B = 1 163 SIM_ADCPRETRGSEL_B = 1
164 } adc0pretrgsel : 1; 164 } adc0pretrgsel : 1;
165 uint32_t _rsvd0 : 2; 165 uint32_t _rsvd0 : 2;
166 enum { 166 enum {
167 SIM_ADCALTTRGEN_PDB = 0, 167 SIM_ADCALTTRGEN_PDB = 0,
168 SIM_ADCALTTRGEN_ALT = 1 168 SIM_ADCALTTRGEN_ALT = 1
169 } adc0alttrgen : 1; 169 } adc0alttrgen : 1;
170 uint32_t _rsvd1 : 24; 170 uint32_t _rsvd1 : 24;
171 UNION_STRUCT_END; 171 UNION_STRUCT_END;
172 } sopt7; 172 } sopt7;
173 uint32_t _pad3[(0x1024 - 0x101c) / 4]; 173 uint32_t _pad3[(0x1024 - 0x101c) / 4];
174 struct SIM_SDID_t { 174 struct SIM_SDID_t {
175 UNION_STRUCT_START(32); 175 UNION_STRUCT_START(32);
176 enum { 176 enum {
177 SIM_PINID_32 = 2, 177 SIM_PINID_32 = 2,
178 SIM_PINID_48 = 4, 178 SIM_PINID_48 = 4,
179 SIM_PINID_64 = 5 179 SIM_PINID_64 = 5
180 } pinid : 4; 180 } pinid : 4;
181 enum { 181 enum {
182 SIM_FAMID_K10 = 0, 182 SIM_FAMID_K10 = 0,
183 SIM_FAMID_K20 = 1 183 SIM_FAMID_K20 = 1
184 } famid : 3; 184 } famid : 3;
185 uint32_t _rsvd1 : 5; 185 uint32_t _rsvd1 : 5;
186 uint32_t revid : 4; 186 uint32_t revid : 4;
187 uint32_t _rsvd2 : 16; 187 uint32_t _rsvd2 : 16;
188 UNION_STRUCT_END; 188 UNION_STRUCT_END;
189 } sdid; 189 } sdid;
190 uint32_t _pad4[(0x1034 - 0x1028) / 4]; 190 uint32_t _pad4[(0x1034 - 0x1028) / 4];
191 struct SIM_SCGC4_t { 191 struct SIM_SCGC4_t {
192 UNION_STRUCT_START(32); 192 UNION_STRUCT_START(32);
193 uint32_t _rsvd0 : 1; 193 uint32_t _rsvd0 : 1;
194 uint32_t ewm : 1; 194 uint32_t ewm : 1;
195 uint32_t cmt : 1; 195 uint32_t cmt : 1;
196 uint32_t _rsvd1 : 3; 196 uint32_t _rsvd1 : 3;
197 uint32_t i2c0 : 1; 197 uint32_t i2c0 : 1;
198 uint32_t _rsvd2 : 3; 198 uint32_t _rsvd2 : 3;
199 uint32_t uart0 : 1; 199 uint32_t uart0 : 1;
200 uint32_t uart1 : 1; 200 uint32_t uart1 : 1;
201 uint32_t uart2 : 1; 201 uint32_t uart2 : 1;
202 uint32_t _rsvd3 : 5; 202 uint32_t _rsvd3 : 5;
203 uint32_t usbotg : 1; 203 uint32_t usbotg : 1;
204 uint32_t cmp : 1; 204 uint32_t cmp : 1;
205 uint32_t vref : 1; 205 uint32_t vref : 1;
206 uint32_t _rsvd4 : 11; 206 uint32_t _rsvd4 : 11;
207 UNION_STRUCT_END; 207 UNION_STRUCT_END;
208 } scgc4; 208 } scgc4;
209 struct SIM_SCGC5_t { 209 struct SIM_SCGC5_t {
210 UNION_STRUCT_START(32); 210 UNION_STRUCT_START(32);
211 uint32_t lptimer : 1; 211 uint32_t lptimer : 1;
212 uint32_t _rsvd0 : 4; 212 uint32_t _rsvd0 : 4;
213 uint32_t tsi : 1; 213 uint32_t tsi : 1;
214 uint32_t _rsvd1 : 3; 214 uint32_t _rsvd1 : 3;
215 uint32_t porta : 1; 215 uint32_t porta : 1;
216 uint32_t portb : 1; 216 uint32_t portb : 1;
217 uint32_t portc : 1; 217 uint32_t portc : 1;
218 uint32_t portd : 1; 218 uint32_t portd : 1;
219 uint32_t porte : 1; 219 uint32_t porte : 1;
220 uint32_t _rsvd2 : 18; 220 uint32_t _rsvd2 : 18;
221 UNION_STRUCT_END; 221 UNION_STRUCT_END;
222 } scgc5; 222 } scgc5;
223 struct SIM_SCGC6_t { 223 struct SIM_SCGC6_t {
224 UNION_STRUCT_START(32); 224 UNION_STRUCT_START(32);
225 uint32_t ftfl : 1; 225 uint32_t ftfl : 1;
226 uint32_t dmamux : 1; 226 uint32_t dmamux : 1;
227 uint32_t _rsvd0 : 10; 227 uint32_t _rsvd0 : 10;
228 uint32_t spi0 : 1; 228 uint32_t spi0 : 1;
229 uint32_t _rsvd1 : 2; 229 uint32_t _rsvd1 : 2;
230 uint32_t i2s : 1; 230 uint32_t i2s : 1;
231 uint32_t _rsvd2 : 2; 231 uint32_t _rsvd2 : 2;
232 uint32_t crc : 1; 232 uint32_t crc : 1;
233 uint32_t _rsvd3 : 2; 233 uint32_t _rsvd3 : 2;
234 uint32_t usbdcd : 1; 234 uint32_t usbdcd : 1;
235 uint32_t pdb : 1; 235 uint32_t pdb : 1;
236 uint32_t pit : 1; 236 uint32_t pit : 1;
237 uint32_t ftm0 : 1; 237 uint32_t ftm0 : 1;
238 uint32_t ftm1 : 1; 238 uint32_t ftm1 : 1;
239 uint32_t _rsvd4 : 1; 239 uint32_t _rsvd4 : 1;
240 uint32_t adc0 : 1; 240 uint32_t adc0 : 1;
241 uint32_t _rsvd5 : 1; 241 uint32_t _rsvd5 : 1;
242 uint32_t rtc : 1; 242 uint32_t rtc : 1;
243 uint32_t _rsvd6 : 2; 243 uint32_t _rsvd6 : 2;
244 UNION_STRUCT_END; 244 UNION_STRUCT_END;
245 } scgc6; 245 } scgc6;
246 struct SIM_SCGC7_t { 246 struct SIM_SCGC7_t {
247 UNION_STRUCT_START(32); 247 UNION_STRUCT_START(32);
248 uint32_t _rsvd0 : 1; 248 uint32_t _rsvd0 : 1;
249 uint32_t dma : 1; 249 uint32_t dma : 1;
250 uint32_t _rsvd1 : 30; 250 uint32_t _rsvd1 : 30;
251 UNION_STRUCT_END; 251 UNION_STRUCT_END;
252 } scgc7; 252 } scgc7;
253 struct SIM_CLKDIV1_t { 253 struct SIM_CLKDIV1_t {
254 UNION_STRUCT_START(32); 254 UNION_STRUCT_START(32);
255 uint32_t _rsvd0 : 16; 255 uint32_t _rsvd0 : 16;
256 uint32_t outdiv4 : 4; 256 uint32_t outdiv4 : 4;
257 uint32_t _rsvd1 : 4; 257 uint32_t _rsvd1 : 4;
258 uint32_t outdiv2 : 4; 258 uint32_t outdiv2 : 4;
259 uint32_t outdiv1 : 4; 259 uint32_t outdiv1 : 4;
260 UNION_STRUCT_END; 260 UNION_STRUCT_END;
261 } clkdiv1; 261 } clkdiv1;
262 struct SIM_CLKDIV2_t { 262 struct SIM_CLKDIV2_t {
263 UNION_STRUCT_START(32); 263 UNION_STRUCT_START(32);
264 uint32_t usbfrac : 1; 264 uint32_t usbfrac : 1;
265 uint32_t usbdiv : 3; 265 uint32_t usbdiv : 3;
266 uint32_t _rsvd0 : 28; 266 uint32_t _rsvd0 : 28;
267 UNION_STRUCT_END; 267 UNION_STRUCT_END;
268 } clkdiv2; 268 } clkdiv2;
269 struct SIM_FCFG1_t { 269 struct SIM_FCFG1_t {
270 UNION_STRUCT_START(32); 270 UNION_STRUCT_START(32);
271 uint32_t flashdis : 1; 271 uint32_t flashdis : 1;
272 uint32_t flashdoze : 1; 272 uint32_t flashdoze : 1;
273 uint32_t _rsvd0 : 6; 273 uint32_t _rsvd0 : 6;
274 274
275 /* the following enum is analogous to enum 275 /* the following enum is analogous to enum
276 * FTFL_FLEXNVM_PARTITION in ftfl.h, but that one is padded 276 * FTFL_FLEXNVM_PARTITION in ftfl.h, but that one is padded
277 * with four 1-bits to make an 8-bit value. 277 * with four 1-bits to make an 8-bit value.
278 */ 278 */
279 enum SIM_FLEXNVM_PARTITION { 279 enum SIM_FLEXNVM_PARTITION {
280 SIM_FLEXNVM_DATA_32_EEPROM_0 = 0x0, 280 SIM_FLEXNVM_DATA_32_EEPROM_0 = 0x0,
281 SIM_FLEXNVM_DATA_24_EEPROM_8 = 0x1, 281 SIM_FLEXNVM_DATA_24_EEPROM_8 = 0x1,
282 SIM_FLEXNVM_DATA_16_EEPROM_16 = 0x2, 282 SIM_FLEXNVM_DATA_16_EEPROM_16 = 0x2,
283 SIM_FLEXNVM_DATA_8_EEPROM_24 = 0x9, 283 SIM_FLEXNVM_DATA_8_EEPROM_24 = 0x9,
284 SIM_FLEXNVM_DATA_0_EEPROM_32 = 0x3 284 SIM_FLEXNVM_DATA_0_EEPROM_32 = 0x3
285 } depart : 4; 285 } depart : 4;
286 286
287 uint32_t _rsvd1 : 4; 287 uint32_t _rsvd1 : 4;
288 enum { 288 enum {
289 SIM_EESIZE_2KB = 3, 289 SIM_EESIZE_2KB = 3,
290 SIM_EESIZE_1KB = 4, 290 SIM_EESIZE_1KB = 4,
291 SIM_EESIZE_512B = 5, 291 SIM_EESIZE_512B = 5,
292 SIM_EESIZE_256B = 6, 292 SIM_EESIZE_256B = 6,
293 SIM_EESIZE_128B = 7, 293 SIM_EESIZE_128B = 7,
294 SIM_EESIZE_64B = 8, 294 SIM_EESIZE_64B = 8,
295 SIM_EESIZE_32B = 9, 295 SIM_EESIZE_32B = 9,
296 SIM_EESIZE_0B = 15 296 SIM_EESIZE_0B = 15
297 } eesize : 4; 297 } eesize : 4;
298 uint32_t _rsvd2 : 4; 298 uint32_t _rsvd2 : 4;
299 enum { 299 enum {
300 SIM_PFSIZE_32KB = 3, 300 SIM_PFSIZE_32KB = 3,
301 SIM_PFSIZE_64KB = 5, 301 SIM_PFSIZE_64KB = 5,
302 SIM_PFSIZE_128KB = 7 302 SIM_PFSIZE_128KB = 7
303 } pfsize : 4; 303 } pfsize : 4;
304 enum { 304 enum {
305 SIM_NVMSIZE_0KB = 0, 305 SIM_NVMSIZE_0KB = 0,
306 SIM_NVMSIZE_32KB = 3 306 SIM_NVMSIZE_32KB = 3
307 } nvmsize : 4; 307 } nvmsize : 4;
308 UNION_STRUCT_END; 308 UNION_STRUCT_END;
309 } fcfg1; 309 } fcfg1;
310 struct SIM_FCFG2_t { 310 struct SIM_FCFG2_t {
311 UNION_STRUCT_START(32); 311 UNION_STRUCT_START(32);
312 uint32_t _rsvd0 : 16; 312 uint32_t _rsvd0 : 16;
313 uint32_t maxaddr1 : 7; 313 uint32_t maxaddr1 : 7;
314 enum { 314 enum {
315 SIM_PFLSH_FLEXNVM = 0, 315 SIM_PFLSH_FLEXNVM = 0,
316 SIM_PFLSH_PROGRAM = 1 316 SIM_PFLSH_PROGRAM = 1
317 } pflsh : 1; 317 } pflsh : 1;
318 uint32_t maxaddr0 : 7; 318 uint32_t maxaddr0 : 7;
319 uint32_t _rsvd1 : 1; 319 uint32_t _rsvd1 : 1;
320 UNION_STRUCT_END; 320 UNION_STRUCT_END;
321 } fcfg2; 321 } fcfg2;
322 uint32_t uidh; 322 uint32_t uidh;
323 uint32_t uidmh; 323 uint32_t uidmh;
324 uint32_t uidml; 324 uint32_t uidml;
325 uint32_t uidl; 325 uint32_t uidl;
326 }; 326 };
327 CTASSERT_SIZE_BYTE(struct SIM_t, 0x1064); 327 CTASSERT_SIZE_BYTE(struct SIM_t, 0x1064);
328 328
329 extern volatile struct SIM_t SIM; 329 extern volatile struct SIM_t SIM;
330 330