Mercurial > louis > kiibohd-controller
changeset 327:f7b14e25ca5b
Merge pull request #27 from smasher816/wakeup-devel
Inital Remote Wakeup Support
| author | Jacob Alexander <haata@kiibohd.com> |
|---|---|
| date | Fri, 12 Jun 2015 18:31:55 -0700 |
| parents | b2c8581307bc (diff) 05a09eda53fb (current diff) |
| children | f6b7c1f0f8a1 |
| files | Output/pjrcUSB/arm/usb_dev.c Output/pjrcUSB/arm/usb_dev.h |
| diffstat | 66 files changed, 6334 insertions(+), 3948 deletions(-) [+] |
line wrap: on
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--- a/Bootloader/CMakeLists.txt Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/CMakeLists.txt Fri Jun 12 18:31:55 2015 -0700 @@ -21,7 +21,7 @@ #| set( CHIP "mk20dx128vlf5" # McHCK mk20dx128vlf5 -# "mk20dx256vlh7" # Kiibohd-dfu mk20dx256vlh7 +# "mk20dx256vlh7" # Kiibohd-dfu mk20dx256vlh7 ) @@ -34,8 +34,8 @@ #| Stick with gcc unless you know what you're doing #| Currently only arm is supported with clang set( COMPILER - "gcc" # arm-none-eabi-gcc / avr-gcc - Default -# "clang" # arm-none-eabi + "gcc" # arm-none-eabi-gcc / avr-gcc - Default +# "clang" # arm-none-eabi CACHE STRING "Compiler Type" )
--- a/Bootloader/dfu.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/dfu.c Fri Jun 12 18:31:55 2015 -0700 @@ -26,146 +26,146 @@ void dfu_write_done( enum dfu_status err, struct dfu_ctx *ctx ) { - ctx->status = err; - if (ctx->status == DFU_STATUS_OK) { - switch (ctx->state) { - case DFU_STATE_dfuDNBUSY: - ctx->state = DFU_STATE_dfuDNLOAD_IDLE; - break; - default: - break; - } - } else { - ctx->state = DFU_STATE_dfuERROR; - } + ctx->status = err; + if (ctx->status == DFU_STATUS_OK) { + switch (ctx->state) { + case DFU_STATE_dfuDNBUSY: + ctx->state = DFU_STATE_dfuDNLOAD_IDLE; + break; + default: + break; + } + } else { + ctx->state = DFU_STATE_dfuERROR; + } } static void dfu_dnload_complete( void *buf, ssize_t len, void *cbdata ) { - struct dfu_ctx *ctx = cbdata; + struct dfu_ctx *ctx = cbdata; - if (len > 0) - ctx->state = DFU_STATE_dfuDNBUSY; - else - ctx->state = DFU_STATE_dfuMANIFEST; - ctx->status = ctx->finish_write(buf, ctx->off, len); - ctx->off += len; - ctx->len = len; + if (len > 0) + ctx->state = DFU_STATE_dfuDNBUSY; + else + ctx->state = DFU_STATE_dfuMANIFEST; + ctx->status = ctx->finish_write(buf, ctx->off, len); + ctx->off += len; + ctx->len = len; - if (ctx->status != DFU_STATUS_async) - dfu_write_done(ctx->status, ctx); + if (ctx->status != DFU_STATUS_async) + dfu_write_done(ctx->status, ctx); - usb_handle_control_status(ctx->state == DFU_STATE_dfuERROR); + usb_handle_control_status(ctx->state == DFU_STATE_dfuERROR); } static void dfu_reset_system( void *buf, ssize_t len, void *cbdata ) { - SOFTWARE_RESET(); + SOFTWARE_RESET(); } static int dfu_handle_control( struct usb_ctrl_req_t *req, void *data ) { - struct dfu_ctx *ctx = data; - int fail = 1; + struct dfu_ctx *ctx = data; + int fail = 1; - switch ((enum dfu_ctrl_req_code)req->bRequest) { - case USB_CTRL_REQ_DFU_DNLOAD: { - void *buf; + switch ((enum dfu_ctrl_req_code)req->bRequest) { + case USB_CTRL_REQ_DFU_DNLOAD: { + void *buf; - switch (ctx->state) { - case DFU_STATE_dfuIDLE: - ctx->off = 0; - break; - case DFU_STATE_dfuDNLOAD_IDLE: - break; - default: - goto err; - } + switch (ctx->state) { + case DFU_STATE_dfuIDLE: + ctx->off = 0; + break; + case DFU_STATE_dfuDNLOAD_IDLE: + break; + default: + goto err; + } - /** - * XXX we are not allowed to STALL here, and we need to eat all transferred data. - * better not allow setup_write to break the protocol. - */ - ctx->status = ctx->setup_write(ctx->off, req->wLength, &buf); - if (ctx->status != DFU_STATUS_OK) { - ctx->state = DFU_STATE_dfuERROR; - goto err_have_status; - } + /** + * XXX we are not allowed to STALL here, and we need to eat all transferred data. + * better not allow setup_write to break the protocol. + */ + ctx->status = ctx->setup_write(ctx->off, req->wLength, &buf); + if (ctx->status != DFU_STATUS_OK) { + ctx->state = DFU_STATE_dfuERROR; + goto err_have_status; + } - if (req->wLength > 0) - usb_ep0_rx(buf, req->wLength, dfu_dnload_complete, ctx); - else - dfu_dnload_complete(NULL, 0, ctx); - goto out_no_status; - } - case USB_CTRL_REQ_DFU_GETSTATUS: { - struct dfu_status_t st; + if (req->wLength > 0) + usb_ep0_rx(buf, req->wLength, dfu_dnload_complete, ctx); + else + dfu_dnload_complete(NULL, 0, ctx); + goto out_no_status; + } + case USB_CTRL_REQ_DFU_GETSTATUS: { + struct dfu_status_t st; - st.bState = ctx->state; - st.bStatus = ctx->status; - st.bwPollTimeout = 1000; /* XXX */ - /** - * If we're in DFU_STATE_dfuMANIFEST, we just finished - * the download, and we're just about to send our last - * status report. Once the report has been sent, go - * and reset the system to put the new firmware into - * effect. - */ - usb_ep0_tx_cp(&st, sizeof(st), req->wLength, NULL, NULL); - if (ctx->state == DFU_STATE_dfuMANIFEST) { - usb_handle_control_status_cb(dfu_reset_system); - goto out_no_status; - } - break; - } - case USB_CTRL_REQ_DFU_CLRSTATUS: - ctx->state = DFU_STATE_dfuIDLE; - ctx->status = DFU_STATUS_OK; - break; - case USB_CTRL_REQ_DFU_GETSTATE: { - uint8_t st = ctx->state; - usb_ep0_tx_cp(&st, sizeof(st), req->wLength, NULL, NULL); - break; - } - case USB_CTRL_REQ_DFU_ABORT: - switch (ctx->state) { - case DFU_STATE_dfuIDLE: - case DFU_STATE_dfuDNLOAD_IDLE: - /* case DFU_STATE_dfuUPLOAD_IDLE: */ - ctx->state = DFU_STATE_dfuIDLE; - break; - default: - goto err; - } - break; - /* case USB_CTRL_REQ_DFU_UPLOAD: */ - default: - return (0); - } + st.bState = ctx->state; + st.bStatus = ctx->status; + st.bwPollTimeout = 1000; /* XXX */ + /** + * If we're in DFU_STATE_dfuMANIFEST, we just finished + * the download, and we're just about to send our last + * status report. Once the report has been sent, go + * and reset the system to put the new firmware into + * effect. + */ + usb_ep0_tx_cp(&st, sizeof(st), req->wLength, NULL, NULL); + if (ctx->state == DFU_STATE_dfuMANIFEST) { + usb_handle_control_status_cb(dfu_reset_system); + goto out_no_status; + } + break; + } + case USB_CTRL_REQ_DFU_CLRSTATUS: + ctx->state = DFU_STATE_dfuIDLE; + ctx->status = DFU_STATUS_OK; + break; + case USB_CTRL_REQ_DFU_GETSTATE: { + uint8_t st = ctx->state; + usb_ep0_tx_cp(&st, sizeof(st), req->wLength, NULL, NULL); + break; + } + case USB_CTRL_REQ_DFU_ABORT: + switch (ctx->state) { + case DFU_STATE_dfuIDLE: + case DFU_STATE_dfuDNLOAD_IDLE: + /* case DFU_STATE_dfuUPLOAD_IDLE: */ + ctx->state = DFU_STATE_dfuIDLE; + break; + default: + goto err; + } + break; + /* case USB_CTRL_REQ_DFU_UPLOAD: */ + default: + return (0); + } - fail = 0; - goto out; + fail = 0; + goto out; err: - ctx->status = DFU_STATUS_errSTALLEDPKT; + ctx->status = DFU_STATUS_errSTALLEDPKT; err_have_status: - ctx->state = DFU_STATE_dfuERROR; + ctx->state = DFU_STATE_dfuERROR; out: - usb_handle_control_status(fail); + usb_handle_control_status(fail); out_no_status: - return (1); + return (1); } void dfu_init( dfu_setup_write_t setup_write, dfu_finish_write_t finish_write, struct dfu_ctx *ctx ) { - ctx->state = DFU_STATE_dfuIDLE; - ctx->setup_write = setup_write; - ctx->finish_write = finish_write; - usb_attach_function(&dfu_function, &ctx->header); + ctx->state = DFU_STATE_dfuIDLE; + ctx->setup_write = setup_write; + ctx->finish_write = finish_write; + usb_attach_function(&dfu_function, &ctx->header); } const struct usbd_function dfu_function = { - .control = dfu_handle_control, - .interface_count = USB_FUNCTION_DFU_IFACE_COUNT, + .control = dfu_handle_control, + .interface_count = USB_FUNCTION_DFU_IFACE_COUNT, };
--- a/Bootloader/dfu.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/dfu.h Fri Jun 12 18:31:55 2015 -0700 @@ -30,104 +30,104 @@ #ifndef USB_DFU_TRANSFER_SIZE -#define USB_DFU_TRANSFER_SIZE FLASH_SECTOR_SIZE +#define USB_DFU_TRANSFER_SIZE FLASH_SECTOR_SIZE #endif #define USB_FUNCTION_DESC_DFU_DECL \ - struct dfu_function_desc + struct dfu_function_desc -#define USB_FUNCTION_DFU_IFACE_COUNT 1 -#define USB_FUNCTION_DFU_RX_EP_COUNT 0 -#define USB_FUNCTION_DFU_TX_EP_COUNT 0 +#define USB_FUNCTION_DFU_IFACE_COUNT 1 +#define USB_FUNCTION_DFU_RX_EP_COUNT 0 +#define USB_FUNCTION_DFU_TX_EP_COUNT 0 // ----- Macros ----- #define USB_FUNCTION_DESC_DFU(state...) \ - { \ - .iface = { \ - .bLength = sizeof(struct usb_desc_iface_t), \ - .bDescriptorType = USB_DESC_IFACE, \ - .bInterfaceNumber = USB_FUNCTION_IFACE(0, state), \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 0, \ - .bInterfaceClass = USB_DEV_CLASS_APP, \ - .bInterfaceSubClass = USB_DEV_SUBCLASS_APP_DFU, \ - .bInterfaceProtocol = USB_DEV_PROTO_DFU_DFU, \ - .iInterface = 0, \ - }, \ - .dfu = { \ - .bLength = sizeof(struct dfu_desc_functional), \ - .bDescriptorType = { \ - .id = 0x1, \ - .type_type = USB_DESC_TYPE_CLASS \ - }, \ - .will_detach = 1, \ - .manifestation_tolerant = 0, \ - .can_upload = 0, \ - .can_download = 1, \ - .wDetachTimeOut = 0, \ - .wTransferSize = USB_DFU_TRANSFER_SIZE, \ - .bcdDFUVersion = { .maj = 1, .min = 1 } \ - } \ - } + { \ + .iface = { \ + .bLength = sizeof(struct usb_desc_iface_t), \ + .bDescriptorType = USB_DESC_IFACE, \ + .bInterfaceNumber = USB_FUNCTION_IFACE(0, state), \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 0, \ + .bInterfaceClass = USB_DEV_CLASS_APP, \ + .bInterfaceSubClass = USB_DEV_SUBCLASS_APP_DFU, \ + .bInterfaceProtocol = USB_DEV_PROTO_DFU_DFU, \ + .iInterface = 0, \ + }, \ + .dfu = { \ + .bLength = sizeof(struct dfu_desc_functional), \ + .bDescriptorType = { \ + .id = 0x1, \ + .type_type = USB_DESC_TYPE_CLASS \ + }, \ + .will_detach = 1, \ + .manifestation_tolerant = 0, \ + .can_upload = 0, \ + .can_download = 1, \ + .wDetachTimeOut = 0, \ + .wTransferSize = USB_DFU_TRANSFER_SIZE, \ + .bcdDFUVersion = { .maj = 1, .min = 1 } \ + } \ + } // ----- Enumerations ----- enum dfu_dev_subclass { - USB_DEV_SUBCLASS_APP_DFU = 0x01 + USB_DEV_SUBCLASS_APP_DFU = 0x01 }; enum dfu_dev_proto { - USB_DEV_PROTO_DFU_APP = 0x01, - USB_DEV_PROTO_DFU_DFU = 0x02 + USB_DEV_PROTO_DFU_APP = 0x01, + USB_DEV_PROTO_DFU_DFU = 0x02 }; enum dfu_ctrl_req_code { - USB_CTRL_REQ_DFU_DETACH = 0, - USB_CTRL_REQ_DFU_DNLOAD = 1, - USB_CTRL_REQ_DFU_UPLOAD = 2, - USB_CTRL_REQ_DFU_GETSTATUS = 3, - USB_CTRL_REQ_DFU_CLRSTATUS = 4, - USB_CTRL_REQ_DFU_GETSTATE = 5, - USB_CTRL_REQ_DFU_ABORT = 6 + USB_CTRL_REQ_DFU_DETACH = 0, + USB_CTRL_REQ_DFU_DNLOAD = 1, + USB_CTRL_REQ_DFU_UPLOAD = 2, + USB_CTRL_REQ_DFU_GETSTATUS = 3, + USB_CTRL_REQ_DFU_CLRSTATUS = 4, + USB_CTRL_REQ_DFU_GETSTATE = 5, + USB_CTRL_REQ_DFU_ABORT = 6 }; enum dfu_status { - DFU_STATUS_async = 0xff, - DFU_STATUS_OK = 0x00, - DFU_STATUS_errTARGET = 0x01, - DFU_STATUS_errFILE = 0x02, - DFU_STATUS_errWRITE = 0x03, - DFU_STATUS_errERASE = 0x04, - DFU_STATUS_errCHECK_ERASED = 0x05, - DFU_STATUS_errPROG = 0x06, - DFU_STATUS_errVERIFY = 0x07, - DFU_STATUS_errADDRESS = 0x08, - DFU_STATUS_errNOTDONE = 0x09, - DFU_STATUS_errFIRMWARE = 0x0a, - DFU_STATUS_errVENDOR = 0x0b, - DFU_STATUS_errUSBR = 0x0c, - DFU_STATUS_errPOR = 0x0d, - DFU_STATUS_errUNKNOWN = 0x0e, - DFU_STATUS_errSTALLEDPKT = 0x0f + DFU_STATUS_async = 0xff, + DFU_STATUS_OK = 0x00, + DFU_STATUS_errTARGET = 0x01, + DFU_STATUS_errFILE = 0x02, + DFU_STATUS_errWRITE = 0x03, + DFU_STATUS_errERASE = 0x04, + DFU_STATUS_errCHECK_ERASED = 0x05, + DFU_STATUS_errPROG = 0x06, + DFU_STATUS_errVERIFY = 0x07, + DFU_STATUS_errADDRESS = 0x08, + DFU_STATUS_errNOTDONE = 0x09, + DFU_STATUS_errFIRMWARE = 0x0a, + DFU_STATUS_errVENDOR = 0x0b, + DFU_STATUS_errUSBR = 0x0c, + DFU_STATUS_errPOR = 0x0d, + DFU_STATUS_errUNKNOWN = 0x0e, + DFU_STATUS_errSTALLEDPKT = 0x0f }; enum dfu_state { - DFU_STATE_appIDLE = 0, - DFU_STATE_appDETACH = 1, - DFU_STATE_dfuIDLE = 2, - DFU_STATE_dfuDNLOAD_SYNC = 3, - DFU_STATE_dfuDNBUSY = 4, - DFU_STATE_dfuDNLOAD_IDLE = 5, - DFU_STATE_dfuMANIFEST_SYNC = 6, - DFU_STATE_dfuMANIFEST = 7, - DFU_STATE_dfuMANIFEST_WAIT_RESET = 8, - DFU_STATE_dfuUPLOAD_IDLE = 9, - DFU_STATE_dfuERROR = 10 + DFU_STATE_appIDLE = 0, + DFU_STATE_appDETACH = 1, + DFU_STATE_dfuIDLE = 2, + DFU_STATE_dfuDNLOAD_SYNC = 3, + DFU_STATE_dfuDNBUSY = 4, + DFU_STATE_dfuDNLOAD_IDLE = 5, + DFU_STATE_dfuMANIFEST_SYNC = 6, + DFU_STATE_dfuMANIFEST = 7, + DFU_STATE_dfuMANIFEST_WAIT_RESET = 8, + DFU_STATE_dfuUPLOAD_IDLE = 9, + DFU_STATE_dfuERROR = 10 }; @@ -135,10 +135,10 @@ // ----- Structs ----- struct dfu_status_t { - enum dfu_status bStatus : 8; - uint32_t bwPollTimeout : 24; - enum dfu_state bState : 8; - uint8_t iString; + enum dfu_status bStatus : 8; + uint32_t bwPollTimeout : 24; + enum dfu_state bState : 8; + uint8_t iString; } __packed; CTASSERT_SIZE_BYTE(struct dfu_status_t, 6); @@ -148,38 +148,38 @@ typedef void (*dfu_detach_t)(void); struct dfu_ctx { - struct usbd_function_ctx_header header; - enum dfu_state state; - enum dfu_status status; - dfu_setup_write_t setup_write; - dfu_finish_write_t finish_write; - size_t off; - size_t len; + struct usbd_function_ctx_header header; + enum dfu_state state; + enum dfu_status status; + dfu_setup_write_t setup_write; + dfu_finish_write_t finish_write; + size_t off; + size_t len; }; struct dfu_desc_functional { - uint8_t bLength; - struct usb_desc_type_t bDescriptorType; /* = class DFU/0x1 FUNCTIONAL */ - union { - struct { - uint8_t can_download : 1; - uint8_t can_upload : 1; - uint8_t manifestation_tolerant : 1; - uint8_t will_detach : 1; - uint8_t _rsvd0 : 4; - }; - uint8_t bmAttributes; - }; - uint16_t wDetachTimeOut; - uint16_t wTransferSize; - struct usb_bcd_t bcdDFUVersion; + uint8_t bLength; + struct usb_desc_type_t bDescriptorType; /* = class DFU/0x1 FUNCTIONAL */ + union { + struct { + uint8_t can_download : 1; + uint8_t can_upload : 1; + uint8_t manifestation_tolerant : 1; + uint8_t will_detach : 1; + uint8_t _rsvd0 : 4; + }; + uint8_t bmAttributes; + }; + uint16_t wDetachTimeOut; + uint16_t wTransferSize; + struct usb_bcd_t bcdDFUVersion; } __packed; CTASSERT_SIZE_BYTE(struct dfu_desc_functional, 9); struct dfu_function_desc { - struct usb_desc_iface_t iface; - struct dfu_desc_functional dfu; + struct usb_desc_iface_t iface; + struct dfu_desc_functional dfu; };
--- a/Bootloader/flash.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/flash.c Fri Jun 12 18:31:55 2015 -0700 @@ -33,60 +33,60 @@ __attribute__((section(".ramtext.ftfl_submit_cmd"), long_call)) int ftfl_submit_cmd(void) { - FTFL.fstat.raw = ((struct FTFL_FSTAT_t){ - .ccif = 1, - .rdcolerr = 1, - .accerr = 1, - .fpviol = 1 - }).raw; - struct FTFL_FSTAT_t stat; - while (!(stat = FTFL.fstat).ccif) - /* NOTHING */; /* XXX maybe WFI? */ - return (!!stat.mgstat0); + FTFL.fstat.raw = ((struct FTFL_FSTAT_t){ + .ccif = 1, + .rdcolerr = 1, + .accerr = 1, + .fpviol = 1 + }).raw; + struct FTFL_FSTAT_t stat; + while (!(stat = FTFL.fstat).ccif) + /* NOTHING */; /* XXX maybe WFI? */ + return (!!stat.mgstat0); } int flash_prepare_flashing(void) { - /* switch to FlexRAM */ - if (!FTFL.fcnfg.ramrdy) { - FTFL.fccob.set_flexram.fcmd = FTFL_FCMD_SET_FLEXRAM; - FTFL.fccob.set_flexram.flexram_function = FTFL_FLEXRAM_RAM; - return (ftfl_submit_cmd()); - } - return (0); + /* switch to FlexRAM */ + if (!FTFL.fcnfg.ramrdy) { + FTFL.fccob.set_flexram.fcmd = FTFL_FCMD_SET_FLEXRAM; + FTFL.fccob.set_flexram.flexram_function = FTFL_FLEXRAM_RAM; + return (ftfl_submit_cmd()); + } + return (0); } int flash_erase_sector(uintptr_t addr) { - if (addr < (uintptr_t)&_app_rom && - flash_ALLOW_BRICKABLE_ADDRESSES != 0x00023420) - return (-1); - FTFL.fccob.erase.fcmd = FTFL_FCMD_ERASE_SECTOR; - FTFL.fccob.erase.addr = addr; - return (ftfl_submit_cmd()); + if (addr < (uintptr_t)&_app_rom && + flash_ALLOW_BRICKABLE_ADDRESSES != 0x00023420) + return (-1); + FTFL.fccob.erase.fcmd = FTFL_FCMD_ERASE_SECTOR; + FTFL.fccob.erase.addr = addr; + return (ftfl_submit_cmd()); } int flash_program_section(uintptr_t addr, size_t num_words) { - FTFL.fccob.program_section.fcmd = FTFL_FCMD_PROGRAM_SECTION; - FTFL.fccob.program_section.addr = addr; - FTFL.fccob.program_section.num_words = num_words; - return (ftfl_submit_cmd()); + FTFL.fccob.program_section.fcmd = FTFL_FCMD_PROGRAM_SECTION; + FTFL.fccob.program_section.addr = addr; + FTFL.fccob.program_section.num_words = num_words; + return (ftfl_submit_cmd()); } int flash_program_sector(uintptr_t addr, size_t len) { - return (len != FLASH_SECTOR_SIZE || - (addr & (FLASH_SECTOR_SIZE - 1)) != 0 || - flash_erase_sector(addr) || - flash_program_section(addr, FLASH_SECTOR_SIZE/4)); + return (len != FLASH_SECTOR_SIZE || + (addr & (FLASH_SECTOR_SIZE - 1)) != 0 || + flash_erase_sector(addr) || + flash_program_section(addr, FLASH_SECTOR_SIZE/4)); } void *flash_get_staging_area(uintptr_t addr, size_t len) { - if ((addr & (FLASH_SECTOR_SIZE - 1)) != 0 || - len != FLASH_SECTOR_SIZE) - return (NULL); - return (FlexRAM); + if ((addr & (FLASH_SECTOR_SIZE - 1)) != 0 || + len != FLASH_SECTOR_SIZE) + return (NULL); + return (FlexRAM); }
--- a/Bootloader/ftfl.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/ftfl.h Fri Jun 12 18:31:55 2015 -0700 @@ -27,60 +27,60 @@ // ----- Structs ----- struct FTFL_FSTAT_t { - UNION_STRUCT_START(8); - uint8_t mgstat0 : 1; - uint8_t _rsvd0 : 3; - uint8_t fpviol : 1; - uint8_t accerr : 1; - uint8_t rdcolerr : 1; - uint8_t ccif : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t mgstat0 : 1; + uint8_t _rsvd0 : 3; + uint8_t fpviol : 1; + uint8_t accerr : 1; + uint8_t rdcolerr : 1; + uint8_t ccif : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct FTFL_FSTAT_t, 8); struct FTFL_FCNFG_t { - UNION_STRUCT_START(8); - uint8_t eeerdy : 1; - uint8_t ramrdy : 1; - uint8_t pflsh : 1; - uint8_t _rsvd0 : 1; - uint8_t erssusp : 1; - uint8_t ersareq : 1; - uint8_t rdcollie : 1; - uint8_t ccie : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t eeerdy : 1; + uint8_t ramrdy : 1; + uint8_t pflsh : 1; + uint8_t _rsvd0 : 1; + uint8_t erssusp : 1; + uint8_t ersareq : 1; + uint8_t rdcollie : 1; + uint8_t ccie : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct FTFL_FCNFG_t, 8); struct FTFL_FSEC_t { - UNION_STRUCT_START(8); - enum { - FTFL_FSEC_SEC_UNSECURE = 2, - FTFL_FSEC_SEC_SECURE = 3 - } sec : 2; - enum { - FTFL_FSEC_FSLACC_DENY = 1, - FTFL_FSEC_FSLACC_GRANT = 3 - } fslacc : 2; - enum { - FTFL_FSEC_MEEN_DISABLE = 2, - FTFL_FSEC_MEEN_ENABLE = 3 - } meen : 2; - enum { - FTFL_FSEC_KEYEN_DISABLE = 1, - FTFL_FSEC_KEYEN_ENABLE = 2 - } keyen : 2; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + enum { + FTFL_FSEC_SEC_UNSECURE = 2, + FTFL_FSEC_SEC_SECURE = 3 + } sec : 2; + enum { + FTFL_FSEC_FSLACC_DENY = 1, + FTFL_FSEC_FSLACC_GRANT = 3 + } fslacc : 2; + enum { + FTFL_FSEC_MEEN_DISABLE = 2, + FTFL_FSEC_MEEN_ENABLE = 3 + } meen : 2; + enum { + FTFL_FSEC_KEYEN_DISABLE = 1, + FTFL_FSEC_KEYEN_ENABLE = 2 + } keyen : 2; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct FTFL_FSEC_t, 8); struct FTFL_FOPT_t { - UNION_STRUCT_START(8); - uint8_t lpboot : 1; - uint8_t ezport_dis : 1; - uint8_t nmi_dis : 1; - uint8_t _rsvd0 : 5; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t lpboot : 1; + uint8_t ezport_dis : 1; + uint8_t nmi_dis : 1; + uint8_t _rsvd0 : 5; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct FTFL_FOPT_t, 8); @@ -90,151 +90,151 @@ * some that is little endian. */ union FTFL_FCCOB_t { - struct ftfl_generic { - uint32_t addr : 24; - enum FTFL_FCMD { - FTFL_FCMD_READ_1s_BLOCK = 0x00, - FTFL_FCMD_READ_1s_SECTION = 0x01, - FTFL_FCMD_PROGRAM_CHECK = 0x02, - FTFL_FCMD_READ_RESOURCE = 0x03, - FTFL_FCMD_PROGRAM_LONGWORD = 0x06, - FTFL_FCMD_ERASE_BLOCK = 0x08, - FTFL_FCMD_ERASE_SECTOR = 0x09, - FTFL_FCMD_PROGRAM_SECTION = 0x0b, - FTFL_FCMD_READ_1s_ALL_BLOCKS = 0x40, - FTFL_FCMD_READ_ONCE = 0x41, - FTFL_FCMD_PROGRAM_ONCE = 0x43, - FTFL_FCMD_ERASE_ALL_BLOCKS = 0x44, - FTFL_FCMD_VERIFY_KEY = 0x45, - FTFL_FCMD_PROGRAM_PARTITION = 0x80, - FTFL_FCMD_SET_FLEXRAM = 0x81 - } fcmd : 8; - uint8_t data_be[8]; - } generic; - struct { - uint32_t addr : 24; - enum FTFL_FCMD fcmd : 8; - uint8_t _rsvd0[3]; - enum FTFL_MARGIN_CHOICE { - FTFL_MARGIN_NORMAL = 0x00, - FTFL_MARGIN_USER = 0x01, - FTFL_MARGIN_FACTORY = 0x02 - } margin : 8; - } read_1s_block; - struct ftfl_data_num_words { - uint32_t addr : 24; - enum FTFL_FCMD fcmd : 8; - uint8_t _rsvd0; - enum FTFL_MARGIN_CHOICE margin : 8; - uint16_t num_words; - } read_1s_section; - struct { - uint32_t addr : 24; - enum FTFL_FCMD fcmd : 8; - uint8_t _rsvd0[3]; - enum FTFL_MARGIN_CHOICE margin : 8; - uint8_t data_be[4]; - } program_check; - struct { - uint32_t addr : 24; - enum FTFL_FCMD fcmd : 8; - uint32_t data; - uint8_t _rsvd0[3]; - enum FTFL_RESOURCE_SELECT { - FTFL_RESOURCE_IFR = 0x00, - FTFL_RESOURCE_VERSION = 0x01 - } resource_select : 8; - } read_resource; - struct { - uint32_t addr : 24; - enum FTFL_FCMD fcmd : 8; - uint8_t data_be[4]; - } program_longword; - struct { - uint32_t addr : 24; - enum FTFL_FCMD fcmd : 8; - } erase; - struct ftfl_data_num_words program_section; - struct { - uint8_t _rsvd0[2]; - enum FTFL_MARGIN_CHOICE margin : 8; - enum FTFL_FCMD fcmd : 8; - } read_1s_all_blocks; - struct ftfl_cmd_once { - uint8_t _rsvd0[2]; - uint8_t idx; - enum FTFL_FCMD fcmd : 8; - uint8_t data_be[4]; - } read_once; - struct ftfl_cmd_once program_once; - struct { - uint8_t _rsvd0[3]; - enum FTFL_FCMD fcmd : 8; - } erase_all; - struct { - uint8_t _rsvd0[3]; - enum FTFL_FCMD fcmd : 8; - uint8_t key_be[8]; - } verify_key; - struct { - uint8_t _rsvd0[3]; - enum FTFL_FCMD fcmd : 8; - uint8_t _rsvd1[2]; + struct ftfl_generic { + uint32_t addr : 24; + enum FTFL_FCMD { + FTFL_FCMD_READ_1s_BLOCK = 0x00, + FTFL_FCMD_READ_1s_SECTION = 0x01, + FTFL_FCMD_PROGRAM_CHECK = 0x02, + FTFL_FCMD_READ_RESOURCE = 0x03, + FTFL_FCMD_PROGRAM_LONGWORD = 0x06, + FTFL_FCMD_ERASE_BLOCK = 0x08, + FTFL_FCMD_ERASE_SECTOR = 0x09, + FTFL_FCMD_PROGRAM_SECTION = 0x0b, + FTFL_FCMD_READ_1s_ALL_BLOCKS = 0x40, + FTFL_FCMD_READ_ONCE = 0x41, + FTFL_FCMD_PROGRAM_ONCE = 0x43, + FTFL_FCMD_ERASE_ALL_BLOCKS = 0x44, + FTFL_FCMD_VERIFY_KEY = 0x45, + FTFL_FCMD_PROGRAM_PARTITION = 0x80, + FTFL_FCMD_SET_FLEXRAM = 0x81 + } fcmd : 8; + uint8_t data_be[8]; + } generic; + struct { + uint32_t addr : 24; + enum FTFL_FCMD fcmd : 8; + uint8_t _rsvd0[3]; + enum FTFL_MARGIN_CHOICE { + FTFL_MARGIN_NORMAL = 0x00, + FTFL_MARGIN_USER = 0x01, + FTFL_MARGIN_FACTORY = 0x02 + } margin : 8; + } read_1s_block; + struct ftfl_data_num_words { + uint32_t addr : 24; + enum FTFL_FCMD fcmd : 8; + uint8_t _rsvd0; + enum FTFL_MARGIN_CHOICE margin : 8; + uint16_t num_words; + } read_1s_section; + struct { + uint32_t addr : 24; + enum FTFL_FCMD fcmd : 8; + uint8_t _rsvd0[3]; + enum FTFL_MARGIN_CHOICE margin : 8; + uint8_t data_be[4]; + } program_check; + struct { + uint32_t addr : 24; + enum FTFL_FCMD fcmd : 8; + uint32_t data; + uint8_t _rsvd0[3]; + enum FTFL_RESOURCE_SELECT { + FTFL_RESOURCE_IFR = 0x00, + FTFL_RESOURCE_VERSION = 0x01 + } resource_select : 8; + } read_resource; + struct { + uint32_t addr : 24; + enum FTFL_FCMD fcmd : 8; + uint8_t data_be[4]; + } program_longword; + struct { + uint32_t addr : 24; + enum FTFL_FCMD fcmd : 8; + } erase; + struct ftfl_data_num_words program_section; + struct { + uint8_t _rsvd0[2]; + enum FTFL_MARGIN_CHOICE margin : 8; + enum FTFL_FCMD fcmd : 8; + } read_1s_all_blocks; + struct ftfl_cmd_once { + uint8_t _rsvd0[2]; + uint8_t idx; + enum FTFL_FCMD fcmd : 8; + uint8_t data_be[4]; + } read_once; + struct ftfl_cmd_once program_once; + struct { + uint8_t _rsvd0[3]; + enum FTFL_FCMD fcmd : 8; + } erase_all; + struct { + uint8_t _rsvd0[3]; + enum FTFL_FCMD fcmd : 8; + uint8_t key_be[8]; + } verify_key; + struct { + uint8_t _rsvd0[3]; + enum FTFL_FCMD fcmd : 8; + uint8_t _rsvd1[2]; - /* the following enum is analogous to enum - * SIM_FLEXNVM_PARTITION in sim.h, but this one is padded - * with four 1-bits to make an 8-bit value. - */ + /* the following enum is analogous to enum + * SIM_FLEXNVM_PARTITION in sim.h, but this one is padded + * with four 1-bits to make an 8-bit value. + */ - enum FTFL_FLEXNVM_PARTITION { - FTFL_FLEXNVM_DATA_32_EEPROM_0 = 0xF0, - FTFL_FLEXNVM_DATA_24_EEPROM_8 = 0xF1, - FTFL_FLEXNVM_DATA_16_EEPROM_16 = 0xF2, - FTFL_FLEXNVM_DATA_8_EEPROM_24 = 0xF9, - FTFL_FLEXNVM_DATA_0_EEPROM_32 = 0xF3 - } flexnvm_partition : 8; - enum FTFL_EEPROM_SIZE { - FTFL_EEPROM_SIZE_0 = 0x3f, - FTFL_EEPROM_SIZE_32 = 0x39, - FTFL_EEPROM_SIZE_64 = 0x38, - FTFL_EEPROM_SIZE_128 = 0x37, - FTFL_EEPROM_SIZE_256 = 0x36, - FTFL_EEPROM_SIZE_512 = 0x35, - FTFL_EEPROM_SIZE_1024 = 0x34, - FTFL_EEPROM_SIZE_2048 = 0x33 - } eeprom_size : 8; - } program_partition; - struct { - uint8_t _rsvd0[2]; - enum FTFL_FLEXRAM_FUNCTION { - FTFL_FLEXRAM_EEPROM = 0x00, - FTFL_FLEXRAM_RAM = 0xff - } flexram_function : 8; - enum FTFL_FCMD fcmd : 8; - } set_flexram; + enum FTFL_FLEXNVM_PARTITION { + FTFL_FLEXNVM_DATA_32_EEPROM_0 = 0xF0, + FTFL_FLEXNVM_DATA_24_EEPROM_8 = 0xF1, + FTFL_FLEXNVM_DATA_16_EEPROM_16 = 0xF2, + FTFL_FLEXNVM_DATA_8_EEPROM_24 = 0xF9, + FTFL_FLEXNVM_DATA_0_EEPROM_32 = 0xF3 + } flexnvm_partition : 8; + enum FTFL_EEPROM_SIZE { + FTFL_EEPROM_SIZE_0 = 0x3f, + FTFL_EEPROM_SIZE_32 = 0x39, + FTFL_EEPROM_SIZE_64 = 0x38, + FTFL_EEPROM_SIZE_128 = 0x37, + FTFL_EEPROM_SIZE_256 = 0x36, + FTFL_EEPROM_SIZE_512 = 0x35, + FTFL_EEPROM_SIZE_1024 = 0x34, + FTFL_EEPROM_SIZE_2048 = 0x33 + } eeprom_size : 8; + } program_partition; + struct { + uint8_t _rsvd0[2]; + enum FTFL_FLEXRAM_FUNCTION { + FTFL_FLEXRAM_EEPROM = 0x00, + FTFL_FLEXRAM_RAM = 0xff + } flexram_function : 8; + enum FTFL_FCMD fcmd : 8; + } set_flexram; }; CTASSERT_SIZE_BYTE(union FTFL_FCCOB_t, 12); struct FTFL_t { - struct FTFL_FSTAT_t fstat; - struct FTFL_FCNFG_t fcnfg; - struct FTFL_FSEC_t fsec; - struct FTFL_FOPT_t fopt; - union FTFL_FCCOB_t fccob; - uint8_t fprot_be[4]; - uint8_t feprot; - uint8_t fdprot; + struct FTFL_FSTAT_t fstat; + struct FTFL_FCNFG_t fcnfg; + struct FTFL_FSEC_t fsec; + struct FTFL_FOPT_t fopt; + union FTFL_FCCOB_t fccob; + uint8_t fprot_be[4]; + uint8_t feprot; + uint8_t fdprot; }; CTASSERT_SIZE_BYTE(struct FTFL_t, 0x18); /* Flash Configuration Field, see Sub-Family Reference Manual, section 28.3.1 */ struct FTFL_CONFIG_t { - uint8_t key[8]; - uint8_t fprot[4]; - struct FTFL_FSEC_t fsec; - struct FTFL_FOPT_t fopt; - uint8_t feprot; - uint8_t fdprot; + uint8_t key[8]; + uint8_t fprot[4]; + struct FTFL_FSEC_t fsec; + struct FTFL_FOPT_t fopt; + uint8_t feprot; + uint8_t fdprot; }; CTASSERT_SIZE_BYTE(struct FTFL_CONFIG_t, 16);
--- a/Bootloader/kinetis.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/kinetis.c Fri Jun 12 18:31:55 2015 -0700 @@ -55,272 +55,272 @@ static struct USB_BD_t * usb_get_bd(struct usbd_ep_pipe_state_t *s) { - return (&bdt[(s->ep_num << 2) | (s->ep_dir << 1) | s->pingpong]); + return (&bdt[(s->ep_num << 2) | (s->ep_dir << 1) | s->pingpong]); } static struct USB_BD_t * usb_get_bd_stat(struct USB_STAT_t *stat) { - return (((void *)(uintptr_t)bdt + (stat->raw << 1))); + return (((void *)(uintptr_t)bdt + (stat->raw << 1))); } void *usb_get_xfer_data(struct usb_xfer_info *i) { - return (usb_get_bd_stat(i)->addr); + return (usb_get_bd_stat(i)->addr); } enum usb_tok_pid usb_get_xfer_pid(struct usb_xfer_info *i) { - return (usb_get_bd_stat(i)->tok_pid); + return (usb_get_bd_stat(i)->tok_pid); } int usb_get_xfer_ep(struct usb_xfer_info *i) { - return (i->ep); + return (i->ep); } enum usb_ep_dir usb_get_xfer_dir(struct usb_xfer_info *i) { - return (i->dir); + return (i->dir); } void usb_enable_xfers(void) { - USB0.ctl.raw = ((struct USB_CTL_t){ - .txd_suspend = 0, - .usben = 1 - }).raw; + USB0.ctl.raw = ((struct USB_CTL_t){ + .txd_suspend = 0, + .usben = 1 + }).raw; } void usb_set_addr(int addr) { - USB0.addr.raw = addr; + USB0.addr.raw = addr; } void usb_pipe_stall(struct usbd_ep_pipe_state_t *s) { - volatile struct USB_BD_t *bd = usb_get_bd(s); - bd->raw = ((struct USB_BD_BITS_t){ - .stall = 1, - .own = 1 - }).raw; + volatile struct USB_BD_t *bd = usb_get_bd(s); + bd->raw = ((struct USB_BD_BITS_t){ + .stall = 1, + .own = 1 + }).raw; } void usb_pipe_unstall(struct usbd_ep_pipe_state_t *s) { - volatile struct USB_BD_t *bd = usb_get_bd(s); - struct USB_BD_BITS_t state = { .raw = bd->raw }; + volatile struct USB_BD_t *bd = usb_get_bd(s); + struct USB_BD_BITS_t state = { .raw = bd->raw }; - if (state.own && state.stall) - bd->raw = 0; + if (state.own && state.stall) + bd->raw = 0; } void usb_pipe_enable(struct usbd_ep_pipe_state_t *s) { - USB0.endpt[s->ep_num].raw |= ((struct USB_ENDPT_t){ - .eptxen = s->ep_dir == USB_EP_TX, - .eprxen = s->ep_dir == USB_EP_RX, - .ephshk = 1, /* XXX ISO */ - .epctldis = s->ep_num != 0 - }).raw; + USB0.endpt[s->ep_num].raw |= ((struct USB_ENDPT_t){ + .eptxen = s->ep_dir == USB_EP_TX, + .eprxen = s->ep_dir == USB_EP_RX, + .ephshk = 1, /* XXX ISO */ + .epctldis = s->ep_num != 0 + }).raw; } void usb_pipe_disable(struct usbd_ep_pipe_state_t *s) { - USB0.endpt[s->ep_num].raw &= ~((struct USB_ENDPT_t){ - .eptxen = s->ep_dir == USB_EP_TX, - .eprxen = s->ep_dir == USB_EP_RX, - .epctldis = 1 - }).raw; + USB0.endpt[s->ep_num].raw &= ~((struct USB_ENDPT_t){ + .eptxen = s->ep_dir == USB_EP_TX, + .eprxen = s->ep_dir == USB_EP_RX, + .epctldis = 1 + }).raw; } size_t usb_ep_get_transfer_size(struct usbd_ep_pipe_state_t *s) { - struct USB_BD_t *bd = usb_get_bd(s); - return (bd->bc); + struct USB_BD_t *bd = usb_get_bd(s); + return (bd->bc); } void usb_queue_next(struct usbd_ep_pipe_state_t *s, void *addr, size_t len) { - volatile struct USB_BD_t *bd = usb_get_bd(s); + volatile struct USB_BD_t *bd = usb_get_bd(s); - bd->addr = addr; - /* damn you bitfield problems */ - bd->raw = ((struct USB_BD_BITS_t){ - .dts = 1, - .own = 1, - .data01 = s->data01, - .bc = len, - }).raw; + bd->addr = addr; + /* damn you bitfield problems */ + bd->raw = ((struct USB_BD_BITS_t){ + .dts = 1, + .own = 1, + .data01 = s->data01, + .bc = len, + }).raw; } static void usb_reset(void) { - /* reset pingpong state */ - /* For some obscure reason, we need to use or here. */ - USB0.ctl.raw |= ((struct USB_CTL_t){ - .txd_suspend = 1, - .oddrst = 1, - }).raw; + /* reset pingpong state */ + /* For some obscure reason, we need to use or here. */ + USB0.ctl.raw |= ((struct USB_CTL_t){ + .txd_suspend = 1, + .oddrst = 1, + }).raw; - /* clear all interrupt bits - not sure if needed */ - USB0.istat.raw = 0xff; - USB0.errstat.raw = 0xff; - USB0.otgistat.raw = 0xff; + /* clear all interrupt bits - not sure if needed */ + USB0.istat.raw = 0xff; + USB0.errstat.raw = 0xff; + USB0.otgistat.raw = 0xff; - /* zap also BDT pingpong & queued transactions */ - memset(bdt, 0, sizeof(bdt)); - USB0.addr.raw = 0; + /* zap also BDT pingpong & queued transactions */ + memset(bdt, 0, sizeof(bdt)); + USB0.addr.raw = 0; - usb_restart(); + usb_restart(); - USB0.ctl.raw = ((struct USB_CTL_t){ - .txd_suspend = 0, - .usben = 1 - }).raw; + USB0.ctl.raw = ((struct USB_CTL_t){ + .txd_suspend = 0, + .usben = 1 + }).raw; - /* we're only interested in reset and transfers */ - USB0.inten.raw = ((struct USB_ISTAT_t){ - .tokdne = 1, - .usbrst = 1, - .stall = 1, - .sleep = 1, - }).raw; + /* we're only interested in reset and transfers */ + USB0.inten.raw = ((struct USB_ISTAT_t){ + .tokdne = 1, + .usbrst = 1, + .stall = 1, + .sleep = 1, + }).raw; - USB0.usbtrc0.usbresmen = 0; - USB0.usbctrl.susp = 0; + USB0.usbtrc0.usbresmen = 0; + USB0.usbctrl.susp = 0; } void usb_enable(void) { - SIM.sopt2.usbsrc = 1; /* usb from mcg */ - SIM.scgc4.usbotg = 1; /* enable usb clock */ + SIM.sopt2.usbsrc = 1; /* usb from mcg */ + SIM.scgc4.usbotg = 1; /* enable usb clock */ - /* reset module - not sure if needed */ - USB0.usbtrc0.raw = ((struct USB_USBTRC0_t){ - .usbreset = 1, - .usbresmen = 1 - }).raw; - while (USB0.usbtrc0.usbreset) - /* NOTHING */; + /* reset module - not sure if needed */ + USB0.usbtrc0.raw = ((struct USB_USBTRC0_t){ + .usbreset = 1, + .usbresmen = 1 + }).raw; + while (USB0.usbtrc0.usbreset) + /* NOTHING */; - USB0.bdtpage1 = (uintptr_t)bdt >> 8; - USB0.bdtpage2 = (uintptr_t)bdt >> 16; - USB0.bdtpage3 = (uintptr_t)bdt >> 24; + USB0.bdtpage1 = (uintptr_t)bdt >> 8; + USB0.bdtpage2 = (uintptr_t)bdt >> 16; + USB0.bdtpage3 = (uintptr_t)bdt >> 24; - USB0.control.raw = ((struct USB_CONTROL_t){ - .dppullupnonotg = 1 /* enable pullup */ - }).raw; + USB0.control.raw = ((struct USB_CONTROL_t){ + .dppullupnonotg = 1 /* enable pullup */ + }).raw; - USB0.usbctrl.raw = 0; /* resume peripheral & disable pulldowns */ - usb_reset(); /* this will start usb processing */ + USB0.usbctrl.raw = 0; /* resume peripheral & disable pulldowns */ + usb_reset(); /* this will start usb processing */ - /* really only one thing we want */ - USB0.inten.raw = ((struct USB_ISTAT_t){ - .usbrst = 1, - }).raw; + /* really only one thing we want */ + USB0.inten.raw = ((struct USB_ISTAT_t){ + .usbrst = 1, + }).raw; - /** - * Suspend transceiver now - we'll wake up at reset again. - */ + /** + * Suspend transceiver now - we'll wake up at reset again. + */ // TODO - Possible removal - USB0.usbctrl.susp = 1; - USB0.usbtrc0.usbresmen = 1; + USB0.usbctrl.susp = 1; + USB0.usbtrc0.usbresmen = 1; } void USB0_Handler(void) { - struct USB_ISTAT_t stat = {.raw = USB0.istat.raw }; + struct USB_ISTAT_t stat = {.raw = USB0.istat.raw }; - if (stat.usbrst) { - usb_reset(); - return; - } - if (stat.stall) { - /* XXX need more work for non-0 ep */ - volatile struct USB_BD_t *bd = usb_get_bd(&usb.ep_state[0].rx); - if (bd->stall) - usb_setup_control(); - } - if (stat.tokdne) { - struct usb_xfer_info stat = USB0.stat; - usb_handle_transaction(&stat); - } - if (stat.sleep) { - USB0.inten.sleep = 0; - USB0.inten.resume = 1; - USB0.usbctrl.susp = 1; - USB0.usbtrc0.usbresmen = 1; + if (stat.usbrst) { + usb_reset(); + return; + } + if (stat.stall) { + /* XXX need more work for non-0 ep */ + volatile struct USB_BD_t *bd = usb_get_bd(&usb.ep_state[0].rx); + if (bd->stall) + usb_setup_control(); + } + if (stat.tokdne) { + struct usb_xfer_info stat = USB0.stat; + usb_handle_transaction(&stat); + } + if (stat.sleep) { + USB0.inten.sleep = 0; + USB0.inten.resume = 1; + USB0.usbctrl.susp = 1; + USB0.usbtrc0.usbresmen = 1; - /** - * Clear interrupts now so that we can detect a fresh - * resume later on. - */ - USB0.istat.raw = stat.raw; + /** + * Clear interrupts now so that we can detect a fresh + * resume later on. + */ + USB0.istat.raw = stat.raw; - const struct usbd_config *c = usb_get_config_data(-1); - if (c && c->suspend) - c->suspend(); - } - /** - * XXX it is unclear whether we will receive a synchronous - * resume interrupt if we were in sleep. This code assumes we - * do. - */ - if (stat.resume || USB0.usbtrc0.usb_resume_int) { - USB0.inten.resume = 0; - USB0.inten.sleep = 1; - USB0.usbtrc0.usbresmen = 0; - USB0.usbctrl.susp = 0; + const struct usbd_config *c = usb_get_config_data(-1); + if (c && c->suspend) + c->suspend(); + } + /** + * XXX it is unclear whether we will receive a synchronous + * resume interrupt if we were in sleep. This code assumes we + * do. + */ + if (stat.resume || USB0.usbtrc0.usb_resume_int) { + USB0.inten.resume = 0; + USB0.inten.sleep = 1; + USB0.usbtrc0.usbresmen = 0; + USB0.usbctrl.susp = 0; - const struct usbd_config *c = usb_get_config_data(-1); - if (c && c->resume) - c->resume(); + const struct usbd_config *c = usb_get_config_data(-1); + if (c && c->resume) + c->resume(); - stat.resume = 1; /* always clear bit */ - } - USB0.istat.raw = stat.raw; + stat.resume = 1; /* always clear bit */ + } + USB0.istat.raw = stat.raw; } void usb_poll(void) { - USB0_Handler(); + USB0_Handler(); } int usb_tx_serialno(size_t reqlen) { - struct usb_desc_string_t *d; - const size_t nregs = 3; - /** - * actually 4, but UIDH is 0xffffffff. Also our output buffer - * is only 64 bytes, and 128 bit + desc header exceeds this by - * 2 bytes. - */ - const size_t len = nregs * 4 * 2 * 2 + sizeof(*d); + struct usb_desc_string_t *d; + const size_t nregs = 3; + /** + * actually 4, but UIDH is 0xffffffff. Also our output buffer + * is only 64 bytes, and 128 bit + desc header exceeds this by + * 2 bytes. + */ + const size_t len = nregs * 4 * 2 * 2 + sizeof(*d); - d = usb_ep0_tx_inplace_prepare(len); + d = usb_ep0_tx_inplace_prepare(len); - if (d == NULL) - return (-1); + if (d == NULL) + return (-1); - d->bLength = len; - d->bDescriptorType = USB_DESC_STRING; + d->bLength = len; + d->bDescriptorType = USB_DESC_STRING; - size_t bufpos = 0; - for (size_t reg = 0; reg < nregs; ++reg) { - /* registers run MSW first */ - uint32_t val = (&SIM.uidmh)[reg]; + size_t bufpos = 0; + for (size_t reg = 0; reg < nregs; ++reg) { + /* registers run MSW first */ + uint32_t val = (&SIM.uidmh)[reg]; - for (size_t bits = 32; bits > 0; bits -= 4, val <<= 4) { - int nibble = val >> 28; + for (size_t bits = 32; bits > 0; bits -= 4, val <<= 4) { + int nibble = val >> 28; - if (nibble > 9) - nibble += 'a' - '9' - 1; - ((char16_t *)d->bString)[bufpos++] = nibble + '0'; - } - } - usb_ep0_tx(d, len, reqlen, NULL, NULL); - return (0); + if (nibble > 9) + nibble += 'a' - '9' - 1; + ((char16_t *)d->bString)[bufpos++] = nibble + '0'; + } + } + usb_ep0_tx(d, len, reqlen, NULL, NULL); + return (0); }
--- a/Bootloader/main.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/main.c Fri Jun 12 18:31:55 2015 -0700 @@ -36,38 +36,38 @@ static enum dfu_status setup_write(size_t off, size_t len, void **buf) { - static int last = 0; + static int last = 0; - if (len > sizeof(staging)) - return (DFU_STATUS_errADDRESS); + if (len > sizeof(staging)) + return (DFU_STATUS_errADDRESS); - // We only allow the last write to be less than one sector size. - if (off == 0) - last = 0; - if (last && len != 0) - return (DFU_STATUS_errADDRESS); - if (len != FLASH_SECTOR_SIZE) { - last = 1; - memset(staging, 0xff, sizeof(staging)); - } + // We only allow the last write to be less than one sector size. + if (off == 0) + last = 0; + if (last && len != 0) + return (DFU_STATUS_errADDRESS); + if (len != FLASH_SECTOR_SIZE) { + last = 1; + memset(staging, 0xff, sizeof(staging)); + } - *buf = staging; - return (DFU_STATUS_OK); + *buf = staging; + return (DFU_STATUS_OK); } static enum dfu_status finish_write( void *buf, size_t off, size_t len ) { - void *target; - if (len == 0) - return (DFU_STATUS_OK); + void *target; + if (len == 0) + return (DFU_STATUS_OK); - target = flash_get_staging_area(off + (uintptr_t)&_app_rom, FLASH_SECTOR_SIZE); - if (!target) - return (DFU_STATUS_errADDRESS); - memcpy(target, buf, len); - if (flash_program_sector(off + (uintptr_t)&_app_rom, FLASH_SECTOR_SIZE) != 0) - return (DFU_STATUS_errADDRESS); - return (DFU_STATUS_OK); + target = flash_get_staging_area(off + (uintptr_t)&_app_rom, FLASH_SECTOR_SIZE); + if (!target) + return (DFU_STATUS_errADDRESS); + memcpy(target, buf, len); + if (flash_program_sector(off + (uintptr_t)&_app_rom, FLASH_SECTOR_SIZE) != 0) + return (DFU_STATUS_errADDRESS); + return (DFU_STATUS_OK); } @@ -75,7 +75,7 @@ void init_usb_bootloader( int config ) { - dfu_init(setup_write, finish_write, &dfu_ctx); + dfu_init(setup_write, finish_write, &dfu_ctx); } void main() @@ -98,12 +98,12 @@ #endif - flash_prepare_flashing(); + flash_prepare_flashing(); - usb_init( &dfu_device ); - for (;;) + usb_init( &dfu_device ); + for (;;) { - usb_poll(); - } + usb_poll(); + } }
--- a/Bootloader/mchck-cdefs.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/mchck-cdefs.h Fri Jun 12 18:31:55 2015 -0700 @@ -42,15 +42,15 @@ #define CTASSERT_SIZE_BIT(t, s) CTASSERT(sizeof(t) * 8 == (s)) #define UNION_STRUCT_START(size) \ - union { \ - _CONCAT(_CONCAT(uint, size), _t) raw; \ - struct { \ - /* just to swallow the following semicolon */ \ - struct _CONCAT(_CONCAT(__dummy_, __COUNTER__), _t) {} + union { \ + _CONCAT(_CONCAT(uint, size), _t) raw; \ + struct { \ + /* just to swallow the following semicolon */ \ + struct _CONCAT(_CONCAT(__dummy_, __COUNTER__), _t) {} #define UNION_STRUCT_END \ - }; /* struct */ \ - }; /* union */ + }; /* struct */ \ + }; /* union */ /** @@ -58,25 +58,25 @@ * <https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s> */ #define __PP_NARG(...) \ - __PP_NARG_(__0, ## __VA_ARGS__, __PP_RSEQ_N()) + __PP_NARG_(__0, ## __VA_ARGS__, __PP_RSEQ_N()) #define __PP_NARG_(...) \ - __PP_ARG_N(__VA_ARGS__) + __PP_ARG_N(__VA_ARGS__) #define __PP_ARG_N( \ - _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \ - _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ - _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ - _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \ - _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ - _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ - _61,_62,_63,N,...) N + _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \ + _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ + _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ + _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \ + _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ + _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ + _61,_62,_63,N,...) N #define __PP_RSEQ_N() \ - 62,61,60, \ - 59,58,57,56,55,54,53,52,51,50, \ - 49,48,47,46,45,44,43,42,41,40, \ - 39,38,37,36,35,34,33,32,31,30, \ - 29,28,27,26,25,24,23,22,21,20, \ - 19,18,17,16,15,14,13,12,11,10, \ - 9,8,7,6,5,4,3,2,1,0 + 62,61,60, \ + 59,58,57,56,55,54,53,52,51,50, \ + 49,48,47,46,45,44,43,42,41,40, \ + 39,38,37,36,35,34,33,32,31,30, \ + 29,28,27,26,25,24,23,22,21,20, \ + 19,18,17,16,15,14,13,12,11,10, \ + 9,8,7,6,5,4,3,2,1,0 /** * From <https://github.com/pfultz2/Cloak/wiki/C-Preprocessor-tricks,-tips,-and-idioms> @@ -126,13 +126,13 @@ #define __REPEAT_INNER(...) __OBSTRUCT(__REPEAT_INDIRECT) () (__VA_ARGS__) #define __REPEAT_INDIRECT() __REPEAT_ #define __REPEAT_(iter, itermacro, macro, a, ...) \ - __OBSTRUCT(macro)(iter, a) \ - __WHEN(__PP_NARG(__VA_ARGS__)) \ - ( \ - __OBSTRUCT(__REPEAT_INDIRECT) () ( \ - itermacro(iter, a), itermacro, macro, __VA_ARGS__ \ - ) \ - ) + __OBSTRUCT(macro)(iter, a) \ + __WHEN(__PP_NARG(__VA_ARGS__)) \ + ( \ + __OBSTRUCT(__REPEAT_INDIRECT) () ( \ + itermacro(iter, a), itermacro, macro, __VA_ARGS__ \ + ) \ + ) #endif
--- a/Bootloader/sim.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/sim.h Fri Jun 12 18:31:55 2015 -0700 @@ -27,302 +27,302 @@ // ----- Structs ----- struct SIM_t { - struct SIM_SOPT1_t { - UNION_STRUCT_START(32); - uint32_t _rsvd0 : 12; - enum { - SIM_RAMSIZE_8KB = 1, - SIM_RAMSIZE_16KB = 3 - } ramsize : 4; - uint32_t _rsvd1 : 2; - enum { - SIM_OSC32KSEL_SYSTEM = 0, - SIM_OSC32KSEL_RTC = 2, - SIM_OSC32KSEL_LPO = 3 - } osc32ksel : 2; - uint32_t _rsvd2 : 9; - uint32_t usbvstby : 1; - uint32_t usbsstby : 1; - uint32_t usbregen : 1; - UNION_STRUCT_END; - } sopt1; - struct SIM_SOPT1CFG_t { - UNION_STRUCT_START(32); - uint32_t _rsvd0 : 24; - uint32_t urwe : 1; - uint32_t uvswe : 1; - uint32_t usswe : 1; - uint32_t _rsvd1 : 5; - UNION_STRUCT_END; - } sopt1cfg; - uint32_t _pad0[(0x1004 - 0x8) / 4]; - struct SIM_SOPT2_t { - UNION_STRUCT_START(32); - uint32_t _rsvd0 : 4; - enum { - SIM_RTCCLKOUTSEL_1HZ = 0, - SIM_RTCCLKOUTSEL_32KHZ = 1 - } rtcclkoutsel : 1; - enum { - SIM_CLKOUTSEL_FLASH = 2, - SIM_CLKOUTSEL_LPO = 3, - SIM_CLKOUTSEL_MCG = 4, - SIM_CLKOUTSEL_RTC = 5, - SIM_CLKOUTSEL_OSC = 6 - } clkoutsel : 3; - uint32_t _rsvd1 : 3; - enum { - SIM_PTD7PAD_SINGLE = 0, - SIM_PTD7PAD_DOUBLE = 1 - } ptd7pad : 1; - enum { - SIM_TRACECLKSEL_MCG = 0, - SIM_TRACECLKSEL_CORE = 1 - } traceclksel : 1; - uint32_t _rsvd2 : 3; - enum { - SIM_PLLFLLSEL_FLL = 0, - SIM_PLLFLLSEL_PLL = 1 - } pllfllsel : 1; - uint32_t _rsvd3 : 1; - enum { - SIM_USBSRC_EXTERNAL = 0, - SIM_USBSRC_MCG = 1 - } usbsrc : 1; - uint32_t _rsvd4 : 13; - UNION_STRUCT_END; - } sopt2; - uint32_t _pad1; - struct SIM_SOPT4_t { - UNION_STRUCT_START(32); - enum sim_ftmflt { - SIM_FTMFLT_FTM = 0, - SIM_FTMFLT_CMP = 1 - } ftm0flt0 : 1; - enum sim_ftmflt ftm0flt1 : 1; - uint32_t _rsvd0 : 2; - enum sim_ftmflt ftm1flt0 : 1; - uint32_t _rsvd1 : 13; - enum { - SIM_FTMCHSRC_FTM = 0, - SIM_FTMCHSRC_CMP0 = 1, - SIM_FTMCHSRC_CMP1 = 2, - SIM_FTMCHSRC_USBSOF = 3 - } ftm1ch0src : 2; - uint32_t _rsvd2 : 4; - enum sim_ftmclksel { - SIM_FTMCLKSEL_CLK0 = 0, - SIM_FTMCLKSEL_CLK1 = 1 - } ftm0clksel : 1; - enum sim_ftmclksel ftm1clksel : 1; - uint32_t _rsvd3 : 2; - enum { - SIM_FTMTRGSRC_HSCMP0 = 0, - SIM_FTMTRGSRC_FTM1 = 1 - } ftm0trg0src : 1; - uint32_t _rsvd4 : 3; - UNION_STRUCT_END; - } sopt4; - struct SIM_SOPT5_t { - UNION_STRUCT_START(32); - enum sim_uarttxsrc { - SIM_UARTTXSRC_UART = 0, - SIM_UARTTXSRC_FTM = 1 - } uart0txsrc : 1; - uint32_t _rsvd0 : 1; - enum sim_uartrxsrc { - SIM_UARTRXSRC_UART = 0, - SIM_UARTRXSRC_CMP0 = 1, - SIM_UARTRXSRC_CMP1 = 2 - } uart0rxsrc : 2; - enum sim_uarttxsrc uart1txsrc : 1; - uint32_t _rsvd1 : 1; - enum sim_uartrxsrc uart1rxsrc : 2; - uint32_t _rsvd2 : 24; - UNION_STRUCT_END; - } sopt5; - uint32_t _pad2; - struct SIM_SOPT7_t { - UNION_STRUCT_START(32); - enum { - SIM_ADCTRGSEL_PDB = 0, - SIM_ADCTRGSEL_HSCMP0 = 1, - SIM_ADCTRGSEL_HSCMP1 = 2, - SIM_ADCTRGSEL_PIT0 = 4, - SIM_ADCTRGSEL_PIT1 = 5, - SIM_ADCTRGSEL_PIT2 = 6, - SIM_ADCTRGSEL_PIT3 = 7, - SIM_ADCTRGSEL_FTM0 = 8, - SIM_ADCTRGSEL_FTM1 = 9, - SIM_ADCTRGSEL_RTCALARM = 12, - SIM_ADCTRGSEL_RTCSECS = 13, - SIM_ADCTRGSEL_LPTIMER = 14 - } adc0trgsel : 4; - enum { - SIM_ADCPRETRGSEL_A = 0, - SIM_ADCPRETRGSEL_B = 1 - } adc0pretrgsel : 1; - uint32_t _rsvd0 : 2; - enum { - SIM_ADCALTTRGEN_PDB = 0, - SIM_ADCALTTRGEN_ALT = 1 - } adc0alttrgen : 1; - uint32_t _rsvd1 : 24; - UNION_STRUCT_END; - } sopt7; - uint32_t _pad3[(0x1024 - 0x101c) / 4]; - struct SIM_SDID_t { - UNION_STRUCT_START(32); - enum { - SIM_PINID_32 = 2, - SIM_PINID_48 = 4, - SIM_PINID_64 = 5 - } pinid : 4; - enum { - SIM_FAMID_K10 = 0, - SIM_FAMID_K20 = 1 - } famid : 3; - uint32_t _rsvd1 : 5; - uint32_t revid : 4; - uint32_t _rsvd2 : 16; - UNION_STRUCT_END; - } sdid; - uint32_t _pad4[(0x1034 - 0x1028) / 4]; - struct SIM_SCGC4_t { - UNION_STRUCT_START(32); - uint32_t _rsvd0 : 1; - uint32_t ewm : 1; - uint32_t cmt : 1; - uint32_t _rsvd1 : 3; - uint32_t i2c0 : 1; - uint32_t _rsvd2 : 3; - uint32_t uart0 : 1; - uint32_t uart1 : 1; - uint32_t uart2 : 1; - uint32_t _rsvd3 : 5; - uint32_t usbotg : 1; - uint32_t cmp : 1; - uint32_t vref : 1; - uint32_t _rsvd4 : 11; - UNION_STRUCT_END; - } scgc4; - struct SIM_SCGC5_t { - UNION_STRUCT_START(32); - uint32_t lptimer : 1; - uint32_t _rsvd0 : 4; - uint32_t tsi : 1; - uint32_t _rsvd1 : 3; - uint32_t porta : 1; - uint32_t portb : 1; - uint32_t portc : 1; - uint32_t portd : 1; - uint32_t porte : 1; - uint32_t _rsvd2 : 18; - UNION_STRUCT_END; - } scgc5; - struct SIM_SCGC6_t { - UNION_STRUCT_START(32); - uint32_t ftfl : 1; - uint32_t dmamux : 1; - uint32_t _rsvd0 : 10; - uint32_t spi0 : 1; - uint32_t _rsvd1 : 2; - uint32_t i2s : 1; - uint32_t _rsvd2 : 2; - uint32_t crc : 1; - uint32_t _rsvd3 : 2; - uint32_t usbdcd : 1; - uint32_t pdb : 1; - uint32_t pit : 1; - uint32_t ftm0 : 1; - uint32_t ftm1 : 1; - uint32_t _rsvd4 : 1; - uint32_t adc0 : 1; - uint32_t _rsvd5 : 1; - uint32_t rtc : 1; - uint32_t _rsvd6 : 2; - UNION_STRUCT_END; - } scgc6; - struct SIM_SCGC7_t { - UNION_STRUCT_START(32); - uint32_t _rsvd0 : 1; - uint32_t dma : 1; - uint32_t _rsvd1 : 30; - UNION_STRUCT_END; - } scgc7; - struct SIM_CLKDIV1_t { - UNION_STRUCT_START(32); - uint32_t _rsvd0 : 16; - uint32_t outdiv4 : 4; - uint32_t _rsvd1 : 4; - uint32_t outdiv2 : 4; - uint32_t outdiv1 : 4; - UNION_STRUCT_END; - } clkdiv1; - struct SIM_CLKDIV2_t { - UNION_STRUCT_START(32); - uint32_t usbfrac : 1; - uint32_t usbdiv : 3; - uint32_t _rsvd0 : 28; - UNION_STRUCT_END; - } clkdiv2; - struct SIM_FCFG1_t { - UNION_STRUCT_START(32); - uint32_t flashdis : 1; - uint32_t flashdoze : 1; - uint32_t _rsvd0 : 6; + struct SIM_SOPT1_t { + UNION_STRUCT_START(32); + uint32_t _rsvd0 : 12; + enum { + SIM_RAMSIZE_8KB = 1, + SIM_RAMSIZE_16KB = 3 + } ramsize : 4; + uint32_t _rsvd1 : 2; + enum { + SIM_OSC32KSEL_SYSTEM = 0, + SIM_OSC32KSEL_RTC = 2, + SIM_OSC32KSEL_LPO = 3 + } osc32ksel : 2; + uint32_t _rsvd2 : 9; + uint32_t usbvstby : 1; + uint32_t usbsstby : 1; + uint32_t usbregen : 1; + UNION_STRUCT_END; + } sopt1; + struct SIM_SOPT1CFG_t { + UNION_STRUCT_START(32); + uint32_t _rsvd0 : 24; + uint32_t urwe : 1; + uint32_t uvswe : 1; + uint32_t usswe : 1; + uint32_t _rsvd1 : 5; + UNION_STRUCT_END; + } sopt1cfg; + uint32_t _pad0[(0x1004 - 0x8) / 4]; + struct SIM_SOPT2_t { + UNION_STRUCT_START(32); + uint32_t _rsvd0 : 4; + enum { + SIM_RTCCLKOUTSEL_1HZ = 0, + SIM_RTCCLKOUTSEL_32KHZ = 1 + } rtcclkoutsel : 1; + enum { + SIM_CLKOUTSEL_FLASH = 2, + SIM_CLKOUTSEL_LPO = 3, + SIM_CLKOUTSEL_MCG = 4, + SIM_CLKOUTSEL_RTC = 5, + SIM_CLKOUTSEL_OSC = 6 + } clkoutsel : 3; + uint32_t _rsvd1 : 3; + enum { + SIM_PTD7PAD_SINGLE = 0, + SIM_PTD7PAD_DOUBLE = 1 + } ptd7pad : 1; + enum { + SIM_TRACECLKSEL_MCG = 0, + SIM_TRACECLKSEL_CORE = 1 + } traceclksel : 1; + uint32_t _rsvd2 : 3; + enum { + SIM_PLLFLLSEL_FLL = 0, + SIM_PLLFLLSEL_PLL = 1 + } pllfllsel : 1; + uint32_t _rsvd3 : 1; + enum { + SIM_USBSRC_EXTERNAL = 0, + SIM_USBSRC_MCG = 1 + } usbsrc : 1; + uint32_t _rsvd4 : 13; + UNION_STRUCT_END; + } sopt2; + uint32_t _pad1; + struct SIM_SOPT4_t { + UNION_STRUCT_START(32); + enum sim_ftmflt { + SIM_FTMFLT_FTM = 0, + SIM_FTMFLT_CMP = 1 + } ftm0flt0 : 1; + enum sim_ftmflt ftm0flt1 : 1; + uint32_t _rsvd0 : 2; + enum sim_ftmflt ftm1flt0 : 1; + uint32_t _rsvd1 : 13; + enum { + SIM_FTMCHSRC_FTM = 0, + SIM_FTMCHSRC_CMP0 = 1, + SIM_FTMCHSRC_CMP1 = 2, + SIM_FTMCHSRC_USBSOF = 3 + } ftm1ch0src : 2; + uint32_t _rsvd2 : 4; + enum sim_ftmclksel { + SIM_FTMCLKSEL_CLK0 = 0, + SIM_FTMCLKSEL_CLK1 = 1 + } ftm0clksel : 1; + enum sim_ftmclksel ftm1clksel : 1; + uint32_t _rsvd3 : 2; + enum { + SIM_FTMTRGSRC_HSCMP0 = 0, + SIM_FTMTRGSRC_FTM1 = 1 + } ftm0trg0src : 1; + uint32_t _rsvd4 : 3; + UNION_STRUCT_END; + } sopt4; + struct SIM_SOPT5_t { + UNION_STRUCT_START(32); + enum sim_uarttxsrc { + SIM_UARTTXSRC_UART = 0, + SIM_UARTTXSRC_FTM = 1 + } uart0txsrc : 1; + uint32_t _rsvd0 : 1; + enum sim_uartrxsrc { + SIM_UARTRXSRC_UART = 0, + SIM_UARTRXSRC_CMP0 = 1, + SIM_UARTRXSRC_CMP1 = 2 + } uart0rxsrc : 2; + enum sim_uarttxsrc uart1txsrc : 1; + uint32_t _rsvd1 : 1; + enum sim_uartrxsrc uart1rxsrc : 2; + uint32_t _rsvd2 : 24; + UNION_STRUCT_END; + } sopt5; + uint32_t _pad2; + struct SIM_SOPT7_t { + UNION_STRUCT_START(32); + enum { + SIM_ADCTRGSEL_PDB = 0, + SIM_ADCTRGSEL_HSCMP0 = 1, + SIM_ADCTRGSEL_HSCMP1 = 2, + SIM_ADCTRGSEL_PIT0 = 4, + SIM_ADCTRGSEL_PIT1 = 5, + SIM_ADCTRGSEL_PIT2 = 6, + SIM_ADCTRGSEL_PIT3 = 7, + SIM_ADCTRGSEL_FTM0 = 8, + SIM_ADCTRGSEL_FTM1 = 9, + SIM_ADCTRGSEL_RTCALARM = 12, + SIM_ADCTRGSEL_RTCSECS = 13, + SIM_ADCTRGSEL_LPTIMER = 14 + } adc0trgsel : 4; + enum { + SIM_ADCPRETRGSEL_A = 0, + SIM_ADCPRETRGSEL_B = 1 + } adc0pretrgsel : 1; + uint32_t _rsvd0 : 2; + enum { + SIM_ADCALTTRGEN_PDB = 0, + SIM_ADCALTTRGEN_ALT = 1 + } adc0alttrgen : 1; + uint32_t _rsvd1 : 24; + UNION_STRUCT_END; + } sopt7; + uint32_t _pad3[(0x1024 - 0x101c) / 4]; + struct SIM_SDID_t { + UNION_STRUCT_START(32); + enum { + SIM_PINID_32 = 2, + SIM_PINID_48 = 4, + SIM_PINID_64 = 5 + } pinid : 4; + enum { + SIM_FAMID_K10 = 0, + SIM_FAMID_K20 = 1 + } famid : 3; + uint32_t _rsvd1 : 5; + uint32_t revid : 4; + uint32_t _rsvd2 : 16; + UNION_STRUCT_END; + } sdid; + uint32_t _pad4[(0x1034 - 0x1028) / 4]; + struct SIM_SCGC4_t { + UNION_STRUCT_START(32); + uint32_t _rsvd0 : 1; + uint32_t ewm : 1; + uint32_t cmt : 1; + uint32_t _rsvd1 : 3; + uint32_t i2c0 : 1; + uint32_t _rsvd2 : 3; + uint32_t uart0 : 1; + uint32_t uart1 : 1; + uint32_t uart2 : 1; + uint32_t _rsvd3 : 5; + uint32_t usbotg : 1; + uint32_t cmp : 1; + uint32_t vref : 1; + uint32_t _rsvd4 : 11; + UNION_STRUCT_END; + } scgc4; + struct SIM_SCGC5_t { + UNION_STRUCT_START(32); + uint32_t lptimer : 1; + uint32_t _rsvd0 : 4; + uint32_t tsi : 1; + uint32_t _rsvd1 : 3; + uint32_t porta : 1; + uint32_t portb : 1; + uint32_t portc : 1; + uint32_t portd : 1; + uint32_t porte : 1; + uint32_t _rsvd2 : 18; + UNION_STRUCT_END; + } scgc5; + struct SIM_SCGC6_t { + UNION_STRUCT_START(32); + uint32_t ftfl : 1; + uint32_t dmamux : 1; + uint32_t _rsvd0 : 10; + uint32_t spi0 : 1; + uint32_t _rsvd1 : 2; + uint32_t i2s : 1; + uint32_t _rsvd2 : 2; + uint32_t crc : 1; + uint32_t _rsvd3 : 2; + uint32_t usbdcd : 1; + uint32_t pdb : 1; + uint32_t pit : 1; + uint32_t ftm0 : 1; + uint32_t ftm1 : 1; + uint32_t _rsvd4 : 1; + uint32_t adc0 : 1; + uint32_t _rsvd5 : 1; + uint32_t rtc : 1; + uint32_t _rsvd6 : 2; + UNION_STRUCT_END; + } scgc6; + struct SIM_SCGC7_t { + UNION_STRUCT_START(32); + uint32_t _rsvd0 : 1; + uint32_t dma : 1; + uint32_t _rsvd1 : 30; + UNION_STRUCT_END; + } scgc7; + struct SIM_CLKDIV1_t { + UNION_STRUCT_START(32); + uint32_t _rsvd0 : 16; + uint32_t outdiv4 : 4; + uint32_t _rsvd1 : 4; + uint32_t outdiv2 : 4; + uint32_t outdiv1 : 4; + UNION_STRUCT_END; + } clkdiv1; + struct SIM_CLKDIV2_t { + UNION_STRUCT_START(32); + uint32_t usbfrac : 1; + uint32_t usbdiv : 3; + uint32_t _rsvd0 : 28; + UNION_STRUCT_END; + } clkdiv2; + struct SIM_FCFG1_t { + UNION_STRUCT_START(32); + uint32_t flashdis : 1; + uint32_t flashdoze : 1; + uint32_t _rsvd0 : 6; - /* the following enum is analogous to enum - * FTFL_FLEXNVM_PARTITION in ftfl.h, but that one is padded - * with four 1-bits to make an 8-bit value. - */ - enum SIM_FLEXNVM_PARTITION { - SIM_FLEXNVM_DATA_32_EEPROM_0 = 0x0, - SIM_FLEXNVM_DATA_24_EEPROM_8 = 0x1, - SIM_FLEXNVM_DATA_16_EEPROM_16 = 0x2, - SIM_FLEXNVM_DATA_8_EEPROM_24 = 0x9, - SIM_FLEXNVM_DATA_0_EEPROM_32 = 0x3 - } depart : 4; + /* the following enum is analogous to enum + * FTFL_FLEXNVM_PARTITION in ftfl.h, but that one is padded + * with four 1-bits to make an 8-bit value. + */ + enum SIM_FLEXNVM_PARTITION { + SIM_FLEXNVM_DATA_32_EEPROM_0 = 0x0, + SIM_FLEXNVM_DATA_24_EEPROM_8 = 0x1, + SIM_FLEXNVM_DATA_16_EEPROM_16 = 0x2, + SIM_FLEXNVM_DATA_8_EEPROM_24 = 0x9, + SIM_FLEXNVM_DATA_0_EEPROM_32 = 0x3 + } depart : 4; - uint32_t _rsvd1 : 4; - enum { - SIM_EESIZE_2KB = 3, - SIM_EESIZE_1KB = 4, - SIM_EESIZE_512B = 5, - SIM_EESIZE_256B = 6, - SIM_EESIZE_128B = 7, - SIM_EESIZE_64B = 8, - SIM_EESIZE_32B = 9, - SIM_EESIZE_0B = 15 - } eesize : 4; - uint32_t _rsvd2 : 4; - enum { - SIM_PFSIZE_32KB = 3, - SIM_PFSIZE_64KB = 5, - SIM_PFSIZE_128KB = 7 - } pfsize : 4; - enum { - SIM_NVMSIZE_0KB = 0, - SIM_NVMSIZE_32KB = 3 - } nvmsize : 4; - UNION_STRUCT_END; - } fcfg1; - struct SIM_FCFG2_t { - UNION_STRUCT_START(32); - uint32_t _rsvd0 : 16; - uint32_t maxaddr1 : 7; - enum { - SIM_PFLSH_FLEXNVM = 0, - SIM_PFLSH_PROGRAM = 1 - } pflsh : 1; - uint32_t maxaddr0 : 7; - uint32_t _rsvd1 : 1; - UNION_STRUCT_END; - } fcfg2; - uint32_t uidh; - uint32_t uidmh; - uint32_t uidml; - uint32_t uidl; + uint32_t _rsvd1 : 4; + enum { + SIM_EESIZE_2KB = 3, + SIM_EESIZE_1KB = 4, + SIM_EESIZE_512B = 5, + SIM_EESIZE_256B = 6, + SIM_EESIZE_128B = 7, + SIM_EESIZE_64B = 8, + SIM_EESIZE_32B = 9, + SIM_EESIZE_0B = 15 + } eesize : 4; + uint32_t _rsvd2 : 4; + enum { + SIM_PFSIZE_32KB = 3, + SIM_PFSIZE_64KB = 5, + SIM_PFSIZE_128KB = 7 + } pfsize : 4; + enum { + SIM_NVMSIZE_0KB = 0, + SIM_NVMSIZE_32KB = 3 + } nvmsize : 4; + UNION_STRUCT_END; + } fcfg1; + struct SIM_FCFG2_t { + UNION_STRUCT_START(32); + uint32_t _rsvd0 : 16; + uint32_t maxaddr1 : 7; + enum { + SIM_PFLSH_FLEXNVM = 0, + SIM_PFLSH_PROGRAM = 1 + } pflsh : 1; + uint32_t maxaddr0 : 7; + uint32_t _rsvd1 : 1; + UNION_STRUCT_END; + } fcfg2; + uint32_t uidh; + uint32_t uidmh; + uint32_t uidml; + uint32_t uidl; }; CTASSERT_SIZE_BYTE(struct SIM_t, 0x1064);
--- a/Bootloader/usb.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/usb.c Fri Jun 12 18:31:55 2015 -0700 @@ -171,10 +171,10 @@ */ size_t nextlen = s->transfer_size; - if (nextlen > s->ep_maxsize) - nextlen = s->ep_maxsize; + if (nextlen > s->ep_maxsize) + nextlen = s->ep_maxsize; - void *addr = s->data_buf + s->pos; + void *addr = s->data_buf + s->pos; usb_queue_next(s, addr, nextlen); return (1);
--- a/Bootloader/usb.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/usb.h Fri Jun 12 18:31:55 2015 -0700 @@ -37,113 +37,113 @@ #define USB_CTRL_REQ_TYPE_SHIFT 1 #define USB_CTRL_REQ_RECP_SHIFT 3 #define USB_CTRL_REQ_CODE_SHIFT 8 -#define USB_CTRL_REQ(req_inout, req_type, req_code) \ - (uint16_t) \ - ((USB_CTRL_REQ_##req_inout << USB_CTRL_REQ_DIR_SHIFT) \ - |(USB_CTRL_REQ_##req_type << USB_CTRL_REQ_TYPE_SHIFT) \ +#define USB_CTRL_REQ(req_inout, req_type, req_code) \ + (uint16_t) \ + ((USB_CTRL_REQ_##req_inout << USB_CTRL_REQ_DIR_SHIFT) \ + |(USB_CTRL_REQ_##req_type << USB_CTRL_REQ_TYPE_SHIFT) \ |(USB_CTRL_REQ_##req_code << USB_CTRL_REQ_CODE_SHIFT)) // ----- Macros ----- -#define USB_DESC_STRING(s) \ - (const void *)&(const struct { \ - struct usb_desc_string_t dsc; \ - char16_t str[sizeof(s) / 2 - 1]; \ - }) {{ \ - .bLength = sizeof(struct usb_desc_string_t) + \ - sizeof(s) - 2, \ - .bDescriptorType = USB_DESC_STRING, \ - }, \ - s \ +#define USB_DESC_STRING(s) \ + (const void *)&(const struct { \ + struct usb_desc_string_t dsc; \ + char16_t str[sizeof(s) / 2 - 1]; \ + }) {{ \ + .bLength = sizeof(struct usb_desc_string_t) + \ + sizeof(s) - 2, \ + .bDescriptorType = USB_DESC_STRING, \ + }, \ + s \ } #define USB_DESC_STRING_LANG_ENUS USB_DESC_STRING(u"\x0409") #define USB_DESC_STRING_SERIALNO ((const void *)1) -#define USB_FUNCTION_IFACE(iface, iface_off, tx_ep_off, rx_ep_off) \ +#define USB_FUNCTION_IFACE(iface, iface_off, tx_ep_off, rx_ep_off) \ ((iface_off) + (iface)) -#define USB_FUNCTION_TX_EP(ep, iface_off, tx_ep_off, rx_ep_off) \ +#define USB_FUNCTION_TX_EP(ep, iface_off, tx_ep_off, rx_ep_off) \ ((tx_ep_off) + (ep)) -#define USB_FUNCTION_RX_EP(ep, iface_off, tx_ep_off, rx_ep_off) \ +#define USB_FUNCTION_RX_EP(ep, iface_off, tx_ep_off, rx_ep_off) \ ((rx_ep_off) + (ep)) #define USB__INCREMENT(i, _0) (i + 1) -#define USB__COUNT_IFACE_EP(i, e) \ +#define USB__COUNT_IFACE_EP(i, e) \ __DEFER(USB__COUNT_IFACE_EP_)(__EXPAND i, e) #define USB__COUNT_IFACE_EP_(iface, tx_ep, rx_ep, func) \ - (iface + USB_FUNCTION_ ## func ## _IFACE_COUNT, \ - tx_ep + USB_FUNCTION_ ## func ## _TX_EP_COUNT, \ + (iface + USB_FUNCTION_ ## func ## _IFACE_COUNT, \ + tx_ep + USB_FUNCTION_ ## func ## _TX_EP_COUNT, \ rx_ep + USB_FUNCTION_ ## func ## _RX_EP_COUNT) -#define USB__GET_FUNCTION_IFACE_COUNT(iter, func) \ +#define USB__GET_FUNCTION_IFACE_COUNT(iter, func) \ USB_FUNCTION_ ## func ## _IFACE_COUNT + -#define USB__DEFINE_FUNCTION_DESC(iter, func) \ +#define USB__DEFINE_FUNCTION_DESC(iter, func) \ USB_FUNCTION_DESC_ ## func ## _DECL __CAT(__usb_func_desc, __COUNTER__); -#define USB__INIT_FUNCTION_DESC(iter, func) \ +#define USB__INIT_FUNCTION_DESC(iter, func) \ USB_FUNCTION_DESC_ ## func iter, -#define USB__DEFINE_CONFIG_DESC(confignum, name, ...) \ - &((const struct name { \ - struct usb_desc_config_t config; \ +#define USB__DEFINE_CONFIG_DESC(confignum, name, ...) \ + &((const struct name { \ + struct usb_desc_config_t config; \ __REPEAT_INNER(, __EAT, USB__DEFINE_FUNCTION_DESC, __VA_ARGS__) \ - }){ \ - .config = { \ - .bLength = sizeof(struct usb_desc_config_t), \ - .bDescriptorType = USB_DESC_CONFIG, \ - .wTotalLength = sizeof(struct name), \ + }){ \ + .config = { \ + .bLength = sizeof(struct usb_desc_config_t), \ + .bDescriptorType = USB_DESC_CONFIG, \ + .wTotalLength = sizeof(struct name), \ .bNumInterfaces = __REPEAT_INNER(, __EAT, USB__GET_FUNCTION_IFACE_COUNT, __VA_ARGS__) 0, \ - .bConfigurationValue = confignum, \ - .iConfiguration = 0, \ - .one = 1, \ - .bMaxPower = 50 \ - }, \ + .bConfigurationValue = confignum, \ + .iConfiguration = 0, \ + .one = 1, \ + .bMaxPower = 50 \ + }, \ __REPEAT_INNER((0, 0, 0), USB__COUNT_IFACE_EP, USB__INIT_FUNCTION_DESC, __VA_ARGS__) \ }).config -#define USB__DEFINE_CONFIG(iter, args) \ +#define USB__DEFINE_CONFIG(iter, args) \ __DEFER(USB__DEFINE_CONFIG_)(iter, __EXPAND args) -#define USB__DEFINE_CONFIG_(confignum, initfun, ...) \ - &(const struct usbd_config){ \ - .init = initfun, \ - .desc = USB__DEFINE_CONFIG_DESC( \ - confignum, \ - __CAT(__usb_desc, __COUNTER__), \ - __VA_ARGS__) \ +#define USB__DEFINE_CONFIG_(confignum, initfun, ...) \ + &(const struct usbd_config){ \ + .init = initfun, \ + .desc = USB__DEFINE_CONFIG_DESC( \ + confignum, \ + __CAT(__usb_desc, __COUNTER__), \ + __VA_ARGS__) \ }, -#define USB_INIT_DEVICE(vid, pid, manuf, product, ...) \ - { \ - .dev_desc = &(const struct usb_desc_dev_t){ \ - .bLength = sizeof(struct usb_desc_dev_t), \ - .bDescriptorType = USB_DESC_DEV, \ - .bcdUSB = { .maj = 2 }, \ - .bDeviceClass = USB_DEV_CLASS_SEE_IFACE, \ - .bDeviceSubClass = USB_DEV_SUBCLASS_SEE_IFACE, \ - .bDeviceProtocol = USB_DEV_PROTO_SEE_IFACE, \ - .bMaxPacketSize0 = EP0_BUFSIZE, \ - .idVendor = vid, \ - .idProduct = pid, \ - .bcdDevice = { .raw = 0 }, \ - .iManufacturer = 1, \ - .iProduct = 2, \ - .iSerialNumber = 3, \ - .bNumConfigurations = __PP_NARG(__VA_ARGS__), \ - }, \ +#define USB_INIT_DEVICE(vid, pid, manuf, product, ...) \ + { \ + .dev_desc = &(const struct usb_desc_dev_t){ \ + .bLength = sizeof(struct usb_desc_dev_t), \ + .bDescriptorType = USB_DESC_DEV, \ + .bcdUSB = { .maj = 2 }, \ + .bDeviceClass = USB_DEV_CLASS_SEE_IFACE, \ + .bDeviceSubClass = USB_DEV_SUBCLASS_SEE_IFACE, \ + .bDeviceProtocol = USB_DEV_PROTO_SEE_IFACE, \ + .bMaxPacketSize0 = EP0_BUFSIZE, \ + .idVendor = vid, \ + .idProduct = pid, \ + .bcdDevice = { .raw = 0 }, \ + .iManufacturer = 1, \ + .iProduct = 2, \ + .iSerialNumber = 3, \ + .bNumConfigurations = __PP_NARG(__VA_ARGS__), \ + }, \ .string_descs = (const struct usb_desc_string_t * const []){ \ - USB_DESC_STRING_LANG_ENUS, \ - USB_DESC_STRING(manuf), \ - USB_DESC_STRING(product), \ - USB_DESC_STRING_SERIALNO, \ - NULL \ - }, \ - .configs = { \ + USB_DESC_STRING_LANG_ENUS, \ + USB_DESC_STRING(manuf), \ + USB_DESC_STRING(product), \ + USB_DESC_STRING_SERIALNO, \ + NULL \ + }, \ + .configs = { \ __REPEAT(1, USB__INCREMENT, USB__DEFINE_CONFIG, __VA_ARGS__) \ - NULL \ - } \ + NULL \ + } \ } @@ -220,7 +220,7 @@ struct usb_desc_dev_t { uint8_t bLength; enum usb_desc_type bDescriptorType : 8; /* = USB_DESC_DEV */ - struct usb_bcd_t bcdUSB; /* = 0x0200 */ + struct usb_bcd_t bcdUSB; /* = 0x0200 */ enum usb_dev_class bDeviceClass : 8; enum usb_dev_subclass bDeviceSubClass : 8; enum usb_dev_proto bDeviceProtocol : 8; @@ -290,7 +290,7 @@ struct usb_desc_config_t { uint8_t bLength; enum usb_desc_type bDescriptorType : 8; /* = USB_DESC_CONFIG */ - uint16_t wTotalLength; /* size of config, iface, ep */ + uint16_t wTotalLength; /* size of config, iface, ep */ uint8_t bNumInterfaces; uint8_t bConfigurationValue; uint8_t iConfiguration; @@ -300,7 +300,7 @@ uint8_t self_powered : 1; uint8_t one : 1; /* = 1 for historical reasons */ }; - uint8_t bMaxPower; /* units of 2mA */ + uint8_t bMaxPower; /* units of 2mA */ } __packed; CTASSERT_SIZE_BYTE(struct usb_desc_config_t, 9);
--- a/Bootloader/usbotg.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Bootloader/usbotg.h Fri Jun 12 18:31:55 2015 -0700 @@ -29,271 +29,271 @@ */ struct USB_ADDINFO_t { - UNION_STRUCT_START(8); - uint8_t iehost : 1; - uint8_t _rsvd0 : 2; - uint8_t irqnum : 5; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t iehost : 1; + uint8_t _rsvd0 : 2; + uint8_t irqnum : 5; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_ADDINFO_t, 8); struct USB_OTGSTAT_t { - UNION_STRUCT_START(8); - uint8_t avbus : 1; - uint8_t _rsvd0 : 1; - uint8_t b_sess : 1; - uint8_t sessvld : 1; - uint8_t _rsvd1 : 1; - uint8_t line_state : 1; - uint8_t onemsec : 1; - uint8_t idchg : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t avbus : 1; + uint8_t _rsvd0 : 1; + uint8_t b_sess : 1; + uint8_t sessvld : 1; + uint8_t _rsvd1 : 1; + uint8_t line_state : 1; + uint8_t onemsec : 1; + uint8_t idchg : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_OTGSTAT_t, 8); struct USB_OTGCTL_t { - UNION_STRUCT_START(8); - uint8_t _rsvd0 : 2; - uint8_t otgen : 1; - uint8_t _rsvd1 : 1; - uint8_t dmlow : 1; - uint8_t dplow : 1; - uint8_t _rsvd2 : 1; - uint8_t dphigh : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t _rsvd0 : 2; + uint8_t otgen : 1; + uint8_t _rsvd1 : 1; + uint8_t dmlow : 1; + uint8_t dplow : 1; + uint8_t _rsvd2 : 1; + uint8_t dphigh : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_OTGCTL_t, 8); struct USB_ISTAT_t { - UNION_STRUCT_START(8); - uint8_t usbrst : 1; - uint8_t error : 1; - uint8_t softok : 1; - uint8_t tokdne : 1; - uint8_t sleep : 1; - uint8_t resume : 1; - uint8_t attach : 1; - uint8_t stall : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t usbrst : 1; + uint8_t error : 1; + uint8_t softok : 1; + uint8_t tokdne : 1; + uint8_t sleep : 1; + uint8_t resume : 1; + uint8_t attach : 1; + uint8_t stall : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_ISTAT_t, 8); struct USB_ERRSTAT_t { - UNION_STRUCT_START(8); - uint8_t piderr : 1; - uint8_t crc5eof : 1; - uint8_t crc16 : 1; - uint8_t dfn8 : 1; - uint8_t btoerr : 1; - uint8_t dmaerr : 1; - uint8_t _rsvd0 : 1; - uint8_t btserr : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t piderr : 1; + uint8_t crc5eof : 1; + uint8_t crc16 : 1; + uint8_t dfn8 : 1; + uint8_t btoerr : 1; + uint8_t dmaerr : 1; + uint8_t _rsvd0 : 1; + uint8_t btserr : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_ERRSTAT_t, 8); struct USB_STAT_t { - UNION_STRUCT_START(8); - uint8_t _rsvd0 : 2; - enum usb_ep_pingpong pingpong : 1; - enum usb_ep_dir dir : 1; - uint8_t ep : 4; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t _rsvd0 : 2; + enum usb_ep_pingpong pingpong : 1; + enum usb_ep_dir dir : 1; + uint8_t ep : 4; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_STAT_t, 8); struct USB_CTL_t { - union { - struct /* common */ { - uint8_t _rsvd1 : 1; - uint8_t oddrst : 1; - uint8_t resume : 1; - uint8_t _rsvd2 : 3; - uint8_t se0 : 1; - uint8_t jstate : 1; - }; - struct /* host */ { - uint8_t sofen : 1; - uint8_t _rsvd3 : 2; - uint8_t hostmodeen : 1; - uint8_t reset : 1; - uint8_t token_busy : 1; - uint8_t _rsvd4 : 2; - }; - struct /* device */ { - uint8_t usben : 1; - uint8_t _rsvd5 : 4; - uint8_t txd_suspend : 1; - uint8_t _rsvd6 : 2; - }; - uint8_t raw; - }; + union { + struct /* common */ { + uint8_t _rsvd1 : 1; + uint8_t oddrst : 1; + uint8_t resume : 1; + uint8_t _rsvd2 : 3; + uint8_t se0 : 1; + uint8_t jstate : 1; + }; + struct /* host */ { + uint8_t sofen : 1; + uint8_t _rsvd3 : 2; + uint8_t hostmodeen : 1; + uint8_t reset : 1; + uint8_t token_busy : 1; + uint8_t _rsvd4 : 2; + }; + struct /* device */ { + uint8_t usben : 1; + uint8_t _rsvd5 : 4; + uint8_t txd_suspend : 1; + uint8_t _rsvd6 : 2; + }; + uint8_t raw; + }; }; CTASSERT_SIZE_BIT(struct USB_CTL_t, 8); struct USB_ADDR_t { - UNION_STRUCT_START(8); - uint8_t addr : 7; - uint8_t lsen : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t addr : 7; + uint8_t lsen : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_ADDR_t, 8); struct USB_TOKEN_t { - UNION_STRUCT_START(8); - uint8_t endpt : 4; - enum usb_tok_pid pid : 4; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t endpt : 4; + enum usb_tok_pid pid : 4; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_TOKEN_t, 8); struct USB_ENDPT_t { - UNION_STRUCT_START(8); - uint8_t ephshk : 1; - uint8_t epstall : 1; - uint8_t eptxen : 1; - uint8_t eprxen : 1; - uint8_t epctldis : 1; - uint8_t _rsvd0 : 1; - uint8_t retrydis : 1; - uint8_t hostwohub : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t ephshk : 1; + uint8_t epstall : 1; + uint8_t eptxen : 1; + uint8_t eprxen : 1; + uint8_t epctldis : 1; + uint8_t _rsvd0 : 1; + uint8_t retrydis : 1; + uint8_t hostwohub : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_ENDPT_t, 8); struct USB_USBCTRL_t { - UNION_STRUCT_START(8); - uint8_t _rsvd0 : 6; - uint8_t pde : 1; - uint8_t susp : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t _rsvd0 : 6; + uint8_t pde : 1; + uint8_t susp : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_USBCTRL_t, 8); struct USB_OBSERVE_t { - UNION_STRUCT_START(8); - uint8_t _rsvd0 : 4; - uint8_t dmpd : 1; - uint8_t _rsvd1 : 1; - uint8_t dppd : 1; - uint8_t dppu : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t _rsvd0 : 4; + uint8_t dmpd : 1; + uint8_t _rsvd1 : 1; + uint8_t dppd : 1; + uint8_t dppu : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_OBSERVE_t, 8); struct USB_CONTROL_t { - UNION_STRUCT_START(8); - uint8_t _rsvd0 : 4; - uint8_t dppullupnonotg : 1; - uint8_t _rsvd1 : 3; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t _rsvd0 : 4; + uint8_t dppullupnonotg : 1; + uint8_t _rsvd1 : 3; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_CONTROL_t, 8); struct USB_USBTRC0_t { - UNION_STRUCT_START(8); - uint8_t usb_resume_int : 1; - uint8_t sync_det : 1; - uint8_t _rsvd0 : 3; - uint8_t usbresmen : 1; - uint8_t _rsvd1 : 1; - uint8_t usbreset : 1; - UNION_STRUCT_END; + UNION_STRUCT_START(8); + uint8_t usb_resume_int : 1; + uint8_t sync_det : 1; + uint8_t _rsvd0 : 3; + uint8_t usbresmen : 1; + uint8_t _rsvd1 : 1; + uint8_t usbreset : 1; + UNION_STRUCT_END; }; CTASSERT_SIZE_BIT(struct USB_USBTRC0_t, 8); struct USB_t { - uint8_t perid; - uint8_t _pad0[3]; - uint8_t idcomp; - uint8_t _pad1[3]; - uint8_t rev; - uint8_t _pad2[3]; - struct USB_ADDINFO_t addinfo; - uint8_t _pad3[3]; - struct USB_OTGSTAT_t otgistat; - uint8_t _pad4[3]; - struct USB_OTGSTAT_t otgicr; - uint8_t _pad5[3]; - struct USB_OTGSTAT_t otgstat; - uint8_t _pad6[3]; - struct USB_OTGCTL_t otgctl; - uint8_t _pad7[3]; - uint8_t _pad8[0x80 - 0x20]; - struct USB_ISTAT_t istat; - uint8_t _pad9[3]; - struct USB_ISTAT_t inten; - uint8_t _pad10[3]; - struct USB_ERRSTAT_t errstat; - uint8_t _pad11[3]; - struct USB_ERRSTAT_t erren; - uint8_t _pad12[3]; - struct USB_STAT_t stat; - uint8_t _pad13[3]; - struct USB_CTL_t ctl; - uint8_t _pad14[3]; - struct USB_ADDR_t addr; - uint8_t _pad15[3]; - uint8_t bdtpage1; - uint8_t _pad16[3]; - uint8_t frmnuml; - uint8_t _pad17[3]; - struct { - uint8_t frmnumh : 3; - uint8_t _rsvd0 : 5; - }; - uint8_t _pad18[3]; - struct USB_TOKEN_t token; - uint8_t _pad19[3]; - uint8_t softhld; - uint8_t _pad20[3]; - uint8_t bdtpage2; - uint8_t _pad21[3]; - uint8_t bdtpage3; - uint8_t _pad22[3]; - uint8_t _pad23[0xc0 - 0xb8]; - struct { - struct USB_ENDPT_t; - uint8_t _pad24[3]; - } endpt[16]; - struct USB_USBCTRL_t usbctrl; - uint8_t _pad25[3]; - struct USB_OBSERVE_t observe; - uint8_t _pad26[3]; - struct USB_CONTROL_t control; - uint8_t _pad27[3]; - struct USB_USBTRC0_t usbtrc0; - uint8_t _pad28[3]; - uint8_t _pad29[4]; - uint8_t usbfrmadjust; - uint8_t _pad30[3]; + uint8_t perid; + uint8_t _pad0[3]; + uint8_t idcomp; + uint8_t _pad1[3]; + uint8_t rev; + uint8_t _pad2[3]; + struct USB_ADDINFO_t addinfo; + uint8_t _pad3[3]; + struct USB_OTGSTAT_t otgistat; + uint8_t _pad4[3]; + struct USB_OTGSTAT_t otgicr; + uint8_t _pad5[3]; + struct USB_OTGSTAT_t otgstat; + uint8_t _pad6[3]; + struct USB_OTGCTL_t otgctl; + uint8_t _pad7[3]; + uint8_t _pad8[0x80 - 0x20]; + struct USB_ISTAT_t istat; + uint8_t _pad9[3]; + struct USB_ISTAT_t inten; + uint8_t _pad10[3]; + struct USB_ERRSTAT_t errstat; + uint8_t _pad11[3]; + struct USB_ERRSTAT_t erren; + uint8_t _pad12[3]; + struct USB_STAT_t stat; + uint8_t _pad13[3]; + struct USB_CTL_t ctl; + uint8_t _pad14[3]; + struct USB_ADDR_t addr; + uint8_t _pad15[3]; + uint8_t bdtpage1; + uint8_t _pad16[3]; + uint8_t frmnuml; + uint8_t _pad17[3]; + struct { + uint8_t frmnumh : 3; + uint8_t _rsvd0 : 5; + }; + uint8_t _pad18[3]; + struct USB_TOKEN_t token; + uint8_t _pad19[3]; + uint8_t softhld; + uint8_t _pad20[3]; + uint8_t bdtpage2; + uint8_t _pad21[3]; + uint8_t bdtpage3; + uint8_t _pad22[3]; + uint8_t _pad23[0xc0 - 0xb8]; + struct { + struct USB_ENDPT_t; + uint8_t _pad24[3]; + } endpt[16]; + struct USB_USBCTRL_t usbctrl; + uint8_t _pad25[3]; + struct USB_OBSERVE_t observe; + uint8_t _pad26[3]; + struct USB_CONTROL_t control; + uint8_t _pad27[3]; + struct USB_USBTRC0_t usbtrc0; + uint8_t _pad28[3]; + uint8_t _pad29[4]; + uint8_t usbfrmadjust; + uint8_t _pad30[3]; }; CTASSERT_SIZE_BYTE(struct USB_t, 0x118); struct USB_BD_t { - struct USB_BD_BITS_t { - union { - struct { - uint32_t _rsvd0 : 2; - uint32_t stall : 1; - uint32_t dts : 1; - uint32_t ninc : 1; - uint32_t keep : 1; - enum usb_data01 data01 : 1; - uint32_t own : 1; - uint32_t _rsvd1 : 8; - uint32_t bc : 10; - uint32_t _rsvd2 : 6; - }; - struct /* processor */ { - uint32_t _rsvd5 : 2; - enum usb_tok_pid tok_pid : 4; - uint32_t _rsvd6 : 26; - }; - uint32_t raw; - }; - }; - void *addr; + struct USB_BD_BITS_t { + union { + struct { + uint32_t _rsvd0 : 2; + uint32_t stall : 1; + uint32_t dts : 1; + uint32_t ninc : 1; + uint32_t keep : 1; + enum usb_data01 data01 : 1; + uint32_t own : 1; + uint32_t _rsvd1 : 8; + uint32_t bc : 10; + uint32_t _rsvd2 : 6; + }; + struct /* processor */ { + uint32_t _rsvd5 : 2; + enum usb_tok_pid tok_pid : 4; + uint32_t _rsvd6 : 26; + }; + uint32_t raw; + }; + }; + void *addr; }; CTASSERT_SIZE_BYTE(struct USB_BD_t, 8);
--- a/CMakeLists.txt Sun Mar 08 22:35:55 2015 -0700 +++ b/CMakeLists.txt Fri Jun 12 18:31:55 2015 -0700 @@ -17,14 +17,14 @@ #| You _MUST_ clean the build directory if you change this value #| set( CHIP -# "at90usb162" # Teensy 1.0 (avr) -# "atmega32u4" # Teensy 2.0 (avr) -# "at90usb646" # Teensy++ 1.0 (avr) -# "at90usb1286" # Teensy++ 2.0 (avr) -# "mk20dx128" # Teensy 3.0 (arm) +# "at90usb162" # Teensy 1.0 (avr) +# "atmega32u4" # Teensy 2.0 (avr) +# "at90usb646" # Teensy++ 1.0 (avr) +# "at90usb1286" # Teensy++ 2.0 (avr) +# "mk20dx128" # Teensy 3.0 (arm) "mk20dx128vlf5" # McHCK mk20dx128vlf5 -# "mk20dx256" # Teensy 3.1 (arm) -# "mk20dx256vlh7" # Kiibohd-dfu mk20dx256vlh7 +# "mk20dx256" # Teensy 3.1 (arm) +# "mk20dx256vlh7" # Kiibohd-dfu mk20dx256vlh7 CACHE STRING "Microcontroller Chip" ) @@ -37,8 +37,8 @@ #| Stick with gcc unless you know what you're doing #| Currently only arm is supported with clang set( COMPILER - "gcc" # arm-none-eabi-gcc / avr-gcc - Default -# "clang" # arm-none-eabi + "gcc" # arm-none-eabi-gcc / avr-gcc - Default +# "clang" # arm-none-eabi CACHE STRING "Compiler Type" )
--- a/Debug/cli/cli.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Debug/cli/cli.c Fri Jun 12 18:31:55 2015 -0700 @@ -35,6 +35,7 @@ // ----- Variables ----- // Basic command dictionary +CLIDict_Entry( clear, "Clear the screen."); CLIDict_Entry( cliDebug, "Enables/Disables hex output of the most recent cli input." ); CLIDict_Entry( help, "You're looking at it :P" ); CLIDict_Entry( led, "Enables/Disables indicator LED. Try a couple times just in case the LED is in an odd state.\r\n\t\t\033[33mWarning\033[0m: May adversely affect some modules..." ); @@ -44,6 +45,7 @@ CLIDict_Entry( version, "Version information about this firmware." ); CLIDict_Def( basicCLIDict, "General Commands" ) = { + CLIDict_Item( clear ), CLIDict_Item( cliDebug ), CLIDict_Item( help ), CLIDict_Item( led ), @@ -70,6 +72,11 @@ // Reset the Line Buffer CLILineBufferCurrent = 0; + // History starts empty + CLIHistoryHead = 0; + CLIHistoryCurrent = 0; + CLIHistoryTail = 0; + // Set prompt prompt(); @@ -152,6 +159,22 @@ // Process the current line buffer CLI_commandLookup(); + // Add the command to the history + CLI_saveHistory( CLILineBuffer ); + + // Keep the array circular, discarding the older entries + if ( CLIHistoryTail < CLIHistoryHead ) + CLIHistoryHead = ( CLIHistoryHead + 1 ) % CLIMaxHistorySize; + CLIHistoryTail++; + if ( CLIHistoryTail == CLIMaxHistorySize ) + { + CLIHistoryTail = 0; + CLIHistoryHead = 1; + } + + CLIHistoryCurrent = CLIHistoryTail; // 'Up' starts at the last item + CLI_saveHistory( NULL ); // delete the old temp buffer + // Reset the buffer CLILineBufferCurrent = 0; @@ -173,9 +196,38 @@ // Doesn't look like it will happen *that* often, so not handling it for now -HaaTa return; - case 0x1B: // Esc - // Check for escape sequence - // TODO + case 0x1B: // Esc / Escape codes + // Check for other escape sequence + + // \e[ is an escape code in vt100 compatable terminals + if ( CLILineBufferCurrent >= prev_buf_pos + 3 + && CLILineBuffer[ prev_buf_pos ] == 0x1B + && CLILineBuffer[ prev_buf_pos + 1] == 0x5B ) + { + // Arrow Keys: A (0x41) = Up, B (0x42) = Down, C (0x43) = Right, D (0x44) = Left + + if ( CLILineBuffer[ prev_buf_pos + 2 ] == 0x41 ) // Hist prev + { + if ( CLIHistoryCurrent == CLIHistoryTail ) + { + // Is first time pressing arrow. Save the current buffer + CLILineBuffer[ prev_buf_pos ] = '\0'; + CLI_saveHistory( CLILineBuffer ); + } + + // Grab the previus item from the history if there is one + if ( RING_PREV( CLIHistoryCurrent ) != RING_PREV( CLIHistoryHead ) ) + CLIHistoryCurrent = RING_PREV( CLIHistoryCurrent ); + CLI_retreiveHistory( CLIHistoryCurrent ); + } + if ( CLILineBuffer[ prev_buf_pos + 2 ] == 0x42 ) // Hist next + { + // Grab the next item from the history if it exists + if ( RING_NEXT( CLIHistoryCurrent ) != RING_NEXT( CLIHistoryTail ) ) + CLIHistoryCurrent = RING_NEXT( CLIHistoryCurrent ); + CLI_retreiveHistory( CLIHistoryCurrent ); + } + } return; case 0x08: @@ -346,10 +398,63 @@ } } +inline int CLI_wrap( int kX, int const kLowerBound, int const kUpperBound ) +{ + int range_size = kUpperBound - kLowerBound + 1; + + if ( kX < kLowerBound ) + kX += range_size * ((kLowerBound - kX) / range_size + 1); + + return kLowerBound + (kX - kLowerBound) % range_size; +} + +inline void CLI_saveHistory( char *buff ) +{ + if ( buff == NULL ) + { + //clear the item + CLIHistoryBuffer[ CLIHistoryTail ][ 0 ] = '\0'; + return; + } + + // Copy the line to the history + int i; + for (i = 0; i < CLILineBufferCurrent; i++) + { + CLIHistoryBuffer[ CLIHistoryTail ][ i ] = CLILineBuffer[ i ]; + } +} + +void CLI_retreiveHistory( int index ) +{ + char *histMatch = CLIHistoryBuffer[ index ]; + + // Reset the buffer + CLILineBufferCurrent = 0; + + // Reprint the prompt (automatically clears the line) + prompt(); + + // Display the command + dPrint( histMatch ); + + // There are no index counts, so just copy the whole string to the input buffe + CLILineBufferCurrent = 0; + while ( *histMatch != '\0' ) + { + CLILineBuffer[ CLILineBufferCurrent++ ] = *histMatch++; + } +} + // ----- CLI Command Functions ----- +void cliFunc_clear( char* args) +{ + print("\033[2J\033[H\r"); // Erases the whole screen +} + void cliFunc_cliDebug( char* args ) { // Toggle Hex Debug Mode
--- a/Debug/cli/cli.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Debug/cli/cli.h Fri Jun 12 18:31:55 2015 -0700 @@ -1,4 +1,4 @@ -/* Copyright (C) 2014 by Jacob Alexander +/* Copyright (C) 2014-2015 by Jacob Alexander * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,9 +34,9 @@ // ----- Defines ----- #define CLILineBufferMaxSize 100 -#define CLIMaxDictionaries 5 +#define CLIMaxDictionaries 10 #define CLIEntryTabAlign 13 - +#define CLIMaxHistorySize 10 // ----- Macros ----- @@ -67,6 +67,8 @@ const char name##CLIDict_DescEntry[] = description; #endif +#define RING_PREV(i) CLI_wrap(i - 1, 0, CLIMaxHistorySize - 1) +#define RING_NEXT(i) CLI_wrap(i + 1, 0, CLIMaxHistorySize - 1) // ----- Structs ----- @@ -90,6 +92,13 @@ char* CLIDictNames[CLIMaxDictionaries]; uint8_t CLIDictionariesUsed; +// History +char CLIHistoryBuffer[CLIMaxHistorySize][CLILineBufferMaxSize]; +uint8_t CLIHistoryHead; +uint8_t CLIHistoryTail; +int8_t CLIHistoryCurrent; + +// Debug uint8_t CLILEDState; uint8_t CLIHexDebugMode; @@ -102,12 +111,16 @@ void CLI_registerDictionary( const CLIDictItem *cmdDict, const char* dictName ); void CLI_argumentIsolation( char* string, char** first, char** second ); +int CLI_wrap( int x, int low, int high ); void CLI_commandLookup(); void CLI_tabCompletion(); +void CLI_saveHistory( char *buff ); +void CLI_retreiveHistory( int index ); // CLI Command Functions void cliFunc_arch ( char* args ); void cliFunc_chip ( char* args ); +void cliFunc_clear ( char* args ); void cliFunc_cliDebug( char* args ); void cliFunc_device ( char* args ); void cliFunc_help ( char* args );
--- a/Debug/print/print.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Debug/print/print.h Fri Jun 12 18:31:55 2015 -0700 @@ -54,11 +54,11 @@ // Special Msg Constructs (Uses VT100 tags) #define dPrintMsg(colour_code_str,msg,...) \ - printstrs("\033[", colour_code_str, "m", msg, "\033[0m - ", __VA_ARGS__, NL, "\0\0\0") + printstrs("\033[", colour_code_str, "m", msg, "\033[0m - ", __VA_ARGS__, NL, "\0\0\0") #define printMsgNL(colour_code_str,msg,str) \ - print("\033[" colour_code_str "m" msg "\033[0m - " str NL) + print("\033[" colour_code_str "m" msg "\033[0m - " str NL) #define printMsg(colour_code_str,msg,str) \ - print("\033[" colour_code_str "m" msg "\033[0m - " str) + print("\033[" colour_code_str "m" msg "\033[0m - " str) // Info Messages #define info_dPrint(...) dPrintMsg ("1;32", "INFO", __VA_ARGS__) // Info Msg
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Keyboards/README.markdown Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,37 @@ +Keyboard Compiler Scripts +========================= + +Scripts for major keyboards designed using the Kiibohd firmware. +Please refer to `<script> --help` for specific details. + +Refer to the [wiki](https://github.com/kiibohd/controller/wiki) on setting up your system for compiling. + + +Build Steps +----------- + +* Try to build once to make sure your system is setup correctly +* Add any .kll files in the build directory you want +* Edit `<script>` to include the new .kll files +* Rebuild + + +Example +------- + +```bash +./infinity.bash +``` + + +Projects +-------- + +* infinity.bash (Infinity Keyboard 2014/10/15) +* template.bash (Example template for new keyboards) + + +**Extra files** + +* cmake.bash (Used by the compilation script, does nothing on it's own) +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Keyboards/cmake.bash Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,88 @@ +#!/bin/bash +# This is bash lib file for the convenience build scripts +# Don't call this script directly +# Jacob Alexander 2015 + +# Make sure all of the relevant variables have been set +# NOTE: PartialMaps and DefaultMap do not have to be set +VariablesList=(BuildPath BaseMap ScanModule MacroModule OutputModule DebugModule Chip Compiler) +ExitEarly=false +for var in ${VariablesList[@]}; do + if [ -z ${!var+x} ]; then + echo "ERROR: Unset variable => '${var}'" + ExitEarly=true + fi +done + +# Error was detected, exit immediately +if $ExitEarly; then + exit 1 +fi + + +# Prepare PartialMaps +PartialMapsExpanded="${PartialMaps[1]}" +count=2 # Start the loop at index 2 +while [ "$count" -le "${#PartialMaps[@]}" ]; do + PartialMapsExpanded="${PartialMapsExpanded};${PartialMaps[count]}" + count=$(($count+1)) +done + + +# Internal Variables +CMakeListsPath="../.." +PROG_NAME=$(basename $0) + + +# Process the command line arguments (if any) +while (( "$#" >= "1" )); do + # Scan each argument + key="$1" + case $key in + -c|--cmakelists-path) + CMakeListsPath="$2" + shift + ;; + -f|--force-rebuild) + # Remove the old directory first + rm -rf "${BuildPath}" + ;; + -o|--output-path) + BuildPath="$2" + shift + ;; + -h|--help) + echo "Usage: $PROG_NAME [options...]" + echo "" + echo "Convenience script to build the source of a given keyboard." + echo "Edit '$PROG_NAME' to configure the keyboard options such as KLL layouts." + echo "" + echo "Arguments:" + echo " -c, --cmakelists-path PATH Set the path of CMakeLists.txt" + echo " Default: ${CMakeListsPath}" + echo " -f, --force-rebuild Deletes the old build directory and rebuilds from scratch." + echo " -o, --output-path PATH Set the path of the build files." + echo " Default: ${BuildPath}" + echo " -h, --help This message." + exit 1 + ;; + *) + echo "INVALID ARG: '$1'" + exit 2 + ;; + esac + + # Shift to the next argument + shift +done + + +# Run CMake commands +## TODO Check for windows and do windows specific things ## +mkdir -p "${BuildPath}" +cd "${BuildPath}" +cmake -DCHIP="${Chip}" -DCOMPILER="${Compiler}" -DScanModule="${ScanModule}" -DMacroModule="${MacroModule}" -DOutputModule="${OutputModule}" -DDebugModule="${DebugModule}" -DBaseMap="${BaseMap}" -DDefaultMap="${DefaultMap}" -DPartialMaps="${PartialMapsExpanded}" "${CMakeListsPath}" +make + +echo "Firmware has been compiled into: '${BuildPath}'" +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Keyboards/infinity.bash Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,72 @@ +#!/bin/bash +# This is a build script template +# These build scripts are just a convenience for configuring your keyboard (less daunting than CMake) +# Jacob Alexander 2015 + + + +################# +# Configuration # +################# + +# Feel free to change the variables in this section to configure your keyboard + +BuildPath="template" + +## KLL Configuration ## + +# Generally shouldn't be changed, this will affect every layer +BaseMap="defaultMap" + +# This is the default layer of the keyboard +# NOTE: To combine kll files into a single layout, separate them by spaces +# e.g. DefaultMap="mylayout mylayoutmod" +DefaultMap="md1Overlay stdFuncMap" + +# This is where you set the additional layers +# NOTE: Indexing starts at 1 +# NOTE: Each new layer is another array entry +# e.g. PartialMaps[1]="layer1 layer1mod" +# PartialMaps[2]="layer2" +# PartialMaps[3]="layer3" +PartialMaps[1]="hhkbpro2" + + + +########################## +# Advanced Configuration # +########################## + +# Don't change the variables in this section unless you know what you're doing +# These are useful for completely custom keyboards +# NOTE: Changing any of these variables will require a force build to compile correctly + +# Keyboard Module Configuration +ScanModule="MD1" +MacroModule="PartialMap" +OutputModule="pjrcUSB" +DebugModule="full" + +# Microcontroller +Chip="mk20dx128vlf5" + +# Compiler Selection +Compiler="gcc" + + + +######################## +# Bash Library Include # +######################## + +# Shouldn't need to touch this section + +# Check if the library can be found +if [ ! -f cmake.bash ]; then + echo "ERROR: Cannot find 'cmake.bash'" + exit 1 +fi + +# Load the library +source cmake.bash +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Keyboards/template.bash Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,73 @@ +#!/bin/bash +# This is a build script template +# These build scripts are just a convenience for configuring your keyboard (less daunting than CMake) +# Jacob Alexander 2015 + + + +################# +# Configuration # +################# + +# Feel free to change the variables in this section to configure your keyboard + +BuildPath="template" + +## KLL Configuration ## + +# Generally shouldn't be changed, this will affect every layer +BaseMap="defaultMap" + +# This is the default layer of the keyboard +# NOTE: To combine kll files into a single layout, separate them by spaces +# e.g. DefaultMap="mylayout mylayoutmod" +DefaultMap="md1Overlay stdFuncMap" + +# This is where you set the additional layers +# NOTE: Indexing starts at 1 +# NOTE: Each new layer is another array entry +# e.g. PartialMaps[1]="layer1 layer1mod" +# PartialMaps[2]="layer2" +# PartialMaps[3]="layer3" +PartialMaps[1]="hhkbpro2" +PartialMaps[2]="colemak" + + + +########################## +# Advanced Configuration # +########################## + +# Don't change the variables in this section unless you know what you're doing +# These are useful for completely custom keyboards +# NOTE: Changing any of these variables will require a force build to compile correctly + +# Keyboard Module Configuration +ScanModule="MD1" +MacroModule="PartialMap" +OutputModule="pjrcUSB" +DebugModule="full" + +# Microcontroller +Chip="mk20dx128vlf5" + +# Compiler Selection +Compiler="gcc" + + + +######################## +# Bash Library Include # +######################## + +# Shouldn't need to touch this section + +# Check if the library can be found +if [ ! -f cmake.bash ]; then + echo "ERROR: Cannot find 'cmake.bash'" + exit 1 +fi + +# Load the library +source cmake.bash +
--- a/Lib/CMake/kll.cmake Sun Mar 08 22:35:55 2015 -0700 +++ b/Lib/CMake/kll.cmake Fri Jun 12 18:31:55 2015 -0700 @@ -57,9 +57,11 @@ if ( NOT EXISTS ${pathname}/${BaseMap}.kll ) set ( BaseMap_Args ${BaseMap_Args} ${pathname}/defaultMap.kll ) set ( KLL_DEPENDS ${KLL_DEPENDS} ${pathname}/defaultMap.kll ) -else () +elseif ( EXISTS "${pathname}/${BaseMap}.kll" ) set ( BaseMap_Args ${BaseMap_Args} ${pathname}/${BaseMap}.kll ) set ( KLL_DEPENDS ${KLL_DEPENDS} ${pathname}/${BaseMap}.kll ) +else () + message ( FATAL "Could not find '${BaseMap}.kll'" ) endif () #| Configure DefaultMap if specified @@ -71,10 +73,12 @@ # Check if kll file is in build directory, otherwise default to layout directory if ( EXISTS "${PROJECT_BINARY_DIR}/${MAP}.kll" ) set ( DefaultMap_Args ${DefaultMap_Args} ${MAP}.kll ) - set ( KLL_DEPENDS ${KLL_DEPENDS} ${MAP}.kll ) - else () + set ( KLL_DEPENDS ${KLL_DEPENDS} ${PROJECT_BINARY_DIR}/${MAP}.kll ) + elseif ( EXISTS "${PROJECT_SOURCE_DIR}/kll/layouts/${MAP}.kll" ) set ( DefaultMap_Args ${DefaultMap_Args} ${PROJECT_SOURCE_DIR}/kll/layouts/${MAP}.kll ) set ( KLL_DEPENDS ${KLL_DEPENDS} ${PROJECT_SOURCE_DIR}/kll/layouts/${MAP}.kll ) + else () + message ( FATAL "Could not find '${MAP}.kll'" ) endif () endforeach () endif () @@ -91,10 +95,12 @@ # Check if kll file is in build directory, otherwise default to layout directory if ( EXISTS "${PROJECT_BINARY_DIR}/${MAP_PART}.kll" ) set ( PartialMap_Args ${PartialMap_Args} ${MAP_PART}.kll ) - set ( KLL_DEPENDS ${KLL_DEPENDS} ${MAP_PART}.kll ) - else () + set ( KLL_DEPENDS ${KLL_DEPENDS} ${PROJECT_BINARY_DIR}/${MAP_PART}.kll ) + elseif ( EXISTS "${PROJECT_SOURCE_DIR}/kll/layouts/${MAP_PART}.kll" ) set ( PartialMap_Args ${PartialMap_Args} ${PROJECT_SOURCE_DIR}/kll/layouts/${MAP_PART}.kll ) set ( KLL_DEPENDS ${KLL_DEPENDS} ${PROJECT_SOURCE_DIR}/kll/layouts/${MAP_PART}.kll ) + else () + message ( FATAL "Could not find '${MAP_PART}.kll'" ) endif () endforeach () endforeach ()
--- a/Lib/_buildvars.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Lib/_buildvars.h Fri Jun 12 18:31:55 2015 -0700 @@ -55,8 +55,8 @@ // Windows, even though the driver is supplied by Microsoft, an // INF file is needed to load the driver. These numbers need to // match the INF file. -#define VENDOR_ID @VENDOR_ID@ -#define PRODUCT_ID @PRODUCT_ID@ +#define VENDOR_ID @VENDOR_ID@ +#define PRODUCT_ID @PRODUCT_ID@ #endif
--- a/Lib/delay.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Lib/delay.h Fri Jun 12 18:31:55 2015 -0700 @@ -69,9 +69,9 @@ uint32_t n = usec << 3; #endif asm volatile( - "L_%=_delayMicroseconds:" "\n\t" - "subs %0, #1" "\n\t" - "bne L_%=_delayMicroseconds" "\n" + "L_%=_delayMicroseconds:" "\n\t" + "subs %0, #1" "\n\t" + "bne L_%=_delayMicroseconds" "\n" : "+r" (n) : ); }
--- a/Lib/mk20dx.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Lib/mk20dx.c Fri Jun 12 18:31:55 2015 -0700 @@ -400,6 +400,7 @@ 0x03, // Flash nonvolatile option byte FOPT 0xFF, // EEPROM Protection Byte FEPROT 0xFF, // Data Flash Protection Byte FDPROT +}; #endif @@ -410,12 +411,12 @@ __attribute__((noreturn)) static inline void jump_to_app( uintptr_t addr ) { - // addr is in r0 - __asm__("ldr sp, [%[addr], #0]\n" - "ldr pc, [%[addr], #4]" - :: [addr] "r" (addr)); - // NOTREACHED - __builtin_unreachable(); + // addr is in r0 + __asm__("ldr sp, [%[addr], #0]\n" + "ldr pc, [%[addr], #4]" + :: [addr] "r" (addr)); + // NOTREACHED + __builtin_unreachable(); } #endif @@ -526,7 +527,7 @@ NVIC_SET_PRIORITY( i, 128 ); } - // FLL at 48MHz + // FLL at 48MHz MCG_C4 = MCG_C4_DMX32 | MCG_C4_DRST_DRS( 1 ); // USB Clock and FLL select @@ -534,7 +535,7 @@ // Teensy 3.0 and 3.1 and Kiibohd-dfu (mk20dx256vlh7) #else - SCB_VTOR = 0; // use vector table in flash + SCB_VTOR = 0; // use vector table in flash // default all interrupts to medium priority level for ( unsigned int i = 0; i < NVIC_NUM_INTERRUPTS; i++ )
--- a/Lib/mk20dx.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Lib/mk20dx.h Fri Jun 12 18:31:55 2015 -0700 @@ -61,18 +61,18 @@ // ----- Registers ----- // chapter 11: Port control and interrupts (PORT) -#define PORT_PCR_ISF (uint32_t)0x01000000 // Interrupt Status Flag -#define PORT_PCR_IRQC(n) (uint32_t)(((n) & 15) << 16) // Interrupt Configuration -#define PORT_PCR_IRQC_MASK (uint32_t)0x000F0000 -#define PORT_PCR_LK (uint32_t)0x00008000 // Lock Register -#define PORT_PCR_MUX(n) (uint32_t)(((n) & 7) << 8) // Pin Mux Control -#define PORT_PCR_MUX_MASK (uint32_t)0x00000700 -#define PORT_PCR_DSE (uint32_t)0x00000040 // Drive Strength Enable -#define PORT_PCR_ODE (uint32_t)0x00000020 // Open Drain Enable -#define PORT_PCR_PFE (uint32_t)0x00000010 // Passive Filter Enable -#define PORT_PCR_SRE (uint32_t)0x00000004 // Slew Rate Enable -#define PORT_PCR_PE (uint32_t)0x00000002 // Pull Enable -#define PORT_PCR_PS (uint32_t)0x00000001 // Pull Select +#define PORT_PCR_ISF (uint32_t)0x01000000 // Interrupt Status Flag +#define PORT_PCR_IRQC(n) (uint32_t)(((n) & 15) << 16) // Interrupt Configuration +#define PORT_PCR_IRQC_MASK (uint32_t)0x000F0000 +#define PORT_PCR_LK (uint32_t)0x00008000 // Lock Register +#define PORT_PCR_MUX(n) (uint32_t)(((n) & 7) << 8) // Pin Mux Control +#define PORT_PCR_MUX_MASK (uint32_t)0x00000700 +#define PORT_PCR_DSE (uint32_t)0x00000040 // Drive Strength Enable +#define PORT_PCR_ODE (uint32_t)0x00000020 // Open Drain Enable +#define PORT_PCR_PFE (uint32_t)0x00000010 // Passive Filter Enable +#define PORT_PCR_SRE (uint32_t)0x00000004 // Slew Rate Enable +#define PORT_PCR_PE (uint32_t)0x00000002 // Pull Enable +#define PORT_PCR_PS (uint32_t)0x00000001 // Pull Select #define PORTA_PCR0 *(volatile uint32_t *)0x40049000 // Pin Control Register n #define PORTA_PCR1 *(volatile uint32_t *)0x40049004 // Pin Control Register n #define PORTA_PCR2 *(volatile uint32_t *)0x40049008 // Pin Control Register n @@ -253,64 +253,64 @@ #define SIM_SOPT1 *(volatile uint32_t *)0x40047000 // System Options Register 1 #define SIM_SOPT1CFG *(volatile uint32_t *)0x40047004 // SOPT1 Configuration Register #define SIM_SOPT2 *(volatile uint32_t *)0x40048004 // System Options Register 2 -#define SIM_SOPT2_USBSRC (uint32_t)0x00040000 // 0=USB_CLKIN, 1=FFL/PLL -#define SIM_SOPT2_PLLFLLSEL (uint32_t)0x00010000 // 0=FLL, 1=PLL -#define SIM_SOPT2_TRACECLKSEL (uint32_t)0x00001000 // 0=MCGOUTCLK, 1=CPU -#define SIM_SOPT2_PTD7PAD (uint32_t)0x00000800 // 0=normal, 1=double drive PTD7 -#define SIM_SOPT2_CLKOUTSEL(n) (uint32_t)(((n) & 7) << 5) // Selects the clock to output on the CLKOUT pin. -#define SIM_SOPT2_RTCCLKOUTSEL (uint32_t)0x00000010 // RTC clock out select -#define SIM_SOPT4 *(volatile uint32_t *)0x4004800C // System Options Register 4 -#define SIM_SOPT5 *(volatile uint32_t *)0x40048010 // System Options Register 5 -#define SIM_SOPT7 *(volatile uint32_t *)0x40048018 // System Options Register 7 -#define SIM_SDID *(const uint32_t *)0x40048024 // System Device Identification Register -#define SIM_SCGC2 *(volatile uint32_t *)0x4004802C // System Clock Gating Control Register 2 -#define SIM_SCGC2_DAC0 (uint32_t)0x00001000 // DAC0 Clock Gate Control -#define SIM_SCGC3 *(volatile uint32_t *)0x40048030 // System Clock Gating Control Register 3 -#define SIM_SCGC3_ADC1 (uint32_t)0x08000000 // ADC1 Clock Gate Control -#define SIM_SCGC3_FTM2 (uint32_t)0x01000000 // FTM2 Clock Gate Control -#define SIM_SCGC4 *(volatile uint32_t *)0x40048034 // System Clock Gating Control Register 4 -#define SIM_SCGC4_VREF (uint32_t)0x00100000 // VREF Clock Gate Control -#define SIM_SCGC4_CMP (uint32_t)0x00080000 // Comparator Clock Gate Control -#define SIM_SCGC4_USBOTG (uint32_t)0x00040000 // USB Clock Gate Control -#define SIM_SCGC4_UART2 (uint32_t)0x00001000 // UART2 Clock Gate Control -#define SIM_SCGC4_UART1 (uint32_t)0x00000800 // UART1 Clock Gate Control -#define SIM_SCGC4_UART0 (uint32_t)0x00000400 // UART0 Clock Gate Control -#define SIM_SCGC4_I2C1 (uint32_t)0x00000080 // I2C1 Clock Gate Control -#define SIM_SCGC4_I2C0 (uint32_t)0x00000040 // I2C0 Clock Gate Control -#define SIM_SCGC4_CMT (uint32_t)0x00000004 // CMT Clock Gate Control -#define SIM_SCGC4_EWM (uint32_t)0x00000002 // EWM Clock Gate Control +#define SIM_SOPT2_USBSRC (uint32_t)0x00040000 // 0=USB_CLKIN, 1=FFL/PLL +#define SIM_SOPT2_PLLFLLSEL (uint32_t)0x00010000 // 0=FLL, 1=PLL +#define SIM_SOPT2_TRACECLKSEL (uint32_t)0x00001000 // 0=MCGOUTCLK, 1=CPU +#define SIM_SOPT2_PTD7PAD (uint32_t)0x00000800 // 0=normal, 1=double drive PTD7 +#define SIM_SOPT2_CLKOUTSEL(n) (uint32_t)(((n) & 7) << 5) // Selects the clock to output on the CLKOUT pin. +#define SIM_SOPT2_RTCCLKOUTSEL (uint32_t)0x00000010 // RTC clock out select +#define SIM_SOPT4 *(volatile uint32_t *)0x4004800C // System Options Register 4 +#define SIM_SOPT5 *(volatile uint32_t *)0x40048010 // System Options Register 5 +#define SIM_SOPT7 *(volatile uint32_t *)0x40048018 // System Options Register 7 +#define SIM_SDID *(const uint32_t *)0x40048024 // System Device Identification Register +#define SIM_SCGC2 *(volatile uint32_t *)0x4004802C // System Clock Gating Control Register 2 +#define SIM_SCGC2_DAC0 (uint32_t)0x00001000 // DAC0 Clock Gate Control +#define SIM_SCGC3 *(volatile uint32_t *)0x40048030 // System Clock Gating Control Register 3 +#define SIM_SCGC3_ADC1 (uint32_t)0x08000000 // ADC1 Clock Gate Control +#define SIM_SCGC3_FTM2 (uint32_t)0x01000000 // FTM2 Clock Gate Control +#define SIM_SCGC4 *(volatile uint32_t *)0x40048034 // System Clock Gating Control Register 4 +#define SIM_SCGC4_VREF (uint32_t)0x00100000 // VREF Clock Gate Control +#define SIM_SCGC4_CMP (uint32_t)0x00080000 // Comparator Clock Gate Control +#define SIM_SCGC4_USBOTG (uint32_t)0x00040000 // USB Clock Gate Control +#define SIM_SCGC4_UART2 (uint32_t)0x00001000 // UART2 Clock Gate Control +#define SIM_SCGC4_UART1 (uint32_t)0x00000800 // UART1 Clock Gate Control +#define SIM_SCGC4_UART0 (uint32_t)0x00000400 // UART0 Clock Gate Control +#define SIM_SCGC4_I2C1 (uint32_t)0x00000080 // I2C1 Clock Gate Control +#define SIM_SCGC4_I2C0 (uint32_t)0x00000040 // I2C0 Clock Gate Control +#define SIM_SCGC4_CMT (uint32_t)0x00000004 // CMT Clock Gate Control +#define SIM_SCGC4_EWM (uint32_t)0x00000002 // EWM Clock Gate Control #define SIM_SCGC5 *(volatile uint32_t *)0x40048038 // System Clock Gating Control Register 5 -#define SIM_SCGC5_PORTE (uint32_t)0x00002000 // Port E Clock Gate Control -#define SIM_SCGC5_PORTD (uint32_t)0x00001000 // Port D Clock Gate Control -#define SIM_SCGC5_PORTC (uint32_t)0x00000800 // Port C Clock Gate Control -#define SIM_SCGC5_PORTB (uint32_t)0x00000400 // Port B Clock Gate Control -#define SIM_SCGC5_PORTA (uint32_t)0x00000200 // Port A Clock Gate Control -#define SIM_SCGC5_TSI (uint32_t)0x00000020 // Touch Sense Input TSI Clock Gate Control -#define SIM_SCGC5_LPTIMER (uint32_t)0x00000001 // Low Power Timer Access Control +#define SIM_SCGC5_PORTE (uint32_t)0x00002000 // Port E Clock Gate Control +#define SIM_SCGC5_PORTD (uint32_t)0x00001000 // Port D Clock Gate Control +#define SIM_SCGC5_PORTC (uint32_t)0x00000800 // Port C Clock Gate Control +#define SIM_SCGC5_PORTB (uint32_t)0x00000400 // Port B Clock Gate Control +#define SIM_SCGC5_PORTA (uint32_t)0x00000200 // Port A Clock Gate Control +#define SIM_SCGC5_TSI (uint32_t)0x00000020 // Touch Sense Input TSI Clock Gate Control +#define SIM_SCGC5_LPTIMER (uint32_t)0x00000001 // Low Power Timer Access Control #define SIM_SCGC6 *(volatile uint32_t *)0x4004803C // System Clock Gating Control Register 6 -#define SIM_SCGC6_RTC (uint32_t)0x20000000 // RTC Access -#define SIM_SCGC6_ADC0 (uint32_t)0x08000000 // ADC0 Clock Gate Control -#define SIM_SCGC6_FTM1 (uint32_t)0x02000000 // FTM1 Clock Gate Control -#define SIM_SCGC6_FTM0 (uint32_t)0x01000000 // FTM0 Clock Gate Control -#define SIM_SCGC6_PIT (uint32_t)0x00800000 // PIT Clock Gate Control -#define SIM_SCGC6_PDB (uint32_t)0x00400000 // PDB Clock Gate Control -#define SIM_SCGC6_USBDCD (uint32_t)0x00200000 // USB DCD Clock Gate Control -#define SIM_SCGC6_CRC (uint32_t)0x00040000 // CRC Clock Gate Control -#define SIM_SCGC6_I2S (uint32_t)0x00008000 // I2S Clock Gate Control -#define SIM_SCGC6_SPI1 (uint32_t)0x00002000 // SPI1 Clock Gate Control -#define SIM_SCGC6_SPI0 (uint32_t)0x00001000 // SPI0 Clock Gate Control -#define SIM_SCGC6_FLEXCAN0 (uint32_t)0x00000010 // FlexCAN0 Clock Gate Control -#define SIM_SCGC6_DMAMUX (uint32_t)0x00000002 // DMA Mux Clock Gate Control -#define SIM_SCGC6_FTFL (uint32_t)0x00000001 // Flash Memory Clock Gate Control -#define SIM_SCGC7 *(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7 -#define SIM_SCGC7_DMA (uint32_t)0x00000002 // DMA Clock Gate Control -#define SIM_CLKDIV1 *(volatile uint32_t *)0x40048044 // System Clock Divider Register 1 -#define SIM_CLKDIV1_OUTDIV1(n) (uint32_t)(((n) & 0x0F) << 28) // divide value for the core/system clock -#define SIM_CLKDIV1_OUTDIV2(n) (uint32_t)(((n) & 0x0F) << 24) // divide value for the peripheral clock -#define SIM_CLKDIV1_OUTDIV4(n) (uint32_t)(((n) & 0x0F) << 16) // divide value for the flash clock +#define SIM_SCGC6_RTC (uint32_t)0x20000000 // RTC Access +#define SIM_SCGC6_ADC0 (uint32_t)0x08000000 // ADC0 Clock Gate Control +#define SIM_SCGC6_FTM1 (uint32_t)0x02000000 // FTM1 Clock Gate Control +#define SIM_SCGC6_FTM0 (uint32_t)0x01000000 // FTM0 Clock Gate Control +#define SIM_SCGC6_PIT (uint32_t)0x00800000 // PIT Clock Gate Control +#define SIM_SCGC6_PDB (uint32_t)0x00400000 // PDB Clock Gate Control +#define SIM_SCGC6_USBDCD (uint32_t)0x00200000 // USB DCD Clock Gate Control +#define SIM_SCGC6_CRC (uint32_t)0x00040000 // CRC Clock Gate Control +#define SIM_SCGC6_I2S (uint32_t)0x00008000 // I2S Clock Gate Control +#define SIM_SCGC6_SPI1 (uint32_t)0x00002000 // SPI1 Clock Gate Control +#define SIM_SCGC6_SPI0 (uint32_t)0x00001000 // SPI0 Clock Gate Control +#define SIM_SCGC6_FLEXCAN0 (uint32_t)0x00000010 // FlexCAN0 Clock Gate Control +#define SIM_SCGC6_DMAMUX (uint32_t)0x00000002 // DMA Mux Clock Gate Control +#define SIM_SCGC6_FTFL (uint32_t)0x00000001 // Flash Memory Clock Gate Control +#define SIM_SCGC7 *(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7 +#define SIM_SCGC7_DMA (uint32_t)0x00000002 // DMA Clock Gate Control +#define SIM_CLKDIV1 *(volatile uint32_t *)0x40048044 // System Clock Divider Register 1 +#define SIM_CLKDIV1_OUTDIV1(n) (uint32_t)(((n) & 0x0F) << 28) // divide value for the core/system clock +#define SIM_CLKDIV1_OUTDIV2(n) (uint32_t)(((n) & 0x0F) << 24) // divide value for the peripheral clock +#define SIM_CLKDIV1_OUTDIV4(n) (uint32_t)(((n) & 0x0F) << 16) // divide value for the flash clock #define SIM_CLKDIV2 *(volatile uint32_t *)0x40048048 // System Clock Divider Register 2 -#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) -#define SIM_CLKDIV2_USBFRAC (uint32_t)0x01 +#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) +#define SIM_CLKDIV2_USBFRAC (uint32_t)0x01 #define SIM_FCFG1 *(const uint32_t *)0x4004804C // Flash Configuration Register 1 #define SIM_FCFG2 *(const uint32_t *)0x40048050 // Flash Configuration Register 2 #define SIM_UIDH *(const uint32_t *)0x40048054 // Unique Identification Register High @@ -326,44 +326,44 @@ #define RCM_MR *(volatile uint8_t *)0x4007F007 // Mode Register // Chapter 14: System Mode Controller -#define SMC_PMPROT *(volatile uint8_t *)0x4007E000 // Power Mode Protection Register -#define SMC_PMPROT_AVLP (uint8_t)0x20 // Allow very low power modes -#define SMC_PMPROT_ALLS (uint8_t)0x08 // Allow low leakage stop mode -#define SMC_PMPROT_AVLLS (uint8_t)0x02 // Allow very low leakage stop mode -#define SMC_PMCTRL *(volatile uint8_t *)0x4007E001 // Power Mode Control Register -#define SMC_PMCTRL_LPWUI (uint8_t)0x80 // Low Power Wake Up on Interrupt -#define SMC_PMCTRL_RUNM(n) (uint8_t)(((n) & 0x03) << 5) // Run Mode Control -#define SMC_PMCTRL_STOPA (uint8_t)0x08 // Stop Aborted -#define SMC_PMCTRL_STOPM(n) (uint8_t)((n) & 0x07) // Stop Mode Control -#define SMC_VLLSCTRL *(volatile uint8_t *)0x4007E002 // VLLS Control Register -#define SMC_VLLSCTRL_PORPO (uint8_t)0x20 // POR Power Option -#define SMC_VLLSCTRL_VLLSM(n) (uint8_t)((n) & 0x07) // VLLS Mode Control -#define SMC_PMSTAT *(volatile uint8_t *)0x4007E003 // Power Mode Status Register -#define SMC_PMSTAT_RUN (uint8_t)0x01 // Current power mode is RUN -#define SMC_PMSTAT_STOP (uint8_t)0x02 // Current power mode is STOP -#define SMC_PMSTAT_VLPR (uint8_t)0x04 // Current power mode is VLPR -#define SMC_PMSTAT_VLPW (uint8_t)0x08 // Current power mode is VLPW -#define SMC_PMSTAT_VLPS (uint8_t)0x10 // Current power mode is VLPS -#define SMC_PMSTAT_LLS (uint8_t)0x20 // Current power mode is LLS -#define SMC_PMSTAT_VLLS (uint8_t)0x40 // Current power mode is VLLS +#define SMC_PMPROT *(volatile uint8_t *)0x4007E000 // Power Mode Protection Register +#define SMC_PMPROT_AVLP (uint8_t)0x20 // Allow very low power modes +#define SMC_PMPROT_ALLS (uint8_t)0x08 // Allow low leakage stop mode +#define SMC_PMPROT_AVLLS (uint8_t)0x02 // Allow very low leakage stop mode +#define SMC_PMCTRL *(volatile uint8_t *)0x4007E001 // Power Mode Control Register +#define SMC_PMCTRL_LPWUI (uint8_t)0x80 // Low Power Wake Up on Interrupt +#define SMC_PMCTRL_RUNM(n) (uint8_t)(((n) & 0x03) << 5) // Run Mode Control +#define SMC_PMCTRL_STOPA (uint8_t)0x08 // Stop Aborted +#define SMC_PMCTRL_STOPM(n) (uint8_t)((n) & 0x07) // Stop Mode Control +#define SMC_VLLSCTRL *(volatile uint8_t *)0x4007E002 // VLLS Control Register +#define SMC_VLLSCTRL_PORPO (uint8_t)0x20 // POR Power Option +#define SMC_VLLSCTRL_VLLSM(n) (uint8_t)((n) & 0x07) // VLLS Mode Control +#define SMC_PMSTAT *(volatile uint8_t *)0x4007E003 // Power Mode Status Register +#define SMC_PMSTAT_RUN (uint8_t)0x01 // Current power mode is RUN +#define SMC_PMSTAT_STOP (uint8_t)0x02 // Current power mode is STOP +#define SMC_PMSTAT_VLPR (uint8_t)0x04 // Current power mode is VLPR +#define SMC_PMSTAT_VLPW (uint8_t)0x08 // Current power mode is VLPW +#define SMC_PMSTAT_VLPS (uint8_t)0x10 // Current power mode is VLPS +#define SMC_PMSTAT_LLS (uint8_t)0x20 // Current power mode is LLS +#define SMC_PMSTAT_VLLS (uint8_t)0x40 // Current power mode is VLLS // Chapter 15: Power Management Controller -#define PMC_LVDSC1 *(volatile uint8_t *)0x4007D000 // Low Voltage Detect Status And Control 1 register -#define PMC_LVDSC1_LVDF (uint8_t)0x80 // Low-Voltage Detect Flag -#define PMC_LVDSC1_LVDACK (uint8_t)0x40 // Low-Voltage Detect Acknowledge -#define PMC_LVDSC1_LVDIE (uint8_t)0x20 // Low-Voltage Detect Interrupt Enable -#define PMC_LVDSC1_LVDRE (uint8_t)0x10 // Low-Voltage Detect Reset Enable -#define PMC_LVDSC1_LVDV(n) (uint8_t)((n) & 0x03) // Low-Voltage Detect Voltage Select -#define PMC_LVDSC2 *(volatile uint8_t *)0x4007D001 // Low Voltage Detect Status And Control 2 register -#define PMC_LVDSC2_LVWF (uint8_t)0x80 // Low-Voltage Warning Flag -#define PMC_LVDSC2_LVWACK (uint8_t)0x40 // Low-Voltage Warning Acknowledge -#define PMC_LVDSC2_LVWIE (uint8_t)0x20 // Low-Voltage Warning Interrupt Enable -#define PMC_LVDSC2_LVWV(n) (uint8_t)((n) & 0x03) // Low-Voltage Warning Voltage Select -#define PMC_REGSC *(volatile uint8_t *)0x4007D002 // Regulator Status And Control register -#define PMC_REGSC_BGEN (uint8_t)0x10 // Bandgap Enable In VLPx Operation -#define PMC_REGSC_ACKISO (uint8_t)0x08 // Acknowledge Isolation -#define PMC_REGSC_REGONS (uint8_t)0x04 // Regulator In Run Regulation Status -#define PMC_REGSC_BGBE (uint8_t)0x01 // Bandgap Buffer Enable +#define PMC_LVDSC1 *(volatile uint8_t *)0x4007D000 // Low Voltage Detect Status And Control 1 register +#define PMC_LVDSC1_LVDF (uint8_t)0x80 // Low-Voltage Detect Flag +#define PMC_LVDSC1_LVDACK (uint8_t)0x40 // Low-Voltage Detect Acknowledge +#define PMC_LVDSC1_LVDIE (uint8_t)0x20 // Low-Voltage Detect Interrupt Enable +#define PMC_LVDSC1_LVDRE (uint8_t)0x10 // Low-Voltage Detect Reset Enable +#define PMC_LVDSC1_LVDV(n) (uint8_t)((n) & 0x03) // Low-Voltage Detect Voltage Select +#define PMC_LVDSC2 *(volatile uint8_t *)0x4007D001 // Low Voltage Detect Status And Control 2 register +#define PMC_LVDSC2_LVWF (uint8_t)0x80 // Low-Voltage Warning Flag +#define PMC_LVDSC2_LVWACK (uint8_t)0x40 // Low-Voltage Warning Acknowledge +#define PMC_LVDSC2_LVWIE (uint8_t)0x20 // Low-Voltage Warning Interrupt Enable +#define PMC_LVDSC2_LVWV(n) (uint8_t)((n) & 0x03) // Low-Voltage Warning Voltage Select +#define PMC_REGSC *(volatile uint8_t *)0x4007D002 // Regulator Status And Control register +#define PMC_REGSC_BGEN (uint8_t)0x10 // Bandgap Enable In VLPx Operation +#define PMC_REGSC_ACKISO (uint8_t)0x08 // Acknowledge Isolation +#define PMC_REGSC_REGONS (uint8_t)0x04 // Regulator In Run Regulation Status +#define PMC_REGSC_BGBE (uint8_t)0x01 // Bandgap Buffer Enable // Chapter 16: Low-Leakage Wakeup Unit (LLWU) #define LLWU_PE1 *(volatile uint8_t *)0x4007C000 // LLWU Pin Enable 1 register @@ -379,289 +379,289 @@ #define LLWU_RST *(volatile uint8_t *)0x4007C00A // LLWU Reset Enable register // Chapter 17: Miscellaneous Control Module (MCM) -#define MCM_PLASC *(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration -#define MCM_PLAMC *(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration -#define MCM_PLACR *(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register (MK20DX128) -#define MCM_PLACR_ARG (uint32_t)0x00000200 // Arbitration select, 0=fixed, 1=round-robin -#define MCM_CR *(volatile uint32_t *)0xE008000C // RAM arbitration control register (MK20DX256) -#define MCM_CR_SRAMLWP (uint32_t)0x40000000 // SRAM_L write protect -#define MCM_CR_SRAMLAP(n) (uint32_t)(((n) & 0x03) << 28) // SRAM_L priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA -#define MCM_CR_SRAMUWP (uint32_t)0x04000000 // SRAM_U write protect -#define MCM_CR_SRAMUAP(n) (uint32_t)(((n) & 0x03) << 24) // SRAM_U priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA +#define MCM_PLASC *(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration +#define MCM_PLAMC *(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration +#define MCM_PLACR *(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register (MK20DX128) +#define MCM_PLACR_ARG (uint32_t)0x00000200 // Arbitration select, 0=fixed, 1=round-robin +#define MCM_CR *(volatile uint32_t *)0xE008000C // RAM arbitration control register (MK20DX256) +#define MCM_CR_SRAMLWP (uint32_t)0x40000000 // SRAM_L write protect +#define MCM_CR_SRAMLAP(n) (uint32_t)(((n) & 0x03) << 28) // SRAM_L priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA +#define MCM_CR_SRAMUWP (uint32_t)0x04000000 // SRAM_U write protect +#define MCM_CR_SRAMUAP(n) (uint32_t)(((n) & 0x03) << 24) // SRAM_U priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA // Crossbar Switch (AXBS) - only programmable on MK20DX256 -#define AXBS_PRS0 *(volatile uint32_t *)0x40004000 // Priority Registers Slave 0 -#define AXBS_CRS0 *(volatile uint32_t *)0x40004010 // Control Register 0 -#define AXBS_PRS1 *(volatile uint32_t *)0x40004100 // Priority Registers Slave 1 -#define AXBS_CRS1 *(volatile uint32_t *)0x40004110 // Control Register 1 -#define AXBS_PRS2 *(volatile uint32_t *)0x40004200 // Priority Registers Slave 2 -#define AXBS_CRS2 *(volatile uint32_t *)0x40004210 // Control Register 2 -#define AXBS_PRS3 *(volatile uint32_t *)0x40004300 // Priority Registers Slave 3 -#define AXBS_CRS3 *(volatile uint32_t *)0x40004310 // Control Register 3 -#define AXBS_PRS4 *(volatile uint32_t *)0x40004400 // Priority Registers Slave 4 -#define AXBS_CRS4 *(volatile uint32_t *)0x40004410 // Control Register 4 -#define AXBS_PRS5 *(volatile uint32_t *)0x40004500 // Priority Registers Slave 5 -#define AXBS_CRS5 *(volatile uint32_t *)0x40004510 // Control Register 5 -#define AXBS_PRS6 *(volatile uint32_t *)0x40004600 // Priority Registers Slave 6 -#define AXBS_CRS6 *(volatile uint32_t *)0x40004610 // Control Register 6 -#define AXBS_PRS7 *(volatile uint32_t *)0x40004700 // Priority Registers Slave 7 -#define AXBS_CRS7 *(volatile uint32_t *)0x40004710 // Control Register 7 -#define AXBS_MGPCR0 *(volatile uint32_t *)0x40004800 // Master 0 General Purpose Control Register -#define AXBS_MGPCR1 *(volatile uint32_t *)0x40004900 // Master 1 General Purpose Control Register -#define AXBS_MGPCR2 *(volatile uint32_t *)0x40004A00 // Master 2 General Purpose Control Register -#define AXBS_MGPCR3 *(volatile uint32_t *)0x40004B00 // Master 3 General Purpose Control Register -#define AXBS_MGPCR4 *(volatile uint32_t *)0x40004C00 // Master 4 General Purpose Control Register -#define AXBS_MGPCR5 *(volatile uint32_t *)0x40004D00 // Master 5 General Purpose Control Register -#define AXBS_MGPCR6 *(volatile uint32_t *)0x40004E00 // Master 6 General Purpose Control Register -#define AXBS_MGPCR7 *(volatile uint32_t *)0x40004F00 // Master 7 General Purpose Control Register -#define AXBS_CRS_READONLY (uint32_t)0x80000000 -#define AXBS_CRS_HALTLOWPRIORITY (uint32_t)0x40000000 -#define AXBS_CRS_ARB_FIXED (uint32_t)0x00000000 -#define AXBS_CRS_ARB_ROUNDROBIN (uint32_t)0x00010000 -#define AXBS_CRS_PARK_FIXED (uint32_t)0x00000000 -#define AXBS_CRS_PARK_PREVIOUS (uint32_t)0x00000010 -#define AXBS_CRS_PARK_NONE (uint32_t)0x00000020 -#define AXBS_CRS_PARK(n) (uint32_t)(((n) & 7) << 0) +#define AXBS_PRS0 *(volatile uint32_t *)0x40004000 // Priority Registers Slave 0 +#define AXBS_CRS0 *(volatile uint32_t *)0x40004010 // Control Register 0 +#define AXBS_PRS1 *(volatile uint32_t *)0x40004100 // Priority Registers Slave 1 +#define AXBS_CRS1 *(volatile uint32_t *)0x40004110 // Control Register 1 +#define AXBS_PRS2 *(volatile uint32_t *)0x40004200 // Priority Registers Slave 2 +#define AXBS_CRS2 *(volatile uint32_t *)0x40004210 // Control Register 2 +#define AXBS_PRS3 *(volatile uint32_t *)0x40004300 // Priority Registers Slave 3 +#define AXBS_CRS3 *(volatile uint32_t *)0x40004310 // Control Register 3 +#define AXBS_PRS4 *(volatile uint32_t *)0x40004400 // Priority Registers Slave 4 +#define AXBS_CRS4 *(volatile uint32_t *)0x40004410 // Control Register 4 +#define AXBS_PRS5 *(volatile uint32_t *)0x40004500 // Priority Registers Slave 5 +#define AXBS_CRS5 *(volatile uint32_t *)0x40004510 // Control Register 5 +#define AXBS_PRS6 *(volatile uint32_t *)0x40004600 // Priority Registers Slave 6 +#define AXBS_CRS6 *(volatile uint32_t *)0x40004610 // Control Register 6 +#define AXBS_PRS7 *(volatile uint32_t *)0x40004700 // Priority Registers Slave 7 +#define AXBS_CRS7 *(volatile uint32_t *)0x40004710 // Control Register 7 +#define AXBS_MGPCR0 *(volatile uint32_t *)0x40004800 // Master 0 General Purpose Control Register +#define AXBS_MGPCR1 *(volatile uint32_t *)0x40004900 // Master 1 General Purpose Control Register +#define AXBS_MGPCR2 *(volatile uint32_t *)0x40004A00 // Master 2 General Purpose Control Register +#define AXBS_MGPCR3 *(volatile uint32_t *)0x40004B00 // Master 3 General Purpose Control Register +#define AXBS_MGPCR4 *(volatile uint32_t *)0x40004C00 // Master 4 General Purpose Control Register +#define AXBS_MGPCR5 *(volatile uint32_t *)0x40004D00 // Master 5 General Purpose Control Register +#define AXBS_MGPCR6 *(volatile uint32_t *)0x40004E00 // Master 6 General Purpose Control Register +#define AXBS_MGPCR7 *(volatile uint32_t *)0x40004F00 // Master 7 General Purpose Control Register +#define AXBS_CRS_READONLY (uint32_t)0x80000000 +#define AXBS_CRS_HALTLOWPRIORITY (uint32_t)0x40000000 +#define AXBS_CRS_ARB_FIXED (uint32_t)0x00000000 +#define AXBS_CRS_ARB_ROUNDROBIN (uint32_t)0x00010000 +#define AXBS_CRS_PARK_FIXED (uint32_t)0x00000000 +#define AXBS_CRS_PARK_PREVIOUS (uint32_t)0x00000010 +#define AXBS_CRS_PARK_NONE (uint32_t)0x00000020 +#define AXBS_CRS_PARK(n) (uint32_t)(((n) & 7) << 0) // Chapter 20: Direct Memory Access Multiplexer (DMAMUX) -#define DMAMUX0_CHCFG0 *(volatile uint8_t *)0x40021000 // Channel Configuration register -#define DMAMUX0_CHCFG1 *(volatile uint8_t *)0x40021001 // Channel Configuration register -#define DMAMUX0_CHCFG2 *(volatile uint8_t *)0x40021002 // Channel Configuration register -#define DMAMUX0_CHCFG3 *(volatile uint8_t *)0x40021003 // Channel Configuration register -#define DMAMUX0_CHCFG4 *(volatile uint8_t *)0x40021004 // Channel Configuration register -#define DMAMUX0_CHCFG5 *(volatile uint8_t *)0x40021005 // Channel Configuration register -#define DMAMUX0_CHCFG6 *(volatile uint8_t *)0x40021006 // Channel Configuration register -#define DMAMUX0_CHCFG7 *(volatile uint8_t *)0x40021007 // Channel Configuration register -#define DMAMUX0_CHCFG8 *(volatile uint8_t *)0x40021008 // Channel Configuration register -#define DMAMUX0_CHCFG9 *(volatile uint8_t *)0x40021009 // Channel Configuration register -#define DMAMUX0_CHCFG10 *(volatile uint8_t *)0x4002100A // Channel Configuration register -#define DMAMUX0_CHCFG11 *(volatile uint8_t *)0x4002100B // Channel Configuration register -#define DMAMUX0_CHCFG12 *(volatile uint8_t *)0x4002100C // Channel Configuration register -#define DMAMUX0_CHCFG13 *(volatile uint8_t *)0x4002100D // Channel Configuration register -#define DMAMUX0_CHCFG14 *(volatile uint8_t *)0x4002100E // Channel Configuration register -#define DMAMUX0_CHCFG15 *(volatile uint8_t *)0x4002100F // Channel Configuration register -#define DMAMUX_DISABLE 0 -#define DMAMUX_TRIG 64 -#define DMAMUX_ENABLE 128 -#define DMAMUX_SOURCE_UART0_RX 2 -#define DMAMUX_SOURCE_UART0_TX 3 -#define DMAMUX_SOURCE_UART1_RX 4 -#define DMAMUX_SOURCE_UART1_TX 5 -#define DMAMUX_SOURCE_UART2_RX 6 -#define DMAMUX_SOURCE_UART2_TX 7 -#define DMAMUX_SOURCE_I2S0_RX 14 -#define DMAMUX_SOURCE_I2S0_TX 15 -#define DMAMUX_SOURCE_SPI0_RX 16 -#define DMAMUX_SOURCE_SPI0_TX 17 -#define DMAMUX_SOURCE_I2C0 22 -#define DMAMUX_SOURCE_I2C1 23 -#define DMAMUX_SOURCE_FTM0_CH0 24 -#define DMAMUX_SOURCE_FTM0_CH1 25 -#define DMAMUX_SOURCE_FTM0_CH2 26 -#define DMAMUX_SOURCE_FTM0_CH3 27 -#define DMAMUX_SOURCE_FTM0_CH4 28 -#define DMAMUX_SOURCE_FTM0_CH5 29 -#define DMAMUX_SOURCE_FTM0_CH6 30 -#define DMAMUX_SOURCE_FTM0_CH7 31 -#define DMAMUX_SOURCE_FTM1_CH0 32 -#define DMAMUX_SOURCE_FTM1_CH1 33 -#define DMAMUX_SOURCE_FTM2_CH0 34 -#define DMAMUX_SOURCE_FTM2_CH1 35 -#define DMAMUX_SOURCE_ADC0 40 -#define DMAMUX_SOURCE_ADC1 41 -#define DMAMUX_SOURCE_CMP0 42 -#define DMAMUX_SOURCE_CMP1 43 -#define DMAMUX_SOURCE_CMP2 44 -#define DMAMUX_SOURCE_DAC0 45 -#define DMAMUX_SOURCE_CMT 47 -#define DMAMUX_SOURCE_PDB 48 -#define DMAMUX_SOURCE_PORTA 49 -#define DMAMUX_SOURCE_PORTB 50 -#define DMAMUX_SOURCE_PORTC 51 -#define DMAMUX_SOURCE_PORTD 52 -#define DMAMUX_SOURCE_PORTE 53 -#define DMAMUX_SOURCE_ALWAYS0 54 -#define DMAMUX_SOURCE_ALWAYS1 55 -#define DMAMUX_SOURCE_ALWAYS2 56 -#define DMAMUX_SOURCE_ALWAYS3 57 -#define DMAMUX_SOURCE_ALWAYS4 58 -#define DMAMUX_SOURCE_ALWAYS5 59 -#define DMAMUX_SOURCE_ALWAYS6 60 -#define DMAMUX_SOURCE_ALWAYS7 61 -#define DMAMUX_SOURCE_ALWAYS8 62 -#define DMAMUX_SOURCE_ALWAYS9 63 +#define DMAMUX0_CHCFG0 *(volatile uint8_t *)0x40021000 // Channel Configuration register +#define DMAMUX0_CHCFG1 *(volatile uint8_t *)0x40021001 // Channel Configuration register +#define DMAMUX0_CHCFG2 *(volatile uint8_t *)0x40021002 // Channel Configuration register +#define DMAMUX0_CHCFG3 *(volatile uint8_t *)0x40021003 // Channel Configuration register +#define DMAMUX0_CHCFG4 *(volatile uint8_t *)0x40021004 // Channel Configuration register +#define DMAMUX0_CHCFG5 *(volatile uint8_t *)0x40021005 // Channel Configuration register +#define DMAMUX0_CHCFG6 *(volatile uint8_t *)0x40021006 // Channel Configuration register +#define DMAMUX0_CHCFG7 *(volatile uint8_t *)0x40021007 // Channel Configuration register +#define DMAMUX0_CHCFG8 *(volatile uint8_t *)0x40021008 // Channel Configuration register +#define DMAMUX0_CHCFG9 *(volatile uint8_t *)0x40021009 // Channel Configuration register +#define DMAMUX0_CHCFG10 *(volatile uint8_t *)0x4002100A // Channel Configuration register +#define DMAMUX0_CHCFG11 *(volatile uint8_t *)0x4002100B // Channel Configuration register +#define DMAMUX0_CHCFG12 *(volatile uint8_t *)0x4002100C // Channel Configuration register +#define DMAMUX0_CHCFG13 *(volatile uint8_t *)0x4002100D // Channel Configuration register +#define DMAMUX0_CHCFG14 *(volatile uint8_t *)0x4002100E // Channel Configuration register +#define DMAMUX0_CHCFG15 *(volatile uint8_t *)0x4002100F // Channel Configuration register +#define DMAMUX_DISABLE 0 +#define DMAMUX_TRIG 64 +#define DMAMUX_ENABLE 128 +#define DMAMUX_SOURCE_UART0_RX 2 +#define DMAMUX_SOURCE_UART0_TX 3 +#define DMAMUX_SOURCE_UART1_RX 4 +#define DMAMUX_SOURCE_UART1_TX 5 +#define DMAMUX_SOURCE_UART2_RX 6 +#define DMAMUX_SOURCE_UART2_TX 7 +#define DMAMUX_SOURCE_I2S0_RX 14 +#define DMAMUX_SOURCE_I2S0_TX 15 +#define DMAMUX_SOURCE_SPI0_RX 16 +#define DMAMUX_SOURCE_SPI0_TX 17 +#define DMAMUX_SOURCE_I2C0 22 +#define DMAMUX_SOURCE_I2C1 23 +#define DMAMUX_SOURCE_FTM0_CH0 24 +#define DMAMUX_SOURCE_FTM0_CH1 25 +#define DMAMUX_SOURCE_FTM0_CH2 26 +#define DMAMUX_SOURCE_FTM0_CH3 27 +#define DMAMUX_SOURCE_FTM0_CH4 28 +#define DMAMUX_SOURCE_FTM0_CH5 29 +#define DMAMUX_SOURCE_FTM0_CH6 30 +#define DMAMUX_SOURCE_FTM0_CH7 31 +#define DMAMUX_SOURCE_FTM1_CH0 32 +#define DMAMUX_SOURCE_FTM1_CH1 33 +#define DMAMUX_SOURCE_FTM2_CH0 34 +#define DMAMUX_SOURCE_FTM2_CH1 35 +#define DMAMUX_SOURCE_ADC0 40 +#define DMAMUX_SOURCE_ADC1 41 +#define DMAMUX_SOURCE_CMP0 42 +#define DMAMUX_SOURCE_CMP1 43 +#define DMAMUX_SOURCE_CMP2 44 +#define DMAMUX_SOURCE_DAC0 45 +#define DMAMUX_SOURCE_CMT 47 +#define DMAMUX_SOURCE_PDB 48 +#define DMAMUX_SOURCE_PORTA 49 +#define DMAMUX_SOURCE_PORTB 50 +#define DMAMUX_SOURCE_PORTC 51 +#define DMAMUX_SOURCE_PORTD 52 +#define DMAMUX_SOURCE_PORTE 53 +#define DMAMUX_SOURCE_ALWAYS0 54 +#define DMAMUX_SOURCE_ALWAYS1 55 +#define DMAMUX_SOURCE_ALWAYS2 56 +#define DMAMUX_SOURCE_ALWAYS3 57 +#define DMAMUX_SOURCE_ALWAYS4 58 +#define DMAMUX_SOURCE_ALWAYS5 59 +#define DMAMUX_SOURCE_ALWAYS6 60 +#define DMAMUX_SOURCE_ALWAYS7 61 +#define DMAMUX_SOURCE_ALWAYS8 62 +#define DMAMUX_SOURCE_ALWAYS9 63 // Chapter 21: Direct Memory Access Controller (eDMA) -#define DMA_CR *(volatile uint32_t *)0x40008000 // Control Register -#define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer -#define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer -#define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping -#define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode -#define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations -#define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error -#define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration -#define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug -#define DMA_ES *(volatile uint32_t *)0x40008004 // Error Status Register -#define DMA_ERQ *(volatile uint32_t *)0x4000800C // Enable Request Register -#define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0 -#define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1 -#define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2 -#define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3 -#define DMA_EEI *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register -#define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0 -#define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1 -#define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2 -#define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3 -#define DMA_CEEI *(volatile uint8_t *)0x40008018 // Clear Enable Error Interrupt Register -#define DMA_CEEI_CEEI(n) ((uint8_t)(n & 3)<<0) // Clear Enable Error Interrupt -#define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts -#define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP -#define DMA_SEEI *(volatile uint8_t *)0x40008019 // Set Enable Error Interrupt Register -#define DMA_SEEI_SEEI(n) ((uint8_t)(n & 3)<<0) // Set Enable Error Interrupt -#define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts -#define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP -#define DMA_CERQ *(volatile uint8_t *)0x4000801A // Clear Enable Request Register -#define DMA_CERQ_CERQ(n) ((uint8_t)(n & 3)<<0) // Clear Enable Request -#define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests -#define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP -#define DMA_SERQ *(volatile uint8_t *)0x4000801B // Set Enable Request Register -#define DMA_SERQ_SERQ(n) ((uint8_t)(n & 3)<<0) // Set Enable Request -#define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests -#define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP -#define DMA_CDNE *(volatile uint8_t *)0x4000801C // Clear DONE Status Bit Register -#define DMA_CDNE_CDNE(n) ((uint8_t)(n & 3)<<0) // Clear Done Bit -#define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits -#define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP -#define DMA_SSRT *(volatile uint8_t *)0x4000801D // Set START Bit Register -#define DMA_SSRT_SSRT(n) ((uint8_t)(n & 3)<<0) // Set Start Bit -#define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits -#define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP -#define DMA_CERR *(volatile uint8_t *)0x4000801E // Clear Error Register -#define DMA_CERR_CERR(n) ((uint8_t)(n & 3)<<0) // Clear Error Indicator -#define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators -#define DMA_CERR_NOP ((uint8_t)1<<7) // NOP -#define DMA_CINT *(volatile uint8_t *)0x4000801F // Clear Interrupt Request Register -#define DMA_CINT_CINT(n) ((uint8_t)(n & 3)<<0) // Clear Interrupt Request -#define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests -#define DMA_CINT_NOP ((uint8_t)1<<7) // NOP -#define DMA_INT *(volatile uint32_t *)0x40008024 // Interrupt Request Register -#define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0 -#define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1 -#define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2 -#define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3 -#define DMA_ERR *(volatile uint32_t *)0x4000802C // Error Register -#define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0 -#define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1 -#define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2 -#define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3 -#define DMA_HRS *(volatile uint32_t *)0x40008034 // Hardware Request Status Register -#define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0 -#define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1 -#define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2 -#define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3 -#define DMA_DCHPRI3 *(volatile uint8_t *)0x40008100 // Channel n Priority Register -#define DMA_DCHPRI2 *(volatile uint8_t *)0x40008101 // Channel n Priority Register -#define DMA_DCHPRI1 *(volatile uint8_t *)0x40008102 // Channel n Priority Register -#define DMA_DCHPRI0 *(volatile uint8_t *)0x40008103 // Channel n Priority Register -#define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 3)<<0) // Channel Arbitration Priority -#define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability -#define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption +#define DMA_CR *(volatile uint32_t *)0x40008000 // Control Register +#define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer +#define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer +#define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping +#define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode +#define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations +#define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error +#define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration +#define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug +#define DMA_ES *(volatile uint32_t *)0x40008004 // Error Status Register +#define DMA_ERQ *(volatile uint32_t *)0x4000800C // Enable Request Register +#define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0 +#define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1 +#define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2 +#define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3 +#define DMA_EEI *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register +#define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0 +#define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1 +#define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2 +#define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3 +#define DMA_CEEI *(volatile uint8_t *)0x40008018 // Clear Enable Error Interrupt Register +#define DMA_CEEI_CEEI(n) ((uint8_t)(n & 3)<<0) // Clear Enable Error Interrupt +#define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts +#define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP +#define DMA_SEEI *(volatile uint8_t *)0x40008019 // Set Enable Error Interrupt Register +#define DMA_SEEI_SEEI(n) ((uint8_t)(n & 3)<<0) // Set Enable Error Interrupt +#define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts +#define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP +#define DMA_CERQ *(volatile uint8_t *)0x4000801A // Clear Enable Request Register +#define DMA_CERQ_CERQ(n) ((uint8_t)(n & 3)<<0) // Clear Enable Request +#define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests +#define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP +#define DMA_SERQ *(volatile uint8_t *)0x4000801B // Set Enable Request Register +#define DMA_SERQ_SERQ(n) ((uint8_t)(n & 3)<<0) // Set Enable Request +#define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests +#define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP +#define DMA_CDNE *(volatile uint8_t *)0x4000801C // Clear DONE Status Bit Register +#define DMA_CDNE_CDNE(n) ((uint8_t)(n & 3)<<0) // Clear Done Bit +#define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits +#define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP +#define DMA_SSRT *(volatile uint8_t *)0x4000801D // Set START Bit Register +#define DMA_SSRT_SSRT(n) ((uint8_t)(n & 3)<<0) // Set Start Bit +#define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits +#define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP +#define DMA_CERR *(volatile uint8_t *)0x4000801E // Clear Error Register +#define DMA_CERR_CERR(n) ((uint8_t)(n & 3)<<0) // Clear Error Indicator +#define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators +#define DMA_CERR_NOP ((uint8_t)1<<7) // NOP +#define DMA_CINT *(volatile uint8_t *)0x4000801F // Clear Interrupt Request Register +#define DMA_CINT_CINT(n) ((uint8_t)(n & 3)<<0) // Clear Interrupt Request +#define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests +#define DMA_CINT_NOP ((uint8_t)1<<7) // NOP +#define DMA_INT *(volatile uint32_t *)0x40008024 // Interrupt Request Register +#define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0 +#define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1 +#define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2 +#define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3 +#define DMA_ERR *(volatile uint32_t *)0x4000802C // Error Register +#define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0 +#define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1 +#define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2 +#define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3 +#define DMA_HRS *(volatile uint32_t *)0x40008034 // Hardware Request Status Register +#define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0 +#define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1 +#define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2 +#define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3 +#define DMA_DCHPRI3 *(volatile uint8_t *)0x40008100 // Channel n Priority Register +#define DMA_DCHPRI2 *(volatile uint8_t *)0x40008101 // Channel n Priority Register +#define DMA_DCHPRI1 *(volatile uint8_t *)0x40008102 // Channel n Priority Register +#define DMA_DCHPRI0 *(volatile uint8_t *)0x40008103 // Channel n Priority Register +#define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 3)<<0) // Channel Arbitration Priority +#define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability +#define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption -#define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11) -#define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8) -#define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3) -#define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0) -#define DMA_TCD_ATTR_SIZE_8BIT 0 -#define DMA_TCD_ATTR_SIZE_16BIT 1 -#define DMA_TCD_ATTR_SIZE_32BIT 2 -#define DMA_TCD_ATTR_SIZE_16BYTE 4 -#define DMA_TCD_ATTR_SIZE_32BYTE 5 -#define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14) -#define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0x3) << 8) -#define DMA_TCD_CSR_DONE 0x0080 -#define DMA_TCD_CSR_ACTIVE 0x0040 -#define DMA_TCD_CSR_MAJORELINK 0x0020 -#define DMA_TCD_CSR_ESG 0x0010 -#define DMA_TCD_CSR_DREQ 0x0008 -#define DMA_TCD_CSR_INTHALF 0x0004 -#define DMA_TCD_CSR_INTMAJOR 0x0002 -#define DMA_TCD_CSR_START 0x0001 -#define DMA_TCD_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask -#define DMA_TCD_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete -#define DMA_TCD_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask -#define DMA_TCD_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete -#define DMA_TCD_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable -#define DMA_TCD_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable -#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)(n)) // NBytes transfer count when minor loop disabled -#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)(n & 0x1F)) // NBytes transfer count when minor loop enabled -#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset +#define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11) +#define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8) +#define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3) +#define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0) +#define DMA_TCD_ATTR_SIZE_8BIT 0 +#define DMA_TCD_ATTR_SIZE_16BIT 1 +#define DMA_TCD_ATTR_SIZE_32BIT 2 +#define DMA_TCD_ATTR_SIZE_16BYTE 4 +#define DMA_TCD_ATTR_SIZE_32BYTE 5 +#define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14) +#define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0x3) << 8) +#define DMA_TCD_CSR_DONE 0x0080 +#define DMA_TCD_CSR_ACTIVE 0x0040 +#define DMA_TCD_CSR_MAJORELINK 0x0020 +#define DMA_TCD_CSR_ESG 0x0010 +#define DMA_TCD_CSR_DREQ 0x0008 +#define DMA_TCD_CSR_INTHALF 0x0004 +#define DMA_TCD_CSR_INTMAJOR 0x0002 +#define DMA_TCD_CSR_START 0x0001 +#define DMA_TCD_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask +#define DMA_TCD_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete +#define DMA_TCD_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask +#define DMA_TCD_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete +#define DMA_TCD_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable +#define DMA_TCD_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)(n)) // NBytes transfer count when minor loop disabled +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)(n & 0x1F)) // NBytes transfer count when minor loop enabled +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset -#define DMA_TCD0_SADDR *(volatile const void * volatile *)0x40009000 // TCD Source Address -#define DMA_TCD0_SOFF *(volatile int16_t *)0x40009004 // TCD Signed Source Address Offset -#define DMA_TCD0_ATTR *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes -#define DMA_TCD0_NBYTES_MLNO *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled) +#define DMA_TCD0_SADDR *(volatile const void * volatile *)0x40009000 // TCD Source Address +#define DMA_TCD0_SOFF *(volatile int16_t *)0x40009004 // TCD Signed Source Address Offset +#define DMA_TCD0_ATTR *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes +#define DMA_TCD0_NBYTES_MLNO *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled) #define DMA_TCD0_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) #define DMA_TCD0_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) -#define DMA_TCD0_SLAST *(volatile int32_t *)0x4000900C // TCD Last Source Address Adjustment -#define DMA_TCD0_DADDR *(volatile void * volatile *)0x40009010 // TCD Destination Address -#define DMA_TCD0_DOFF *(volatile int16_t *)0x40009014 // TCD Signed Destination Address Offset +#define DMA_TCD0_SLAST *(volatile int32_t *)0x4000900C // TCD Last Source Address Adjustment +#define DMA_TCD0_DADDR *(volatile void * volatile *)0x40009010 // TCD Destination Address +#define DMA_TCD0_DOFF *(volatile int16_t *)0x40009014 // TCD Signed Destination Address Offset #define DMA_TCD0_CITER_ELINKYES *(volatile uint16_t *)0x40009016 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled -#define DMA_TCD0_CITER_ELINKNO *(volatile uint16_t *)0x40009016 // ?? -#define DMA_TCD0_DLASTSGA *(volatile int32_t *)0x40009018 // TCD Last Destination Address Adjustment/Scatter Gather Address -#define DMA_TCD0_CSR *(volatile uint16_t *)0x4000901C // TCD Control and Status +#define DMA_TCD0_CITER_ELINKNO *(volatile uint16_t *)0x40009016 // ?? +#define DMA_TCD0_DLASTSGA *(volatile int32_t *)0x40009018 // TCD Last Destination Address Adjustment/Scatter Gather Address +#define DMA_TCD0_CSR *(volatile uint16_t *)0x4000901C // TCD Control and Status #define DMA_TCD0_BITER_ELINKYES *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled -#define DMA_TCD0_BITER_ELINKNO *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled +#define DMA_TCD0_BITER_ELINKNO *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled -#define DMA_TCD1_SADDR *(volatile const void * volatile *)0x40009020 // TCD Source Address -#define DMA_TCD1_SOFF *(volatile int16_t *)0x40009024 // TCD Signed Source Address Offset -#define DMA_TCD1_ATTR *(volatile uint16_t *)0x40009026 // TCD Transfer Attributes -#define DMA_TCD1_NBYTES_MLNO *(volatile uint32_t *)0x40009028 // TCD Minor Byte Count, Minor Loop Disabled +#define DMA_TCD1_SADDR *(volatile const void * volatile *)0x40009020 // TCD Source Address +#define DMA_TCD1_SOFF *(volatile int16_t *)0x40009024 // TCD Signed Source Address Offset +#define DMA_TCD1_ATTR *(volatile uint16_t *)0x40009026 // TCD Transfer Attributes +#define DMA_TCD1_NBYTES_MLNO *(volatile uint32_t *)0x40009028 // TCD Minor Byte Count, Minor Loop Disabled #define DMA_TCD1_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled #define DMA_TCD1_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled -#define DMA_TCD1_SLAST *(volatile int32_t *)0x4000902C // TCD Last Source Address Adjustment -#define DMA_TCD1_DADDR *(volatile void * volatile *)0x40009030 // TCD Destination Address -#define DMA_TCD1_DOFF *(volatile int16_t *)0x40009034 // TCD Signed Destination Address Offset +#define DMA_TCD1_SLAST *(volatile int32_t *)0x4000902C // TCD Last Source Address Adjustment +#define DMA_TCD1_DADDR *(volatile void * volatile *)0x40009030 // TCD Destination Address +#define DMA_TCD1_DOFF *(volatile int16_t *)0x40009034 // TCD Signed Destination Address Offset #define DMA_TCD1_CITER_ELINKYES *(volatile uint16_t *)0x40009036 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled -#define DMA_TCD1_CITER_ELINKNO *(volatile uint16_t *)0x40009036 // ?? -#define DMA_TCD1_DLASTSGA *(volatile int32_t *)0x40009038 // TCD Last Destination Address Adjustment/Scatter Gather Address -#define DMA_TCD1_CSR *(volatile uint16_t *)0x4000903C // TCD Control and Status +#define DMA_TCD1_CITER_ELINKNO *(volatile uint16_t *)0x40009036 // ?? +#define DMA_TCD1_DLASTSGA *(volatile int32_t *)0x40009038 // TCD Last Destination Address Adjustment/Scatter Gather Address +#define DMA_TCD1_CSR *(volatile uint16_t *)0x4000903C // TCD Control and Status #define DMA_TCD1_BITER_ELINKYES *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled -#define DMA_TCD1_BITER_ELINKNO *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled +#define DMA_TCD1_BITER_ELINKNO *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled -#define DMA_TCD2_SADDR *(volatile const void * volatile *)0x40009040 // TCD Source Address -#define DMA_TCD2_SOFF *(volatile int16_t *)0x40009044 // TCD Signed Source Address Offset -#define DMA_TCD2_ATTR *(volatile uint16_t *)0x40009046 // TCD Transfer Attributes -#define DMA_TCD2_NBYTES_MLNO *(volatile uint32_t *)0x40009048 // TCD Minor Byte Count, Minor Loop Disabled +#define DMA_TCD2_SADDR *(volatile const void * volatile *)0x40009040 // TCD Source Address +#define DMA_TCD2_SOFF *(volatile int16_t *)0x40009044 // TCD Signed Source Address Offset +#define DMA_TCD2_ATTR *(volatile uint16_t *)0x40009046 // TCD Transfer Attributes +#define DMA_TCD2_NBYTES_MLNO *(volatile uint32_t *)0x40009048 // TCD Minor Byte Count, Minor Loop Disabled #define DMA_TCD2_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled #define DMA_TCD2_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled -#define DMA_TCD2_SLAST *(volatile int32_t *)0x4000904C // TCD Last Source Address Adjustment -#define DMA_TCD2_DADDR *(volatile void * volatile *)0x40009050 // TCD Destination Address -#define DMA_TCD2_DOFF *(volatile int16_t *)0x40009054 // TCD Signed Destination Address Offset +#define DMA_TCD2_SLAST *(volatile int32_t *)0x4000904C // TCD Last Source Address Adjustment +#define DMA_TCD2_DADDR *(volatile void * volatile *)0x40009050 // TCD Destination Address +#define DMA_TCD2_DOFF *(volatile int16_t *)0x40009054 // TCD Signed Destination Address Offset #define DMA_TCD2_CITER_ELINKYES *(volatile uint16_t *)0x40009056 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled -#define DMA_TCD2_CITER_ELINKNO *(volatile uint16_t *)0x40009056 // ?? -#define DMA_TCD2_DLASTSGA *(volatile int32_t *)0x40009058 // TCD Last Destination Address Adjustment/Scatter Gather Address -#define DMA_TCD2_CSR *(volatile uint16_t *)0x4000905C // TCD Control and Status +#define DMA_TCD2_CITER_ELINKNO *(volatile uint16_t *)0x40009056 // ?? +#define DMA_TCD2_DLASTSGA *(volatile int32_t *)0x40009058 // TCD Last Destination Address Adjustment/Scatter Gather Address +#define DMA_TCD2_CSR *(volatile uint16_t *)0x4000905C // TCD Control and Status #define DMA_TCD2_BITER_ELINKYES *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled -#define DMA_TCD2_BITER_ELINKNO *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled +#define DMA_TCD2_BITER_ELINKNO *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled -#define DMA_TCD3_SADDR *(volatile const void * volatile *)0x40009060 // TCD Source Address -#define DMA_TCD3_SOFF *(volatile int16_t *)0x40009064 // TCD Signed Source Address Offset -#define DMA_TCD3_ATTR *(volatile uint16_t *)0x40009066 // TCD Transfer Attributes -#define DMA_TCD3_NBYTES_MLNO *(volatile uint32_t *)0x40009068 // TCD Minor Byte Count, Minor Loop Disabled +#define DMA_TCD3_SADDR *(volatile const void * volatile *)0x40009060 // TCD Source Address +#define DMA_TCD3_SOFF *(volatile int16_t *)0x40009064 // TCD Signed Source Address Offset +#define DMA_TCD3_ATTR *(volatile uint16_t *)0x40009066 // TCD Transfer Attributes +#define DMA_TCD3_NBYTES_MLNO *(volatile uint32_t *)0x40009068 // TCD Minor Byte Count, Minor Loop Disabled #define DMA_TCD3_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled #define DMA_TCD3_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled -#define DMA_TCD3_SLAST *(volatile int32_t *)0x4000906C // TCD Last Source Address Adjustment -#define DMA_TCD3_DADDR *(volatile void * volatile *)0x40009070 // TCD Destination Address -#define DMA_TCD3_DOFF *(volatile int16_t *)0x40009074 // TCD Signed Destination Address Offset +#define DMA_TCD3_SLAST *(volatile int32_t *)0x4000906C // TCD Last Source Address Adjustment +#define DMA_TCD3_DADDR *(volatile void * volatile *)0x40009070 // TCD Destination Address +#define DMA_TCD3_DOFF *(volatile int16_t *)0x40009074 // TCD Signed Destination Address Offset #define DMA_TCD3_CITER_ELINKYES *(volatile uint16_t *)0x40009076 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled -#define DMA_TCD3_CITER_ELINKNO *(volatile uint16_t *)0x40009076 // ?? -#define DMA_TCD3_DLASTSGA *(volatile int32_t *)0x40009078 // TCD Last Destination Address Adjustment/Scatter Gather Address -#define DMA_TCD3_CSR *(volatile uint16_t *)0x4000907C // TCD Control and Status +#define DMA_TCD3_CITER_ELINKNO *(volatile uint16_t *)0x40009076 // ?? +#define DMA_TCD3_DLASTSGA *(volatile int32_t *)0x40009078 // TCD Last Destination Address Adjustment/Scatter Gather Address +#define DMA_TCD3_CSR *(volatile uint16_t *)0x4000907C // TCD Control and Status #define DMA_TCD3_BITER_ELINKYES *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled -#define DMA_TCD3_BITER_ELINKNO *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled +#define DMA_TCD3_BITER_ELINKNO *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled // Chapter 22: External Watchdog Monitor (EWM) #define EWM_CTRL *(volatile uint8_t *)0x40061000 // Control Register @@ -671,18 +671,18 @@ // Chapter 23: Watchdog Timer (WDOG) #define WDOG_STCTRLH *(volatile uint16_t *)0x40052000 // Watchdog Status and Control Register High -#define WDOG_STCTRLH_DISTESTWDOG (uint16_t)0x4000 // Allows the WDOG's functional test mode to be disabled permanently. -#define WDOG_STCTRLH_BYTESEL(n) (uint16_t)(((n) & 3) << 12) // selects the byte to be tested when the watchdog is in the byte test mode. -#define WDOG_STCTRLH_TESTSEL (uint16_t)0x0800 -#define WDOG_STCTRLH_TESTWDOG (uint16_t)0x0400 -#define WDOG_STCTRLH_WAITEN (uint16_t)0x0080 -#define WDOG_STCTRLH_STOPEN (uint16_t)0x0040 -#define WDOG_STCTRLH_DBGEN (uint16_t)0x0020 -#define WDOG_STCTRLH_ALLOWUPDATE (uint16_t)0x0010 -#define WDOG_STCTRLH_WINEN (uint16_t)0x0008 -#define WDOG_STCTRLH_IRQRSTEN (uint16_t)0x0004 -#define WDOG_STCTRLH_CLKSRC (uint16_t)0x0002 -#define WDOG_STCTRLH_WDOGEN (uint16_t)0x0001 +#define WDOG_STCTRLH_DISTESTWDOG (uint16_t)0x4000 // Allows the WDOG's functional test mode to be disabled permanently. +#define WDOG_STCTRLH_BYTESEL(n) (uint16_t)(((n) & 3) << 12) // selects the byte to be tested when the watchdog is in the byte test mode. +#define WDOG_STCTRLH_TESTSEL (uint16_t)0x0800 +#define WDOG_STCTRLH_TESTWDOG (uint16_t)0x0400 +#define WDOG_STCTRLH_WAITEN (uint16_t)0x0080 +#define WDOG_STCTRLH_STOPEN (uint16_t)0x0040 +#define WDOG_STCTRLH_DBGEN (uint16_t)0x0020 +#define WDOG_STCTRLH_ALLOWUPDATE (uint16_t)0x0010 +#define WDOG_STCTRLH_WINEN (uint16_t)0x0008 +#define WDOG_STCTRLH_IRQRSTEN (uint16_t)0x0004 +#define WDOG_STCTRLH_CLKSRC (uint16_t)0x0002 +#define WDOG_STCTRLH_WDOGEN (uint16_t)0x0001 #define WDOG_STCTRLL *(volatile uint16_t *)0x40052002 // Watchdog Status and Control Register Low #define WDOG_TOVALH *(volatile uint16_t *)0x40052004 // Watchdog Time-out Value Register High #define WDOG_TOVALL *(volatile uint16_t *)0x40052006 // Watchdog Time-out Value Register Low @@ -690,8 +690,8 @@ #define WDOG_WINL *(volatile uint16_t *)0x4005200A // Watchdog Window Register Low #define WDOG_REFRESH *(volatile uint16_t *)0x4005200C // Watchdog Refresh register #define WDOG_UNLOCK *(volatile uint16_t *)0x4005200E // Watchdog Unlock register -#define WDOG_UNLOCK_SEQ1 (uint16_t)0xC520 -#define WDOG_UNLOCK_SEQ2 (uint16_t)0xD928 +#define WDOG_UNLOCK_SEQ1 (uint16_t)0xC520 +#define WDOG_UNLOCK_SEQ2 (uint16_t)0xD928 #define WDOG_TMROUTH *(volatile uint16_t *)0x40052010 // Watchdog Timer Output Register High #define WDOG_TMROUTL *(volatile uint16_t *)0x40052012 // Watchdog Timer Output Register Low #define WDOG_RSTCNT *(volatile uint16_t *)0x40052014 // Watchdog Reset Count register @@ -699,50 +699,50 @@ // Chapter 24: Multipurpose Clock Generator (MCG) #define MCG_C1 *(volatile uint8_t *)0x40064000 // MCG Control 1 Register -#define MCG_C1_IREFSTEN (uint8_t)0x01 // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. -#define MCG_C1_IRCLKEN (uint8_t)0x02 // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK. -#define MCG_C1_IREFS (uint8_t)0x04 // Internal Reference Select, Selects the reference clock source for the FLL. -#define MCG_C1_FRDIV(n) (uint8_t)(((n) & 0x07) << 3) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL -#define MCG_C1_CLKS(n) (uint8_t)(((n) & 0x03) << 6) // Clock Source Select, Selects the clock source for MCGOUTCLK +#define MCG_C1_IREFSTEN (uint8_t)0x01 // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. +#define MCG_C1_IRCLKEN (uint8_t)0x02 // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK. +#define MCG_C1_IREFS (uint8_t)0x04 // Internal Reference Select, Selects the reference clock source for the FLL. +#define MCG_C1_FRDIV(n) (uint8_t)(((n) & 0x07) << 3) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL +#define MCG_C1_CLKS(n) (uint8_t)(((n) & 0x03) << 6) // Clock Source Select, Selects the clock source for MCGOUTCLK #define MCG_C2 *(volatile uint8_t *)0x40064001 // MCG Control 2 Register -#define MCG_C2_IRCS (uint8_t)0x01 // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source. -#define MCG_C2_LP (uint8_t)0x02 // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. -#define MCG_C2_EREFS (uint8_t)0x04 // External Reference Select, Selects the source for the external reference clock. -#define MCG_C2_HGO0 (uint8_t)0x08 // High Gain Oscillator Select, Controls the crystal oscillator mode of operation -#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator -#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 +#define MCG_C2_IRCS (uint8_t)0x01 // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source. +#define MCG_C2_LP (uint8_t)0x02 // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. +#define MCG_C2_EREFS (uint8_t)0x04 // External Reference Select, Selects the source for the external reference clock. +#define MCG_C2_HGO0 (uint8_t)0x08 // High Gain Oscillator Select, Controls the crystal oscillator mode of operation +#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator +#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 #define MCG_C3 *(volatile uint8_t *)0x40064002 // MCG Control 3 Register -#define MCG_C3_SCTRIM(n) (uint8_t)(n) // Slow Internal Reference Clock Trim Setting +#define MCG_C3_SCTRIM(n) (uint8_t)(n) // Slow Internal Reference Clock Trim Setting #define MCG_C4 *(volatile uint8_t *)0x40064003 // MCG Control 4 Register -#define MCG_C4_SCFTRIM (uint8_t)0x01 // Slow Internal Reference Clock Fine Trim -#define MCG_C4_FCTRIM(n) (uint8_t)(((n) & 0x0F) << 1) // Fast Internal Reference Clock Trim Setting -#define MCG_C4_DRST_DRS(n) (uint8_t)(((n) & 0x03) << 5) // DCO Range Select -#define MCG_C4_DMX32 (uint8_t)0x80 // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed +#define MCG_C4_SCFTRIM (uint8_t)0x01 // Slow Internal Reference Clock Fine Trim +#define MCG_C4_FCTRIM(n) (uint8_t)(((n) & 0x0F) << 1) // Fast Internal Reference Clock Trim Setting +#define MCG_C4_DRST_DRS(n) (uint8_t)(((n) & 0x03) << 5) // DCO Range Select +#define MCG_C4_DMX32 (uint8_t)0x80 // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed #define MCG_C5 *(volatile uint8_t *)0x40064004 // MCG Control 5 Register -#define MCG_C5_PRDIV0(n) (uint8_t)((n) & 0x1F) // PLL External Reference Divider -#define MCG_C5_PLLSTEN0 (uint8_t)0x20 // PLL Stop Enable -#define MCG_C5_PLLCLKEN0 (uint8_t)0x40 // PLL Clock Enable +#define MCG_C5_PRDIV0(n) (uint8_t)((n) & 0x1F) // PLL External Reference Divider +#define MCG_C5_PLLSTEN0 (uint8_t)0x20 // PLL Stop Enable +#define MCG_C5_PLLCLKEN0 (uint8_t)0x40 // PLL Clock Enable #define MCG_C6 *(volatile uint8_t *)0x40064005 // MCG Control 6 Register -#define MCG_C6_VDIV0(n) (uint8_t)((n) & 0x1F) // VCO 0 Divider -#define MCG_C6_CME0 (uint8_t)0x20 // Clock Monitor Enable -#define MCG_C6_PLLS (uint8_t)0x40 // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. -#define MCG_C6_LOLIE0 (uint8_t)0x80 // Loss of Lock Interrrupt Enable +#define MCG_C6_VDIV0(n) (uint8_t)((n) & 0x1F) // VCO 0 Divider +#define MCG_C6_CME0 (uint8_t)0x20 // Clock Monitor Enable +#define MCG_C6_PLLS (uint8_t)0x40 // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. +#define MCG_C6_LOLIE0 (uint8_t)0x80 // Loss of Lock Interrrupt Enable #define MCG_S *(volatile uint8_t *)0x40064006 // MCG Status Register -#define MCG_S_IRCST (uint8_t)0x01 // Internal Reference Clock Status -#define MCG_S_OSCINIT0 (uint8_t)0x02 // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator -#define MCG_S_CLKST(n) (uint8_t)(((n) & 0x03) << 2) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL -#define MCG_S_CLKST_MASK (uint8_t)0x0C -#define MCG_S_IREFST (uint8_t)0x10 // Internal Reference Status -#define MCG_S_PLLST (uint8_t)0x20 // PLL Select Status -#define MCG_S_LOCK0 (uint8_t)0x40 // Lock Status, 0=PLL Unlocked, 1=PLL Locked -#define MCG_S_LOLS0 (uint8_t)0x80 // Loss of Lock Status +#define MCG_S_IRCST (uint8_t)0x01 // Internal Reference Clock Status +#define MCG_S_OSCINIT0 (uint8_t)0x02 // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator +#define MCG_S_CLKST(n) (uint8_t)(((n) & 0x03) << 2) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL +#define MCG_S_CLKST_MASK (uint8_t)0x0C +#define MCG_S_IREFST (uint8_t)0x10 // Internal Reference Status +#define MCG_S_PLLST (uint8_t)0x20 // PLL Select Status +#define MCG_S_LOCK0 (uint8_t)0x40 // Lock Status, 0=PLL Unlocked, 1=PLL Locked +#define MCG_S_LOLS0 (uint8_t)0x80 // Loss of Lock Status #define MCG_SC *(volatile uint8_t *)0x40064008 // MCG Status and Control Register -#define MCG_SC_LOCS0 (uint8_t)0x01 // OSC0 Loss of Clock Status -#define MCG_SC_FCRDIV(n) (uint8_t)(((n) & 0x07) << 1) // Fast Clock Internal Reference Divider -#define MCG_SC_FLTPRSRV (uint8_t)0x10 // FLL Filter Preserve Enable -#define MCG_SC_ATMF (uint8_t)0x20 // Automatic Trim Machine Fail Flag -#define MCG_SC_ATMS (uint8_t)0x40 // Automatic Trim Machine Select -#define MCG_SC_ATME (uint8_t)0x80 // Automatic Trim Machine Enable +#define MCG_SC_LOCS0 (uint8_t)0x01 // OSC0 Loss of Clock Status +#define MCG_SC_FCRDIV(n) (uint8_t)(((n) & 0x07) << 1) // Fast Clock Internal Reference Divider +#define MCG_SC_FLTPRSRV (uint8_t)0x10 // FLL Filter Preserve Enable +#define MCG_SC_ATMF (uint8_t)0x20 // Automatic Trim Machine Fail Flag +#define MCG_SC_ATMS (uint8_t)0x40 // Automatic Trim Machine Select +#define MCG_SC_ATME (uint8_t)0x80 // Automatic Trim Machine Enable #define MCG_ATCVH *(volatile uint8_t *)0x4006400A // MCG Auto Trim Compare Value High Register #define MCG_ATCVL *(volatile uint8_t *)0x4006400B // MCG Auto Trim Compare Value Low Register #define MCG_C7 *(volatile uint8_t *)0x4006400C // MCG Control 7 Register @@ -750,48 +750,48 @@ // Chapter 25: Oscillator (OSC) #define OSC0_CR *(volatile uint8_t *)0x40065000 // OSC Control Register -#define OSC_SC16P (uint8_t)0x01 // Oscillator 16 pF Capacitor Load Configure -#define OSC_SC8P (uint8_t)0x02 // Oscillator 8 pF Capacitor Load Configure -#define OSC_SC4P (uint8_t)0x04 // Oscillator 4 pF Capacitor Load Configure -#define OSC_SC2P (uint8_t)0x08 // Oscillator 2 pF Capacitor Load Configure -#define OSC_EREFSTEN (uint8_t)0x20 // External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. -#define OSC_ERCLKEN (uint8_t)0x80 // External Reference Enable, Enables external reference clock (OSCERCLK). +#define OSC_SC16P (uint8_t)0x01 // Oscillator 16 pF Capacitor Load Configure +#define OSC_SC8P (uint8_t)0x02 // Oscillator 8 pF Capacitor Load Configure +#define OSC_SC4P (uint8_t)0x04 // Oscillator 4 pF Capacitor Load Configure +#define OSC_SC2P (uint8_t)0x08 // Oscillator 2 pF Capacitor Load Configure +#define OSC_EREFSTEN (uint8_t)0x20 // External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. +#define OSC_ERCLKEN (uint8_t)0x80 // External Reference Enable, Enables external reference clock (OSCERCLK). // Chapter 27: Flash Memory Controller (FMC) -#define FMC_PFAPR *(volatile uint32_t *)0x4001F000 // Flash Access Protection -#define FMC_PFB0CR *(volatile uint32_t *)0x4001F004 // Flash Control -#define FMC_TAGVDW0S0 *(volatile uint32_t *)0x4001F100 // Cache Tag Storage -#define FMC_TAGVDW0S1 *(volatile uint32_t *)0x4001F104 // Cache Tag Storage -#define FMC_TAGVDW1S0 *(volatile uint32_t *)0x4001F108 // Cache Tag Storage -#define FMC_TAGVDW1S1 *(volatile uint32_t *)0x4001F10C // Cache Tag Storage -#define FMC_TAGVDW2S0 *(volatile uint32_t *)0x4001F110 // Cache Tag Storage -#define FMC_TAGVDW2S1 *(volatile uint32_t *)0x4001F114 // Cache Tag Storage -#define FMC_TAGVDW3S0 *(volatile uint32_t *)0x4001F118 // Cache Tag Storage -#define FMC_TAGVDW3S1 *(volatile uint32_t *)0x4001F11C // Cache Tag Storage -#define FMC_DATAW0S0 *(volatile uint32_t *)0x4001F200 // Cache Data Storage -#define FMC_DATAW0S1 *(volatile uint32_t *)0x4001F204 // Cache Data Storage -#define FMC_DATAW1S0 *(volatile uint32_t *)0x4001F208 // Cache Data Storage -#define FMC_DATAW1S1 *(volatile uint32_t *)0x4001F20C // Cache Data Storage -#define FMC_DATAW2S0 *(volatile uint32_t *)0x4001F210 // Cache Data Storage -#define FMC_DATAW2S1 *(volatile uint32_t *)0x4001F214 // Cache Data Storage -#define FMC_DATAW3S0 *(volatile uint32_t *)0x4001F218 // Cache Data Storage -#define FMC_DATAW3S1 *(volatile uint32_t *)0x4001F21C // Cache Data Storage +#define FMC_PFAPR *(volatile uint32_t *)0x4001F000 // Flash Access Protection +#define FMC_PFB0CR *(volatile uint32_t *)0x4001F004 // Flash Control +#define FMC_TAGVDW0S0 *(volatile uint32_t *)0x4001F100 // Cache Tag Storage +#define FMC_TAGVDW0S1 *(volatile uint32_t *)0x4001F104 // Cache Tag Storage +#define FMC_TAGVDW1S0 *(volatile uint32_t *)0x4001F108 // Cache Tag Storage +#define FMC_TAGVDW1S1 *(volatile uint32_t *)0x4001F10C // Cache Tag Storage +#define FMC_TAGVDW2S0 *(volatile uint32_t *)0x4001F110 // Cache Tag Storage +#define FMC_TAGVDW2S1 *(volatile uint32_t *)0x4001F114 // Cache Tag Storage +#define FMC_TAGVDW3S0 *(volatile uint32_t *)0x4001F118 // Cache Tag Storage +#define FMC_TAGVDW3S1 *(volatile uint32_t *)0x4001F11C // Cache Tag Storage +#define FMC_DATAW0S0 *(volatile uint32_t *)0x4001F200 // Cache Data Storage +#define FMC_DATAW0S1 *(volatile uint32_t *)0x4001F204 // Cache Data Storage +#define FMC_DATAW1S0 *(volatile uint32_t *)0x4001F208 // Cache Data Storage +#define FMC_DATAW1S1 *(volatile uint32_t *)0x4001F20C // Cache Data Storage +#define FMC_DATAW2S0 *(volatile uint32_t *)0x4001F210 // Cache Data Storage +#define FMC_DATAW2S1 *(volatile uint32_t *)0x4001F214 // Cache Data Storage +#define FMC_DATAW3S0 *(volatile uint32_t *)0x4001F218 // Cache Data Storage +#define FMC_DATAW3S1 *(volatile uint32_t *)0x4001F21C // Cache Data Storage // Chapter 28: Flash Memory Module (FTFL) -#define FTFL_FSTAT *(volatile uint8_t *)0x40020000 // Flash Status Register -#define FTFL_FSTAT_CCIF (uint8_t)0x80 // Command Complete Interrupt Flag -#define FTFL_FSTAT_RDCOLERR (uint8_t)0x40 // Flash Read Collision Error Flag -#define FTFL_FSTAT_ACCERR (uint8_t)0x20 // Flash Access Error Flag -#define FTFL_FSTAT_FPVIOL (uint8_t)0x10 // Flash Protection Violation Flag -#define FTFL_FSTAT_MGSTAT0 (uint8_t)0x01 // Memory Controller Command Completion Status Flag -#define FTFL_FCNFG *(volatile uint8_t *)0x40020001 // Flash Configuration Register -#define FTFL_FCNFG_CCIE (uint8_t)0x80 // Command Complete Interrupt Enable -#define FTFL_FCNFG_RDCOLLIE (uint8_t)0x40 // Read Collision Error Interrupt Enable -#define FTFL_FCNFG_ERSAREQ (uint8_t)0x20 // Erase All Request -#define FTFL_FCNFG_ERSSUSP (uint8_t)0x10 // Erase Suspend -#define FTFL_FCNFG_PFLSH (uint8_t)0x04 // Flash memory configuration -#define FTFL_FCNFG_RAMRDY (uint8_t)0x02 // RAM Ready -#define FTFL_FCNFG_EEERDY (uint8_t)0x01 // EEPROM Ready +#define FTFL_FSTAT *(volatile uint8_t *)0x40020000 // Flash Status Register +#define FTFL_FSTAT_CCIF (uint8_t)0x80 // Command Complete Interrupt Flag +#define FTFL_FSTAT_RDCOLERR (uint8_t)0x40 // Flash Read Collision Error Flag +#define FTFL_FSTAT_ACCERR (uint8_t)0x20 // Flash Access Error Flag +#define FTFL_FSTAT_FPVIOL (uint8_t)0x10 // Flash Protection Violation Flag +#define FTFL_FSTAT_MGSTAT0 (uint8_t)0x01 // Memory Controller Command Completion Status Flag +#define FTFL_FCNFG *(volatile uint8_t *)0x40020001 // Flash Configuration Register +#define FTFL_FCNFG_CCIE (uint8_t)0x80 // Command Complete Interrupt Enable +#define FTFL_FCNFG_RDCOLLIE (uint8_t)0x40 // Read Collision Error Interrupt Enable +#define FTFL_FCNFG_ERSAREQ (uint8_t)0x20 // Erase All Request +#define FTFL_FCNFG_ERSSUSP (uint8_t)0x10 // Erase Suspend +#define FTFL_FCNFG_PFLSH (uint8_t)0x04 // Flash memory configuration +#define FTFL_FCNFG_RAMRDY (uint8_t)0x02 // RAM Ready +#define FTFL_FCNFG_EEERDY (uint8_t)0x01 // EEPROM Ready #define FTFL_FSEC *(const uint8_t *)0x40020002 // Flash Security Register #define FTFL_FOPT *(const uint8_t *)0x40020003 // Flash Option Register #define FTFL_FCCOB3 *(volatile uint8_t *)0x40020004 // Flash Common Command Object Registers @@ -821,125 +821,125 @@ // Chapter 31: Analog-to-Digital Converter (ADC) #define ADC0_SC1A *(volatile uint32_t *)0x4003B000 // ADC status and control registers 1 #define ADC0_SC1B *(volatile uint32_t *)0x4003B004 // ADC status and control registers 1 -#define ADC_SC1_COCO (uint32_t)0x80 // Conversion complete flag -#define ADC_SC1_AIEN (uint32_t)0x40 // Interrupt enable -#define ADC_SC1_DIFF (uint32_t)0x20 // Differential mode enable -#define ADC_SC1_ADCH(n) (uint32_t)((n) & 0x1F) // Input channel select +#define ADC_SC1_COCO (uint32_t)0x80 // Conversion complete flag +#define ADC_SC1_AIEN (uint32_t)0x40 // Interrupt enable +#define ADC_SC1_DIFF (uint32_t)0x20 // Differential mode enable +#define ADC_SC1_ADCH(n) (uint32_t)((n) & 0x1F) // Input channel select #define ADC0_CFG1 *(volatile uint32_t *)0x4003B008 // ADC configuration register 1 -#define ADC_CFG1_ADLPC (uint32_t)0x80 // Low-power configuration -#define ADC_CFG1_ADIV(n) (uint32_t)(((n) & 3) << 5) // Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8 -#define ADC_CFG1_ADLSMP (uint32_t)0x10 // Sample time configuration, 0=Short, 1=Long -#define ADC_CFG1_MODE(n) (uint32_t)(((n) & 3) << 2) // Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit -#define ADC_CFG1_ADICLK(n) (uint32_t)(((n) & 3) << 0) // Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async +#define ADC_CFG1_ADLPC (uint32_t)0x80 // Low-power configuration +#define ADC_CFG1_ADIV(n) (uint32_t)(((n) & 3) << 5) // Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8 +#define ADC_CFG1_ADLSMP (uint32_t)0x10 // Sample time configuration, 0=Short, 1=Long +#define ADC_CFG1_MODE(n) (uint32_t)(((n) & 3) << 2) // Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit +#define ADC_CFG1_ADICLK(n) (uint32_t)(((n) & 3) << 0) // Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async #define ADC0_CFG2 *(volatile uint32_t *)0x4003B00C // Configuration register 2 -#define ADC_CFG2_MUXSEL (uint32_t)0x10 // 0=a channels, 1=b channels -#define ADC_CFG2_ADACKEN (uint32_t)0x08 // async clock enable -#define ADC_CFG2_ADHSC (uint32_t)0x04 // High speed configuration -#define ADC_CFG2_ADLSTS(n) (uint32_t)(((n) & 3) << 0) // Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles +#define ADC_CFG2_MUXSEL (uint32_t)0x10 // 0=a channels, 1=b channels +#define ADC_CFG2_ADACKEN (uint32_t)0x08 // async clock enable +#define ADC_CFG2_ADHSC (uint32_t)0x04 // High speed configuration +#define ADC_CFG2_ADLSTS(n) (uint32_t)(((n) & 3) << 0) // Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles #define ADC0_RA *(volatile uint32_t *)0x4003B010 // ADC data result register #define ADC0_RB *(volatile uint32_t *)0x4003B014 // ADC data result register #define ADC0_CV1 *(volatile uint32_t *)0x4003B018 // Compare value registers #define ADC0_CV2 *(volatile uint32_t *)0x4003B01C // Compare value registers #define ADC0_SC2 *(volatile uint32_t *)0x4003B020 // Status and control register 2 -#define ADC_SC2_ADACT (uint32_t)0x80 // Conversion active -#define ADC_SC2_ADTRG (uint32_t)0x40 // Conversion trigger select, 0=software, 1=hardware -#define ADC_SC2_ACFE (uint32_t)0x20 // Compare function enable -#define ADC_SC2_ACFGT (uint32_t)0x10 // Compare function greater than enable -#define ADC_SC2_ACREN (uint32_t)0x08 // Compare function range enable -#define ADC_SC2_DMAEN (uint32_t)0x04 // DMA enable -#define ADC_SC2_REFSEL(n) (uint32_t)(((n) & 3) << 0) // Voltage reference, 0=vcc/external, 1=1.2 volts +#define ADC_SC2_ADACT (uint32_t)0x80 // Conversion active +#define ADC_SC2_ADTRG (uint32_t)0x40 // Conversion trigger select, 0=software, 1=hardware +#define ADC_SC2_ACFE (uint32_t)0x20 // Compare function enable +#define ADC_SC2_ACFGT (uint32_t)0x10 // Compare function greater than enable +#define ADC_SC2_ACREN (uint32_t)0x08 // Compare function range enable +#define ADC_SC2_DMAEN (uint32_t)0x04 // DMA enable +#define ADC_SC2_REFSEL(n) (uint32_t)(((n) & 3) << 0) // Voltage reference, 0=vcc/external, 1=1.2 volts #define ADC0_SC3 *(volatile uint32_t *)0x4003B024 // Status and control register 3 -#define ADC_SC3_CAL (uint32_t)0x80 // Calibration, 1=begin, stays set while cal in progress -#define ADC_SC3_CALF (uint32_t)0x40 // Calibration failed flag -#define ADC_SC3_ADCO (uint32_t)0x08 // Continuous conversion enable -#define ADC_SC3_AVGE (uint32_t)0x04 // Hardware average enable -#define ADC_SC3_AVGS(n) (uint32_t)(((n) & 3) << 0) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples -#define ADC0_OFS *(volatile uint32_t *)0x4003B028 // ADC offset correction register -#define ADC0_PG *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register -#define ADC0_MG *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register -#define ADC0_CLPD *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register -#define ADC0_CLPS *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register -#define ADC0_CLP4 *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register -#define ADC0_CLP3 *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register -#define ADC0_CLP2 *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register -#define ADC0_CLP1 *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register -#define ADC0_CLP0 *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register -#define ADC0_CLMD *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register -#define ADC0_CLMS *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register -#define ADC0_CLM4 *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register -#define ADC0_CLM3 *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register -#define ADC0_CLM2 *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register -#define ADC0_CLM1 *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register -#define ADC0_CLM0 *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register +#define ADC_SC3_CAL (uint32_t)0x80 // Calibration, 1=begin, stays set while cal in progress +#define ADC_SC3_CALF (uint32_t)0x40 // Calibration failed flag +#define ADC_SC3_ADCO (uint32_t)0x08 // Continuous conversion enable +#define ADC_SC3_AVGE (uint32_t)0x04 // Hardware average enable +#define ADC_SC3_AVGS(n) (uint32_t)(((n) & 3) << 0) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples +#define ADC0_OFS *(volatile uint32_t *)0x4003B028 // ADC offset correction register +#define ADC0_PG *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register +#define ADC0_MG *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register +#define ADC0_CLPD *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register +#define ADC0_CLPS *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register +#define ADC0_CLP4 *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register +#define ADC0_CLP3 *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register +#define ADC0_CLP2 *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register +#define ADC0_CLP1 *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register +#define ADC0_CLP0 *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register +#define ADC0_CLMD *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register +#define ADC0_CLMS *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register +#define ADC0_CLM4 *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register +#define ADC0_CLM3 *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register +#define ADC0_CLM2 *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register +#define ADC0_CLM1 *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register +#define ADC0_CLM0 *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register -#define ADC1_SC1A *(volatile uint32_t *)0x400BB000 // ADC status and control registers 1 -#define ADC1_SC1B *(volatile uint32_t *)0x400BB004 // ADC status and control registers 1 -#define ADC1_CFG1 *(volatile uint32_t *)0x400BB008 // ADC configuration register 1 -#define ADC1_CFG2 *(volatile uint32_t *)0x400BB00C // Configuration register 2 -#define ADC1_RA *(volatile uint32_t *)0x400BB010 // ADC data result register -#define ADC1_RB *(volatile uint32_t *)0x400BB014 // ADC data result register -#define ADC1_CV1 *(volatile uint32_t *)0x400BB018 // Compare value registers -#define ADC1_CV2 *(volatile uint32_t *)0x400BB01C // Compare value registers -#define ADC1_SC2 *(volatile uint32_t *)0x400BB020 // Status and control register 2 -#define ADC1_SC3 *(volatile uint32_t *)0x400BB024 // Status and control register 3 -#define ADC1_OFS *(volatile uint32_t *)0x400BB028 // ADC offset correction register -#define ADC1_PG *(volatile uint32_t *)0x400BB02C // ADC plus-side gain register -#define ADC1_MG *(volatile uint32_t *)0x400BB030 // ADC minus-side gain register -#define ADC1_CLPD *(volatile uint32_t *)0x400BB034 // ADC plus-side general calibration value register -#define ADC1_CLPS *(volatile uint32_t *)0x400BB038 // ADC plus-side general calibration value register -#define ADC1_CLP4 *(volatile uint32_t *)0x400BB03C // ADC plus-side general calibration value register -#define ADC1_CLP3 *(volatile uint32_t *)0x400BB040 // ADC plus-side general calibration value register -#define ADC1_CLP2 *(volatile uint32_t *)0x400BB044 // ADC plus-side general calibration value register -#define ADC1_CLP1 *(volatile uint32_t *)0x400BB048 // ADC plus-side general calibration value register -#define ADC1_CLP0 *(volatile uint32_t *)0x400BB04C // ADC plus-side general calibration value register -#define ADC1_CLMD *(volatile uint32_t *)0x400BB054 // ADC minus-side general calibration value register -#define ADC1_CLMS *(volatile uint32_t *)0x400BB058 // ADC minus-side general calibration value register -#define ADC1_CLM4 *(volatile uint32_t *)0x400BB05C // ADC minus-side general calibration value register -#define ADC1_CLM3 *(volatile uint32_t *)0x400BB060 // ADC minus-side general calibration value register -#define ADC1_CLM2 *(volatile uint32_t *)0x400BB064 // ADC minus-side general calibration value register -#define ADC1_CLM1 *(volatile uint32_t *)0x400BB068 // ADC minus-side general calibration value register -#define ADC1_CLM0 *(volatile uint32_t *)0x400BB06C // ADC minus-side general calibration value register +#define ADC1_SC1A *(volatile uint32_t *)0x400BB000 // ADC status and control registers 1 +#define ADC1_SC1B *(volatile uint32_t *)0x400BB004 // ADC status and control registers 1 +#define ADC1_CFG1 *(volatile uint32_t *)0x400BB008 // ADC configuration register 1 +#define ADC1_CFG2 *(volatile uint32_t *)0x400BB00C // Configuration register 2 +#define ADC1_RA *(volatile uint32_t *)0x400BB010 // ADC data result register +#define ADC1_RB *(volatile uint32_t *)0x400BB014 // ADC data result register +#define ADC1_CV1 *(volatile uint32_t *)0x400BB018 // Compare value registers +#define ADC1_CV2 *(volatile uint32_t *)0x400BB01C // Compare value registers +#define ADC1_SC2 *(volatile uint32_t *)0x400BB020 // Status and control register 2 +#define ADC1_SC3 *(volatile uint32_t *)0x400BB024 // Status and control register 3 +#define ADC1_OFS *(volatile uint32_t *)0x400BB028 // ADC offset correction register +#define ADC1_PG *(volatile uint32_t *)0x400BB02C // ADC plus-side gain register +#define ADC1_MG *(volatile uint32_t *)0x400BB030 // ADC minus-side gain register +#define ADC1_CLPD *(volatile uint32_t *)0x400BB034 // ADC plus-side general calibration value register +#define ADC1_CLPS *(volatile uint32_t *)0x400BB038 // ADC plus-side general calibration value register +#define ADC1_CLP4 *(volatile uint32_t *)0x400BB03C // ADC plus-side general calibration value register +#define ADC1_CLP3 *(volatile uint32_t *)0x400BB040 // ADC plus-side general calibration value register +#define ADC1_CLP2 *(volatile uint32_t *)0x400BB044 // ADC plus-side general calibration value register +#define ADC1_CLP1 *(volatile uint32_t *)0x400BB048 // ADC plus-side general calibration value register +#define ADC1_CLP0 *(volatile uint32_t *)0x400BB04C // ADC plus-side general calibration value register +#define ADC1_CLMD *(volatile uint32_t *)0x400BB054 // ADC minus-side general calibration value register +#define ADC1_CLMS *(volatile uint32_t *)0x400BB058 // ADC minus-side general calibration value register +#define ADC1_CLM4 *(volatile uint32_t *)0x400BB05C // ADC minus-side general calibration value register +#define ADC1_CLM3 *(volatile uint32_t *)0x400BB060 // ADC minus-side general calibration value register +#define ADC1_CLM2 *(volatile uint32_t *)0x400BB064 // ADC minus-side general calibration value register +#define ADC1_CLM1 *(volatile uint32_t *)0x400BB068 // ADC minus-side general calibration value register +#define ADC1_CLM0 *(volatile uint32_t *)0x400BB06C // ADC minus-side general calibration value register -#define DAC0_DAT0L *(volatile uint8_t *)0x400CC000 // DAC Data Low Register -#define DAC0_DATH *(volatile uint8_t *)0x400CC001 // DAC Data High Register -#define DAC0_DAT1L *(volatile uint8_t *)0x400CC002 // DAC Data Low Register -#define DAC0_DAT2L *(volatile uint8_t *)0x400CC004 // DAC Data Low Register -#define DAC0_DAT3L *(volatile uint8_t *)0x400CC006 // DAC Data Low Register -#define DAC0_DAT4L *(volatile uint8_t *)0x400CC008 // DAC Data Low Register -#define DAC0_DAT5L *(volatile uint8_t *)0x400CC00A // DAC Data Low Register -#define DAC0_DAT6L *(volatile uint8_t *)0x400CC00C // DAC Data Low Register -#define DAC0_DAT7L *(volatile uint8_t *)0x400CC00E // DAC Data Low Register -#define DAC0_DAT8L *(volatile uint8_t *)0x400CC010 // DAC Data Low Register -#define DAC0_DAT9L *(volatile uint8_t *)0x400CC012 // DAC Data Low Register -#define DAC0_DAT10L *(volatile uint8_t *)0x400CC014 // DAC Data Low Register -#define DAC0_DAT11L *(volatile uint8_t *)0x400CC016 // DAC Data Low Register -#define DAC0_DAT12L *(volatile uint8_t *)0x400CC018 // DAC Data Low Register -#define DAC0_DAT13L *(volatile uint8_t *)0x400CC01A // DAC Data Low Register -#define DAC0_DAT14L *(volatile uint8_t *)0x400CC01C // DAC Data Low Register -#define DAC0_DAT15L *(volatile uint8_t *)0x400CC01E // DAC Data Low Register -#define DAC0_SR *(volatile uint8_t *)0x400CC020 // DAC Status Register -#define DAC0_C0 *(volatile uint8_t *)0x400CC021 // DAC Control Register -#define DAC_C0_DACEN 0x80 // DAC Enable -#define DAC_C0_DACRFS 0x40 // DAC Reference Select -#define DAC_C0_DACTRGSEL 0x20 // DAC Trigger Select -#define DAC_C0_DACSWTRG 0x10 // DAC Software Trigger -#define DAC_C0_LPEN 0x08 // DAC Low Power Control -#define DAC_C0_DACBWIEN 0x04 // DAC Buffer Watermark Interrupt Enable -#define DAC_C0_DACBTIEN 0x02 // DAC Buffer Read Pointer Top Flag Interrupt Enable -#define DAC_C0_DACBBIEN 0x01 // DAC Buffer Read Pointer Bottom Flag Interrupt Enable -#define DAC0_C1 *(volatile uint8_t *)0x400CC022 // DAC Control Register 1 -#define DAC_C1_DMAEN 0x80 // DMA Enable Select -#define DAC_C1_DACBFWM(n) (((n) & 3) << 3) // DAC Buffer Watermark Select -#define DAC_C1_DACBFMD(n) (((n) & 3) << 0) // DAC Buffer Work Mode Select -#define DAC_C1_DACBFEN 0x00 // DAC Buffer Enable +#define DAC0_DAT0L *(volatile uint8_t *)0x400CC000 // DAC Data Low Register +#define DAC0_DATH *(volatile uint8_t *)0x400CC001 // DAC Data High Register +#define DAC0_DAT1L *(volatile uint8_t *)0x400CC002 // DAC Data Low Register +#define DAC0_DAT2L *(volatile uint8_t *)0x400CC004 // DAC Data Low Register +#define DAC0_DAT3L *(volatile uint8_t *)0x400CC006 // DAC Data Low Register +#define DAC0_DAT4L *(volatile uint8_t *)0x400CC008 // DAC Data Low Register +#define DAC0_DAT5L *(volatile uint8_t *)0x400CC00A // DAC Data Low Register +#define DAC0_DAT6L *(volatile uint8_t *)0x400CC00C // DAC Data Low Register +#define DAC0_DAT7L *(volatile uint8_t *)0x400CC00E // DAC Data Low Register +#define DAC0_DAT8L *(volatile uint8_t *)0x400CC010 // DAC Data Low Register +#define DAC0_DAT9L *(volatile uint8_t *)0x400CC012 // DAC Data Low Register +#define DAC0_DAT10L *(volatile uint8_t *)0x400CC014 // DAC Data Low Register +#define DAC0_DAT11L *(volatile uint8_t *)0x400CC016 // DAC Data Low Register +#define DAC0_DAT12L *(volatile uint8_t *)0x400CC018 // DAC Data Low Register +#define DAC0_DAT13L *(volatile uint8_t *)0x400CC01A // DAC Data Low Register +#define DAC0_DAT14L *(volatile uint8_t *)0x400CC01C // DAC Data Low Register +#define DAC0_DAT15L *(volatile uint8_t *)0x400CC01E // DAC Data Low Register +#define DAC0_SR *(volatile uint8_t *)0x400CC020 // DAC Status Register +#define DAC0_C0 *(volatile uint8_t *)0x400CC021 // DAC Control Register +#define DAC_C0_DACEN 0x80 // DAC Enable +#define DAC_C0_DACRFS 0x40 // DAC Reference Select +#define DAC_C0_DACTRGSEL 0x20 // DAC Trigger Select +#define DAC_C0_DACSWTRG 0x10 // DAC Software Trigger +#define DAC_C0_LPEN 0x08 // DAC Low Power Control +#define DAC_C0_DACBWIEN 0x04 // DAC Buffer Watermark Interrupt Enable +#define DAC_C0_DACBTIEN 0x02 // DAC Buffer Read Pointer Top Flag Interrupt Enable +#define DAC_C0_DACBBIEN 0x01 // DAC Buffer Read Pointer Bottom Flag Interrupt Enable +#define DAC0_C1 *(volatile uint8_t *)0x400CC022 // DAC Control Register 1 +#define DAC_C1_DMAEN 0x80 // DMA Enable Select +#define DAC_C1_DACBFWM(n) (((n) & 3) << 3) // DAC Buffer Watermark Select +#define DAC_C1_DACBFMD(n) (((n) & 3) << 0) // DAC Buffer Work Mode Select +#define DAC_C1_DACBFEN 0x00 // DAC Buffer Enable -#define DAC0_C2 *(volatile uint8_t *)0x400CC023 // DAC Control Register 2 -#define DAC_C2_DACBFRP(n) (((n) & 15) << 4) // DAC Buffer Read Pointer -#define DAC_C2_DACBFUP(n) (((n) & 15) << 0) // DAC Buffer Upper Limit +#define DAC0_C2 *(volatile uint8_t *)0x400CC023 // DAC Control Register 2 +#define DAC_C2_DACBFRP(n) (((n) & 15) << 4) // DAC Buffer Read Pointer +#define DAC_C2_DACBFUP(n) (((n) & 15) << 0) // DAC Buffer Upper Limit -//#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator -//#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 +//#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator +//#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 // Chapter 32: Comparator (CMP) #define CMP0_CR0 *(volatile uint8_t *)0x40073000 // CMP Control Register 0 @@ -961,18 +961,18 @@ // Chapter 34: Programmable Delay Block (PDB) #define PDB0_SC *(volatile uint32_t *)0x40036000 // Status and Control Register -#define PDB_SC_LDMOD(n) (((n) & 3) << 18) // Load Mode Select -#define PDB_SC_PDBEIE 0x00020000 // Sequence Error Interrupt Enable -#define PDB_SC_SWTRIG 0x00010000 // Software Trigger -#define PDB_SC_DMAEN 0x00008000 // DMA Enable -#define PDB_SC_PRESCALER(n) (((n) & 7) << 12) // Prescaler Divider Select -#define PDB_SC_TRGSEL(n) (((n) & 15) << 8) // Trigger Input Source Select -#define PDB_SC_PDBEN 0x00000080 // PDB Enable -#define PDB_SC_PDBIF 0x00000040 // PDB Interrupt Flag -#define PDB_SC_PDBIE 0x00000020 // PDB Interrupt Enable. -#define PDB_SC_MULT(n) (((n) & 3) << 2) // Multiplication Factor -#define PDB_SC_CONT 0x00000002 // Continuous Mode Enable -#define PDB_SC_LDOK 0x00000001 // Load OK +#define PDB_SC_LDMOD(n) (((n) & 3) << 18) // Load Mode Select +#define PDB_SC_PDBEIE 0x00020000 // Sequence Error Interrupt Enable +#define PDB_SC_SWTRIG 0x00010000 // Software Trigger +#define PDB_SC_DMAEN 0x00008000 // DMA Enable +#define PDB_SC_PRESCALER(n) (((n) & 7) << 12) // Prescaler Divider Select +#define PDB_SC_TRGSEL(n) (((n) & 15) << 8) // Trigger Input Source Select +#define PDB_SC_PDBEN 0x00000080 // PDB Enable +#define PDB_SC_PDBIF 0x00000040 // PDB Interrupt Flag +#define PDB_SC_PDBIE 0x00000020 // PDB Interrupt Enable. +#define PDB_SC_MULT(n) (((n) & 3) << 2) // Multiplication Factor +#define PDB_SC_CONT 0x00000002 // Continuous Mode Enable +#define PDB_SC_LDOK 0x00000001 // Load OK #define PDB0_MOD *(volatile uint32_t *)0x40036004 // Modulus Register #define PDB0_CNT *(volatile uint32_t *)0x40036008 // Counter Register #define PDB0_IDLY *(volatile uint32_t *)0x4003600C // Interrupt Delay Register @@ -986,48 +986,48 @@ // Chapter 35: FlexTimer Module (FTM) #define FTM0_SC *(volatile uint32_t *)0x40038000 // Status And Control -#define FTM_SC_TOF 0x80 // Timer Overflow Flag -#define FTM_SC_TOIE 0x40 // Timer Overflow Interrupt Enable -#define FTM_SC_CPWMS 0x20 // Center-Aligned PWM Select -#define FTM_SC_CLKS(n) (((n) & 3) << 3) // Clock Source Selection -#define FTM_SC_PS(n) (((n) & 7) << 0) // Prescale Factor Selection +#define FTM_SC_TOF 0x80 // Timer Overflow Flag +#define FTM_SC_TOIE 0x40 // Timer Overflow Interrupt Enable +#define FTM_SC_CPWMS 0x20 // Center-Aligned PWM Select +#define FTM_SC_CLKS(n) (((n) & 3) << 3) // Clock Source Selection +#define FTM_SC_PS(n) (((n) & 7) << 0) // Prescale Factor Selection #define FTM0_CNT *(volatile uint32_t *)0x40038004 // Counter #define FTM0_MOD *(volatile uint32_t *)0x40038008 // Modulo -#define FTM0_C0SC *(volatile uint32_t *)0x4003800C // Channel 0 Status And Control -#define FTM0_C0V *(volatile uint32_t *)0x40038010 // Channel 0 Value -#define FTM0_C1SC *(volatile uint32_t *)0x40038014 // Channel 1 Status And Control -#define FTM0_C1V *(volatile uint32_t *)0x40038018 // Channel 1 Value -#define FTM0_C2SC *(volatile uint32_t *)0x4003801C // Channel 2 Status And Control -#define FTM0_C2V *(volatile uint32_t *)0x40038020 // Channel 2 Value -#define FTM0_C3SC *(volatile uint32_t *)0x40038024 // Channel 3 Status And Control -#define FTM0_C3V *(volatile uint32_t *)0x40038028 // Channel 3 Value -#define FTM0_C4SC *(volatile uint32_t *)0x4003802C // Channel 4 Status And Control -#define FTM0_C4V *(volatile uint32_t *)0x40038030 // Channel 4 Value -#define FTM0_C5SC *(volatile uint32_t *)0x40038034 // Channel 5 Status And Control -#define FTM0_C5V *(volatile uint32_t *)0x40038038 // Channel 5 Value -#define FTM0_C6SC *(volatile uint32_t *)0x4003803C // Channel 6 Status And Control -#define FTM0_C6V *(volatile uint32_t *)0x40038040 // Channel 6 Value -#define FTM0_C7SC *(volatile uint32_t *)0x40038044 // Channel 7 Status And Control -#define FTM0_C7V *(volatile uint32_t *)0x40038048 // Channel 7 Value +#define FTM0_C0SC *(volatile uint32_t *)0x4003800C // Channel 0 Status And Control +#define FTM0_C0V *(volatile uint32_t *)0x40038010 // Channel 0 Value +#define FTM0_C1SC *(volatile uint32_t *)0x40038014 // Channel 1 Status And Control +#define FTM0_C1V *(volatile uint32_t *)0x40038018 // Channel 1 Value +#define FTM0_C2SC *(volatile uint32_t *)0x4003801C // Channel 2 Status And Control +#define FTM0_C2V *(volatile uint32_t *)0x40038020 // Channel 2 Value +#define FTM0_C3SC *(volatile uint32_t *)0x40038024 // Channel 3 Status And Control +#define FTM0_C3V *(volatile uint32_t *)0x40038028 // Channel 3 Value +#define FTM0_C4SC *(volatile uint32_t *)0x4003802C // Channel 4 Status And Control +#define FTM0_C4V *(volatile uint32_t *)0x40038030 // Channel 4 Value +#define FTM0_C5SC *(volatile uint32_t *)0x40038034 // Channel 5 Status And Control +#define FTM0_C5V *(volatile uint32_t *)0x40038038 // Channel 5 Value +#define FTM0_C6SC *(volatile uint32_t *)0x4003803C // Channel 6 Status And Control +#define FTM0_C6V *(volatile uint32_t *)0x40038040 // Channel 6 Value +#define FTM0_C7SC *(volatile uint32_t *)0x40038044 // Channel 7 Status And Control +#define FTM0_C7V *(volatile uint32_t *)0x40038048 // Channel 7 Value #define FTM0_CNTIN *(volatile uint32_t *)0x4003804C // Counter Initial Value #define FTM0_STATUS *(volatile uint32_t *)0x40038050 // Capture And Compare Status #define FTM0_MODE *(volatile uint32_t *)0x40038054 // Features Mode Selection -#define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable -#define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode -#define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable -#define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode -#define FTM_MODE_WPDIS 0x04 // Write Protection Disable -#define FTM_MODE_INIT 0x02 // Initialize The Channels Output -#define FTM_MODE_FTMEN 0x01 // FTM Enable +#define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable +#define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode +#define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable +#define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode +#define FTM_MODE_WPDIS 0x04 // Write Protection Disable +#define FTM_MODE_INIT 0x02 // Initialize The Channels Output +#define FTM_MODE_FTMEN 0x01 // FTM Enable #define FTM0_SYNC *(volatile uint32_t *)0x40038058 // Synchronization -#define FTM_SYNC_SWSYNC 0x80 // -#define FTM_SYNC_TRIG2 0x40 // -#define FTM_SYNC_TRIG1 0x20 // -#define FTM_SYNC_TRIG0 0x10 // -#define FTM_SYNC_SYNCHOM 0x08 // -#define FTM_SYNC_REINIT 0x04 // -#define FTM_SYNC_CNTMAX 0x02 // -#define FTM_SYNC_CNTMIN 0x01 // +#define FTM_SYNC_SWSYNC 0x80 // +#define FTM_SYNC_TRIG2 0x40 // +#define FTM_SYNC_TRIG1 0x20 // +#define FTM_SYNC_TRIG0 0x10 // +#define FTM_SYNC_SYNCHOM 0x08 // +#define FTM_SYNC_REINIT 0x04 // +#define FTM_SYNC_CNTMAX 0x02 // +#define FTM_SYNC_CNTMIN 0x01 // #define FTM0_OUTINIT *(volatile uint32_t *)0x4003805C // Initial State For Channels Output #define FTM0_OUTMASK *(volatile uint32_t *)0x40038060 // Output Mask #define FTM0_COMBINE *(volatile uint32_t *)0x40038064 // Function For Linked Channels @@ -1047,57 +1047,57 @@ #define FTM1_SC *(volatile uint32_t *)0x40039000 // Status And Control #define FTM1_CNT *(volatile uint32_t *)0x40039004 // Counter #define FTM1_MOD *(volatile uint32_t *)0x40039008 // Modulo -#define FTM1_C0SC *(volatile uint32_t *)0x4003900C // Channel 0 Status And Control -#define FTM1_C0V *(volatile uint32_t *)0x40039010 // Channel 0 Value -#define FTM1_C1SC *(volatile uint32_t *)0x40039014 // Channel 1 Status And Control -#define FTM1_C1V *(volatile uint32_t *)0x40039018 // Channel 1 Value -#define FTM1_CNTIN *(volatile uint32_t *)0x4003904C // Counter Initial Value -#define FTM1_STATUS *(volatile uint32_t *)0x40039050 // Capture And Compare Status -#define FTM1_MODE *(volatile uint32_t *)0x40039054 // Features Mode Selection -#define FTM1_SYNC *(volatile uint32_t *)0x40039058 // Synchronization -#define FTM1_OUTINIT *(volatile uint32_t *)0x4003905C // Initial State For Channels Output -#define FTM1_OUTMASK *(volatile uint32_t *)0x40039060 // Output Mask -#define FTM1_COMBINE *(volatile uint32_t *)0x40039064 // Function For Linked Channels -#define FTM1_DEADTIME *(volatile uint32_t *)0x40039068 // Deadtime Insertion Control -#define FTM1_EXTTRIG *(volatile uint32_t *)0x4003906C // FTM External Trigger -#define FTM1_POL *(volatile uint32_t *)0x40039070 // Channels Polarity -#define FTM1_FMS *(volatile uint32_t *)0x40039074 // Fault Mode Status -#define FTM1_FILTER *(volatile uint32_t *)0x40039078 // Input Capture Filter Control -#define FTM1_FLTCTRL *(volatile uint32_t *)0x4003907C // Fault Control -#define FTM1_QDCTRL *(volatile uint32_t *)0x40039080 // Quadrature Decoder Control And Status -#define FTM1_CONF *(volatile uint32_t *)0x40039084 // Configuration -#define FTM1_FLTPOL *(volatile uint32_t *)0x40039088 // FTM Fault Input Polarity -#define FTM1_SYNCONF *(volatile uint32_t *)0x4003908C // Synchronization Configuration -#define FTM1_INVCTRL *(volatile uint32_t *)0x40039090 // FTM Inverting Control -#define FTM1_SWOCTRL *(volatile uint32_t *)0x40039094 // FTM Software Output Control -#define FTM1_PWMLOAD *(volatile uint32_t *)0x40039098 // FTM PWM Load -#define FTM2_SC *(volatile uint32_t *)0x400B8000 // Status And Control -#define FTM2_CNT *(volatile uint32_t *)0x400B8004 // Counter -#define FTM2_MOD *(volatile uint32_t *)0x400B8008 // Modulo -#define FTM2_C0SC *(volatile uint32_t *)0x400B800C // Channel 0 Status And Control -#define FTM2_C0V *(volatile uint32_t *)0x400B8010 // Channel 0 Value -#define FTM2_C1SC *(volatile uint32_t *)0x400B8014 // Channel 1 Status And Control -#define FTM2_C1V *(volatile uint32_t *)0x400B8018 // Channel 1 Value -#define FTM2_CNTIN *(volatile uint32_t *)0x400B804C // Counter Initial Value -#define FTM2_STATUS *(volatile uint32_t *)0x400B8050 // Capture And Compare Status -#define FTM2_MODE *(volatile uint32_t *)0x400B8054 // Features Mode Selection -#define FTM2_SYNC *(volatile uint32_t *)0x400B8058 // Synchronization -#define FTM2_OUTINIT *(volatile uint32_t *)0x400B805C // Initial State For Channels Output -#define FTM2_OUTMASK *(volatile uint32_t *)0x400B8060 // Output Mask -#define FTM2_COMBINE *(volatile uint32_t *)0x400B8064 // Function For Linked Channels -#define FTM2_DEADTIME *(volatile uint32_t *)0x400B8068 // Deadtime Insertion Control -#define FTM2_EXTTRIG *(volatile uint32_t *)0x400B806C // FTM External Trigger -#define FTM2_POL *(volatile uint32_t *)0x400B8070 // Channels Polarity -#define FTM2_FMS *(volatile uint32_t *)0x400B8074 // Fault Mode Status -#define FTM2_FILTER *(volatile uint32_t *)0x400B8078 // Input Capture Filter Control -#define FTM2_FLTCTRL *(volatile uint32_t *)0x400B807C // Fault Control -#define FTM2_QDCTRL *(volatile uint32_t *)0x400B8080 // Quadrature Decoder Control And Status -#define FTM2_CONF *(volatile uint32_t *)0x400B8084 // Configuration -#define FTM2_FLTPOL *(volatile uint32_t *)0x400B8088 // FTM Fault Input Polarity -#define FTM2_SYNCONF *(volatile uint32_t *)0x400B808C // Synchronization Configuration -#define FTM2_INVCTRL *(volatile uint32_t *)0x400B8090 // FTM Inverting Control -#define FTM2_SWOCTRL *(volatile uint32_t *)0x400B8094 // FTM Software Output Control -#define FTM2_PWMLOAD *(volatile uint32_t *)0x400B8098 // FTM PWM Load +#define FTM1_C0SC *(volatile uint32_t *)0x4003900C // Channel 0 Status And Control +#define FTM1_C0V *(volatile uint32_t *)0x40039010 // Channel 0 Value +#define FTM1_C1SC *(volatile uint32_t *)0x40039014 // Channel 1 Status And Control +#define FTM1_C1V *(volatile uint32_t *)0x40039018 // Channel 1 Value +#define FTM1_CNTIN *(volatile uint32_t *)0x4003904C // Counter Initial Value +#define FTM1_STATUS *(volatile uint32_t *)0x40039050 // Capture And Compare Status +#define FTM1_MODE *(volatile uint32_t *)0x40039054 // Features Mode Selection +#define FTM1_SYNC *(volatile uint32_t *)0x40039058 // Synchronization +#define FTM1_OUTINIT *(volatile uint32_t *)0x4003905C // Initial State For Channels Output +#define FTM1_OUTMASK *(volatile uint32_t *)0x40039060 // Output Mask +#define FTM1_COMBINE *(volatile uint32_t *)0x40039064 // Function For Linked Channels +#define FTM1_DEADTIME *(volatile uint32_t *)0x40039068 // Deadtime Insertion Control +#define FTM1_EXTTRIG *(volatile uint32_t *)0x4003906C // FTM External Trigger +#define FTM1_POL *(volatile uint32_t *)0x40039070 // Channels Polarity +#define FTM1_FMS *(volatile uint32_t *)0x40039074 // Fault Mode Status +#define FTM1_FILTER *(volatile uint32_t *)0x40039078 // Input Capture Filter Control +#define FTM1_FLTCTRL *(volatile uint32_t *)0x4003907C // Fault Control +#define FTM1_QDCTRL *(volatile uint32_t *)0x40039080 // Quadrature Decoder Control And Status +#define FTM1_CONF *(volatile uint32_t *)0x40039084 // Configuration +#define FTM1_FLTPOL *(volatile uint32_t *)0x40039088 // FTM Fault Input Polarity +#define FTM1_SYNCONF *(volatile uint32_t *)0x4003908C // Synchronization Configuration +#define FTM1_INVCTRL *(volatile uint32_t *)0x40039090 // FTM Inverting Control +#define FTM1_SWOCTRL *(volatile uint32_t *)0x40039094 // FTM Software Output Control +#define FTM1_PWMLOAD *(volatile uint32_t *)0x40039098 // FTM PWM Load +#define FTM2_SC *(volatile uint32_t *)0x400B8000 // Status And Control +#define FTM2_CNT *(volatile uint32_t *)0x400B8004 // Counter +#define FTM2_MOD *(volatile uint32_t *)0x400B8008 // Modulo +#define FTM2_C0SC *(volatile uint32_t *)0x400B800C // Channel 0 Status And Control +#define FTM2_C0V *(volatile uint32_t *)0x400B8010 // Channel 0 Value +#define FTM2_C1SC *(volatile uint32_t *)0x400B8014 // Channel 1 Status And Control +#define FTM2_C1V *(volatile uint32_t *)0x400B8018 // Channel 1 Value +#define FTM2_CNTIN *(volatile uint32_t *)0x400B804C // Counter Initial Value +#define FTM2_STATUS *(volatile uint32_t *)0x400B8050 // Capture And Compare Status +#define FTM2_MODE *(volatile uint32_t *)0x400B8054 // Features Mode Selection +#define FTM2_SYNC *(volatile uint32_t *)0x400B8058 // Synchronization +#define FTM2_OUTINIT *(volatile uint32_t *)0x400B805C // Initial State For Channels Output +#define FTM2_OUTMASK *(volatile uint32_t *)0x400B8060 // Output Mask +#define FTM2_COMBINE *(volatile uint32_t *)0x400B8064 // Function For Linked Channels +#define FTM2_DEADTIME *(volatile uint32_t *)0x400B8068 // Deadtime Insertion Control +#define FTM2_EXTTRIG *(volatile uint32_t *)0x400B806C // FTM External Trigger +#define FTM2_POL *(volatile uint32_t *)0x400B8070 // Channels Polarity +#define FTM2_FMS *(volatile uint32_t *)0x400B8074 // Fault Mode Status +#define FTM2_FILTER *(volatile uint32_t *)0x400B8078 // Input Capture Filter Control +#define FTM2_FLTCTRL *(volatile uint32_t *)0x400B807C // Fault Control +#define FTM2_QDCTRL *(volatile uint32_t *)0x400B8080 // Quadrature Decoder Control And Status +#define FTM2_CONF *(volatile uint32_t *)0x400B8084 // Configuration +#define FTM2_FLTPOL *(volatile uint32_t *)0x400B8088 // FTM Fault Input Polarity +#define FTM2_SYNCONF *(volatile uint32_t *)0x400B808C // Synchronization Configuration +#define FTM2_INVCTRL *(volatile uint32_t *)0x400B8090 // FTM Inverting Control +#define FTM2_SWOCTRL *(volatile uint32_t *)0x400B8094 // FTM Software Output Control +#define FTM2_PWMLOAD *(volatile uint32_t *)0x400B8098 // FTM PWM Load // Chapter 36: Periodic Interrupt Timer (PIT) #define PIT_MCR *(volatile uint32_t *)0x40037000 // PIT Module Control Register @@ -1143,26 +1143,26 @@ #define RTC_TPR *(volatile uint32_t *)0x4003D004 // RTC Time Prescaler Register #define RTC_TAR *(volatile uint32_t *)0x4003D008 // RTC Time Alarm Register #define RTC_TCR *(volatile uint32_t *)0x4003D00C // RTC Time Compensation Register -#define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter -#define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value -#define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register -#define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register +#define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter +#define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value +#define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register +#define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register #define RTC_CR *(volatile uint32_t *)0x4003D010 // RTC Control Register -#define RTC_CR_SC2P (uint32_t)0x00002000 // -#define RTC_CR_SC4P (uint32_t)0x00001000 // -#define RTC_CR_SC8P (uint32_t)0x00000800 // -#define RTC_CR_SC16P (uint32_t)0x00000400 // -#define RTC_CR_CLKO (uint32_t)0x00000200 // -#define RTC_CR_OSCE (uint32_t)0x00000100 // -#define RTC_CR_UM (uint32_t)0x00000008 // -#define RTC_CR_SUP (uint32_t)0x00000004 // -#define RTC_CR_WPE (uint32_t)0x00000002 // -#define RTC_CR_SWR (uint32_t)0x00000001 // +#define RTC_CR_SC2P (uint32_t)0x00002000 // +#define RTC_CR_SC4P (uint32_t)0x00001000 // +#define RTC_CR_SC8P (uint32_t)0x00000800 // +#define RTC_CR_SC16P (uint32_t)0x00000400 // +#define RTC_CR_CLKO (uint32_t)0x00000200 // +#define RTC_CR_OSCE (uint32_t)0x00000100 // +#define RTC_CR_UM (uint32_t)0x00000008 // +#define RTC_CR_SUP (uint32_t)0x00000004 // +#define RTC_CR_WPE (uint32_t)0x00000002 // +#define RTC_CR_SWR (uint32_t)0x00000001 // #define RTC_SR *(volatile uint32_t *)0x4003D014 // RTC Status Register -#define RTC_SR_TCE (uint32_t)0x00000010 // -#define RTC_SR_TAF (uint32_t)0x00000004 // -#define RTC_SR_TOF (uint32_t)0x00000002 // -#define RTC_SR_TIF (uint32_t)0x00000001 // +#define RTC_SR_TCE (uint32_t)0x00000010 // +#define RTC_SR_TAF (uint32_t)0x00000004 // +#define RTC_SR_TOF (uint32_t)0x00000002 // +#define RTC_SR_TIF (uint32_t)0x00000001 // #define RTC_LR *(volatile uint32_t *)0x4003D018 // RTC Lock Register #define RTC_IER *(volatile uint32_t *)0x4003D01C // RTC Interrupt Enable Register #define RTC_WAR *(volatile uint32_t *)0x4003D800 // RTC Write Access Register @@ -1174,78 +1174,78 @@ #define USB0_REV *(const uint8_t *)0x40072008 // Peripheral Revision register #define USB0_ADDINFO *(volatile uint8_t *)0x4007200C // Peripheral Additional Info register #define USB0_OTGISTAT *(volatile uint8_t *)0x40072010 // OTG Interrupt Status register -#define USB_OTGISTAT_IDCHG (uint8_t)0x80 // -#define USB_OTGISTAT_ONEMSEC (uint8_t)0x40 // -#define USB_OTGISTAT_LINE_STATE_CHG (uint8_t)0x20 // -#define USB_OTGISTAT_SESSVLDCHG (uint8_t)0x08 // -#define USB_OTGISTAT_B_SESS_CHG (uint8_t)0x04 // -#define USB_OTGISTAT_AVBUSCHG (uint8_t)0x01 // +#define USB_OTGISTAT_IDCHG (uint8_t)0x80 // +#define USB_OTGISTAT_ONEMSEC (uint8_t)0x40 // +#define USB_OTGISTAT_LINE_STATE_CHG (uint8_t)0x20 // +#define USB_OTGISTAT_SESSVLDCHG (uint8_t)0x08 // +#define USB_OTGISTAT_B_SESS_CHG (uint8_t)0x04 // +#define USB_OTGISTAT_AVBUSCHG (uint8_t)0x01 // #define USB0_OTGICR *(volatile uint8_t *)0x40072014 // OTG Interrupt Control Register -#define USB_OTGICR_IDEN (uint8_t)0x80 // -#define USB_OTGICR_ONEMSECEN (uint8_t)0x40 // -#define USB_OTGICR_LINESTATEEN (uint8_t)0x20 // -#define USB_OTGICR_SESSVLDEN (uint8_t)0x08 // -#define USB_OTGICR_BSESSEN (uint8_t)0x04 // -#define USB_OTGICR_AVBUSEN (uint8_t)0x01 // +#define USB_OTGICR_IDEN (uint8_t)0x80 // +#define USB_OTGICR_ONEMSECEN (uint8_t)0x40 // +#define USB_OTGICR_LINESTATEEN (uint8_t)0x20 // +#define USB_OTGICR_SESSVLDEN (uint8_t)0x08 // +#define USB_OTGICR_BSESSEN (uint8_t)0x04 // +#define USB_OTGICR_AVBUSEN (uint8_t)0x01 // #define USB0_OTGSTAT *(volatile uint8_t *)0x40072018 // OTG Status register -#define USB_OTGSTAT_ID (uint8_t)0x80 // -#define USB_OTGSTAT_ONEMSECEN (uint8_t)0x40 // -#define USB_OTGSTAT_LINESTATESTABLE (uint8_t)0x20 // -#define USB_OTGSTAT_SESS_VLD (uint8_t)0x08 // -#define USB_OTGSTAT_BSESSEND (uint8_t)0x04 // -#define USB_OTGSTAT_AVBUSVLD (uint8_t)0x01 // +#define USB_OTGSTAT_ID (uint8_t)0x80 // +#define USB_OTGSTAT_ONEMSECEN (uint8_t)0x40 // +#define USB_OTGSTAT_LINESTATESTABLE (uint8_t)0x20 // +#define USB_OTGSTAT_SESS_VLD (uint8_t)0x08 // +#define USB_OTGSTAT_BSESSEND (uint8_t)0x04 // +#define USB_OTGSTAT_AVBUSVLD (uint8_t)0x01 // #define USB0_OTGCTL *(volatile uint8_t *)0x4007201C // OTG Control Register -#define USB_OTGCTL_DPHIGH (uint8_t)0x80 // -#define USB_OTGCTL_DPLOW (uint8_t)0x20 // -#define USB_OTGCTL_DMLOW (uint8_t)0x10 // -#define USB_OTGCTL_OTGEN (uint8_t)0x04 // +#define USB_OTGCTL_DPHIGH (uint8_t)0x80 // +#define USB_OTGCTL_DPLOW (uint8_t)0x20 // +#define USB_OTGCTL_DMLOW (uint8_t)0x10 // +#define USB_OTGCTL_OTGEN (uint8_t)0x04 // #define USB0_ISTAT *(volatile uint8_t *)0x40072080 // Interrupt Status Register -#define USB_ISTAT_STALL (uint8_t)0x80 // -#define USB_ISTAT_ATTACH (uint8_t)0x40 // -#define USB_ISTAT_RESUME (uint8_t)0x20 // -#define USB_ISTAT_SLEEP (uint8_t)0x10 // -#define USB_ISTAT_TOKDNE (uint8_t)0x08 // -#define USB_ISTAT_SOFTOK (uint8_t)0x04 // -#define USB_ISTAT_ERROR (uint8_t)0x02 // -#define USB_ISTAT_USBRST (uint8_t)0x01 // +#define USB_ISTAT_STALL (uint8_t)0x80 // +#define USB_ISTAT_ATTACH (uint8_t)0x40 // +#define USB_ISTAT_RESUME (uint8_t)0x20 // +#define USB_ISTAT_SLEEP (uint8_t)0x10 // +#define USB_ISTAT_TOKDNE (uint8_t)0x08 // +#define USB_ISTAT_SOFTOK (uint8_t)0x04 // +#define USB_ISTAT_ERROR (uint8_t)0x02 // +#define USB_ISTAT_USBRST (uint8_t)0x01 // #define USB0_INTEN *(volatile uint8_t *)0x40072084 // Interrupt Enable Register -#define USB_INTEN_STALLEN (uint8_t)0x80 // -#define USB_INTEN_ATTACHEN (uint8_t)0x40 // -#define USB_INTEN_RESUMEEN (uint8_t)0x20 // -#define USB_INTEN_SLEEPEN (uint8_t)0x10 // -#define USB_INTEN_TOKDNEEN (uint8_t)0x08 // -#define USB_INTEN_SOFTOKEN (uint8_t)0x04 // -#define USB_INTEN_ERROREN (uint8_t)0x02 // -#define USB_INTEN_USBRSTEN (uint8_t)0x01 // +#define USB_INTEN_STALLEN (uint8_t)0x80 // +#define USB_INTEN_ATTACHEN (uint8_t)0x40 // +#define USB_INTEN_RESUMEEN (uint8_t)0x20 // +#define USB_INTEN_SLEEPEN (uint8_t)0x10 // +#define USB_INTEN_TOKDNEEN (uint8_t)0x08 // +#define USB_INTEN_SOFTOKEN (uint8_t)0x04 // +#define USB_INTEN_ERROREN (uint8_t)0x02 // +#define USB_INTEN_USBRSTEN (uint8_t)0x01 // #define USB0_ERRSTAT *(volatile uint8_t *)0x40072088 // Error Interrupt Status Register -#define USB_ERRSTAT_BTSERR (uint8_t)0x80 // -#define USB_ERRSTAT_DMAERR (uint8_t)0x20 // -#define USB_ERRSTAT_BTOERR (uint8_t)0x10 // -#define USB_ERRSTAT_DFN8 (uint8_t)0x08 // -#define USB_ERRSTAT_CRC16 (uint8_t)0x04 // -#define USB_ERRSTAT_CRC5EOF (uint8_t)0x02 // -#define USB_ERRSTAT_PIDERR (uint8_t)0x01 // +#define USB_ERRSTAT_BTSERR (uint8_t)0x80 // +#define USB_ERRSTAT_DMAERR (uint8_t)0x20 // +#define USB_ERRSTAT_BTOERR (uint8_t)0x10 // +#define USB_ERRSTAT_DFN8 (uint8_t)0x08 // +#define USB_ERRSTAT_CRC16 (uint8_t)0x04 // +#define USB_ERRSTAT_CRC5EOF (uint8_t)0x02 // +#define USB_ERRSTAT_PIDERR (uint8_t)0x01 // #define USB0_ERREN *(volatile uint8_t *)0x4007208C // Error Interrupt Enable Register -#define USB_ERREN_BTSERREN (uint8_t)0x80 // -#define USB_ERREN_DMAERREN (uint8_t)0x20 // -#define USB_ERREN_BTOERREN (uint8_t)0x10 // -#define USB_ERREN_DFN8EN (uint8_t)0x08 // -#define USB_ERREN_CRC16EN (uint8_t)0x04 // -#define USB_ERREN_CRC5EOFEN (uint8_t)0x02 // -#define USB_ERREN_PIDERREN (uint8_t)0x01 // +#define USB_ERREN_BTSERREN (uint8_t)0x80 // +#define USB_ERREN_DMAERREN (uint8_t)0x20 // +#define USB_ERREN_BTOERREN (uint8_t)0x10 // +#define USB_ERREN_DFN8EN (uint8_t)0x08 // +#define USB_ERREN_CRC16EN (uint8_t)0x04 // +#define USB_ERREN_CRC5EOFEN (uint8_t)0x02 // +#define USB_ERREN_PIDERREN (uint8_t)0x01 // #define USB0_STAT *(volatile uint8_t *)0x40072090 // Status Register -#define USB_STAT_TX (uint8_t)0x08 // -#define USB_STAT_ODD (uint8_t)0x04 // -#define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) // +#define USB_STAT_TX (uint8_t)0x08 // +#define USB_STAT_ODD (uint8_t)0x04 // +#define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) // #define USB0_CTL *(volatile uint8_t *)0x40072094 // Control Register -#define USB_CTL_JSTATE (uint8_t)0x80 // -#define USB_CTL_SE0 (uint8_t)0x40 // -#define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 // -#define USB_CTL_RESET (uint8_t)0x10 // -#define USB_CTL_HOSTMODEEN (uint8_t)0x08 // -#define USB_CTL_RESUME (uint8_t)0x04 // -#define USB_CTL_ODDRST (uint8_t)0x02 // -#define USB_CTL_USBENSOFEN (uint8_t)0x01 // +#define USB_CTL_JSTATE (uint8_t)0x80 // +#define USB_CTL_SE0 (uint8_t)0x40 // +#define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 // +#define USB_CTL_RESET (uint8_t)0x10 // +#define USB_CTL_HOSTMODEEN (uint8_t)0x08 // +#define USB_CTL_RESUME (uint8_t)0x04 // +#define USB_CTL_ODDRST (uint8_t)0x02 // +#define USB_CTL_USBENSOFEN (uint8_t)0x01 // #define USB0_ADDR *(volatile uint8_t *)0x40072098 // Address Register #define USB0_BDTPAGE1 *(volatile uint8_t *)0x4007209C // BDT Page Register 1 #define USB0_FRMNUML *(volatile uint8_t *)0x400720A0 // Frame Number Register Low @@ -1255,13 +1255,13 @@ #define USB0_BDTPAGE2 *(volatile uint8_t *)0x400720B0 // BDT Page Register 2 #define USB0_BDTPAGE3 *(volatile uint8_t *)0x400720B4 // BDT Page Register 3 #define USB0_ENDPT0 *(volatile uint8_t *)0x400720C0 // Endpoint Control Register -#define USB_ENDPT_HOSTWOHUB (uint8_t)0x80 // host only, enable low speed -#define USB_ENDPT_RETRYDIS (uint8_t)0x40 // host only, set to disable NAK retry -#define USB_ENDPT_EPCTLDIS (uint8_t)0x10 // 0=control, 1=bulk, interrupt, isync -#define USB_ENDPT_EPRXEN (uint8_t)0x08 // enables the endpoint for RX transfers. -#define USB_ENDPT_EPTXEN (uint8_t)0x04 // enables the endpoint for TX transfers. -#define USB_ENDPT_EPSTALL (uint8_t)0x02 // set to stall endpoint -#define USB_ENDPT_EPHSHK (uint8_t)0x01 // enable handshaking during a transaction, generally set unless Isochronous +#define USB_ENDPT_HOSTWOHUB (uint8_t)0x80 // host only, enable low speed +#define USB_ENDPT_RETRYDIS (uint8_t)0x40 // host only, set to disable NAK retry +#define USB_ENDPT_EPCTLDIS (uint8_t)0x10 // 0=control, 1=bulk, interrupt, isync +#define USB_ENDPT_EPRXEN (uint8_t)0x08 // enables the endpoint for RX transfers. +#define USB_ENDPT_EPTXEN (uint8_t)0x04 // enables the endpoint for TX transfers. +#define USB_ENDPT_EPSTALL (uint8_t)0x02 // set to stall endpoint +#define USB_ENDPT_EPHSHK (uint8_t)0x01 // enable handshaking during a transaction, generally set unless Isochronous #define USB0_ENDPT1 *(volatile uint8_t *)0x400720C4 // Endpoint Control Register #define USB0_ENDPT2 *(volatile uint8_t *)0x400720C8 // Endpoint Control Register #define USB0_ENDPT3 *(volatile uint8_t *)0x400720CC // Endpoint Control Register @@ -1278,19 +1278,19 @@ #define USB0_ENDPT14 *(volatile uint8_t *)0x400720F8 // Endpoint Control Register #define USB0_ENDPT15 *(volatile uint8_t *)0x400720FC // Endpoint Control Register #define USB0_USBCTRL *(volatile uint8_t *)0x40072100 // USB Control Register -#define USB_USBCTRL_SUSP (uint8_t)0x80 // Places the USB transceiver into the suspend state. -#define USB_USBCTRL_PDE (uint8_t)0x40 // Enables the weak pulldowns on the USB transceiver. +#define USB_USBCTRL_SUSP (uint8_t)0x80 // Places the USB transceiver into the suspend state. +#define USB_USBCTRL_PDE (uint8_t)0x40 // Enables the weak pulldowns on the USB transceiver. #define USB0_OBSERVE *(volatile uint8_t *)0x40072104 // USB OTG Observe Register -#define USB_OBSERVE_DPPU (uint8_t)0x80 // -#define USB_OBSERVE_DPPD (uint8_t)0x40 // -#define USB_OBSERVE_DMPD (uint8_t)0x10 // +#define USB_OBSERVE_DPPU (uint8_t)0x80 // +#define USB_OBSERVE_DPPD (uint8_t)0x40 // +#define USB_OBSERVE_DMPD (uint8_t)0x10 // #define USB0_CONTROL *(volatile uint8_t *)0x40072108 // USB OTG Control Register -#define USB_CONTROL_DPPULLUPNONOTG (uint8_t)0x10 // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode. +#define USB_CONTROL_DPPULLUPNONOTG (uint8_t)0x10 // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode. #define USB0_USBTRC0 *(volatile uint8_t *)0x4007210C // USB Transceiver Control Register 0 -#define USB_USBTRC_USBRESET (uint8_t)0x80 // -#define USB_USBTRC_USBRESMEN (uint8_t)0x20 // -#define USB_USBTRC_SYNC_DET (uint8_t)0x02 // -#define USB_USBTRC_USB_RESUME_INT (uint8_t)0x01 // +#define USB_USBTRC_USBRESET (uint8_t)0x80 // +#define USB_USBTRC_USBRESMEN (uint8_t)0x20 // +#define USB_USBTRC_SYNC_DET (uint8_t)0x02 // +#define USB_USBTRC_USB_RESUME_INT (uint8_t)0x01 // #define USB0_USBFRMADJUST *(volatile uint8_t *)0x40072114 // Frame Adjust Register // Chapter 41: USB Device Charger Detection Module (USBDCD) @@ -1303,121 +1303,121 @@ // Chapter 43: SPI (DSPI) #define SPI0_MCR *(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register -#define SPI_MCR_MSTR (uint32_t)0x80000000 // Master/Slave Mode Select -#define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 // -#define SPI_MCR_DCONF(n) (((n) & 3) << 28) // -#define SPI_MCR_FRZ (uint32_t)0x08000000 // -#define SPI_MCR_MTFE (uint32_t)0x04000000 // -#define SPI_MCR_ROOE (uint32_t)0x01000000 // -#define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) // -#define SPI_MCR_DOZE (uint32_t)0x00008000 // -#define SPI_MCR_MDIS (uint32_t)0x00004000 // -#define SPI_MCR_DIS_TXF (uint32_t)0x00002000 // -#define SPI_MCR_DIS_RXF (uint32_t)0x00001000 // -#define SPI_MCR_CLR_TXF (uint32_t)0x00000800 // -#define SPI_MCR_CLR_RXF (uint32_t)0x00000400 // -#define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) // -#define SPI_MCR_HALT (uint32_t)0x00000001 // +#define SPI_MCR_MSTR (uint32_t)0x80000000 // Master/Slave Mode Select +#define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 // +#define SPI_MCR_DCONF(n) (((n) & 3) << 28) // +#define SPI_MCR_FRZ (uint32_t)0x08000000 // +#define SPI_MCR_MTFE (uint32_t)0x04000000 // +#define SPI_MCR_ROOE (uint32_t)0x01000000 // +#define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) // +#define SPI_MCR_DOZE (uint32_t)0x00008000 // +#define SPI_MCR_MDIS (uint32_t)0x00004000 // +#define SPI_MCR_DIS_TXF (uint32_t)0x00002000 // +#define SPI_MCR_DIS_RXF (uint32_t)0x00001000 // +#define SPI_MCR_CLR_TXF (uint32_t)0x00000800 // +#define SPI_MCR_CLR_RXF (uint32_t)0x00000400 // +#define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) // +#define SPI_MCR_HALT (uint32_t)0x00000001 // #define SPI0_TCR *(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register #define SPI0_CTAR0 *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode -#define SPI_CTAR_DBR (uint32_t)0x80000000 // Double Baud Rate -#define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1) -#define SPI_CTAR_CPOL (uint32_t)0x04000000 // Clock Polarity -#define SPI_CTAR_CPHA (uint32_t)0x02000000 // Clock Phase -#define SPI_CTAR_LSBFE (uint32_t)0x01000000 // LSB First -#define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler -#define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler -#define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler -#define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler -#define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler -#define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler -#define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler -#define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler +#define SPI_CTAR_DBR (uint32_t)0x80000000 // Double Baud Rate +#define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1) +#define SPI_CTAR_CPOL (uint32_t)0x04000000 // Clock Polarity +#define SPI_CTAR_CPHA (uint32_t)0x02000000 // Clock Phase +#define SPI_CTAR_LSBFE (uint32_t)0x01000000 // LSB First +#define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler +#define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler +#define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler +#define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler +#define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler +#define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler +#define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler +#define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler #define SPI0_CTAR0_SLAVE *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode #define SPI0_CTAR1 *(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode #define SPI0_SR *(volatile uint32_t *)0x4002C02C // DSPI Status Register -#define SPI_SR_TCF (uint32_t)0x80000000 // Transfer Complete Flag -#define SPI_SR_TXRXS (uint32_t)0x40000000 // TX and RX Status -#define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag -#define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag -#define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag -#define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag -#define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag -#define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register -#define SPI_RSER_TCF_RE (uint32_t)0x80000000 // Transmission Complete Request Enable -#define SPI_RSER_EOQF_RE (uint32_t)0x10000000 // DSPI Finished Request Request Enable -#define SPI_RSER_TFUF_RE (uint32_t)0x08000000 // Transmit FIFO Underflow Request Enable -#define SPI_RSER_TFFF_RE (uint32_t)0x02000000 // Transmit FIFO Fill Request Enable -#define SPI_RSER_TFFF_DIRS (uint32_t)0x01000000 // Transmit FIFO FIll Dma or Interrupt Request Select -#define SPI_RSER_RFOF_RE (uint32_t)0x00080000 // Receive FIFO Overflow Request Enable -#define SPI_RSER_RFDF_RE (uint32_t)0x00020000 // Receive FIFO Drain Request Enable -#define SPI_RSER_RFDF_DIRS (uint32_t)0x00010000 // Receive FIFO Drain DMA or Interrupt Request Select -#define SPI0_PUSHR *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode -#define SPI_PUSHR_CONT (uint32_t)0x80000000 // -#define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) // -#define SPI_PUSHR_EOQ (uint32_t)0x08000000 // -#define SPI_PUSHR_CTCNT (uint32_t)0x04000000 // -#define SPI_PUSHR_PCS(n) (((n) & 31) << 16) // -#define SPI0_PUSHR_SLAVE *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode -#define SPI0_POPR *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register -#define SPI0_TXFR0 *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers -#define SPI0_TXFR1 *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers -#define SPI0_TXFR2 *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers -#define SPI0_TXFR3 *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers -#define SPI0_RXFR0 *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers -#define SPI0_RXFR1 *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers -#define SPI0_RXFR2 *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers -#define SPI0_RXFR3 *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers +#define SPI_SR_TCF (uint32_t)0x80000000 // Transfer Complete Flag +#define SPI_SR_TXRXS (uint32_t)0x40000000 // TX and RX Status +#define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag +#define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag +#define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag +#define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag +#define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag +#define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register +#define SPI_RSER_TCF_RE (uint32_t)0x80000000 // Transmission Complete Request Enable +#define SPI_RSER_EOQF_RE (uint32_t)0x10000000 // DSPI Finished Request Request Enable +#define SPI_RSER_TFUF_RE (uint32_t)0x08000000 // Transmit FIFO Underflow Request Enable +#define SPI_RSER_TFFF_RE (uint32_t)0x02000000 // Transmit FIFO Fill Request Enable +#define SPI_RSER_TFFF_DIRS (uint32_t)0x01000000 // Transmit FIFO FIll Dma or Interrupt Request Select +#define SPI_RSER_RFOF_RE (uint32_t)0x00080000 // Receive FIFO Overflow Request Enable +#define SPI_RSER_RFDF_RE (uint32_t)0x00020000 // Receive FIFO Drain Request Enable +#define SPI_RSER_RFDF_DIRS (uint32_t)0x00010000 // Receive FIFO Drain DMA or Interrupt Request Select +#define SPI0_PUSHR *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode +#define SPI_PUSHR_CONT (uint32_t)0x80000000 // +#define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) // +#define SPI_PUSHR_EOQ (uint32_t)0x08000000 // +#define SPI_PUSHR_CTCNT (uint32_t)0x04000000 // +#define SPI_PUSHR_PCS(n) (((n) & 31) << 16) // +#define SPI0_PUSHR_SLAVE *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode +#define SPI0_POPR *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register +#define SPI0_TXFR0 *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers +#define SPI0_TXFR1 *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers +#define SPI0_TXFR2 *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers +#define SPI0_TXFR3 *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers +#define SPI0_RXFR0 *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers +#define SPI0_RXFR1 *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers +#define SPI0_RXFR2 *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers +#define SPI0_RXFR3 *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers typedef struct { - volatile uint32_t MCR; // 0 - volatile uint32_t unused1;// 4 - volatile uint32_t TCR; // 8 - volatile uint32_t CTAR0; // c - volatile uint32_t CTAR1; // 10 - volatile uint32_t CTAR2; // 14 - volatile uint32_t CTAR3; // 18 - volatile uint32_t CTAR4; // 1c - volatile uint32_t CTAR5; // 20 - volatile uint32_t CTAR6; // 24 - volatile uint32_t CTAR7; // 28 - volatile uint32_t SR; // 2c - volatile uint32_t RSER; // 30 - volatile uint32_t PUSHR; // 34 - volatile uint32_t POPR; // 38 - volatile uint32_t TXFR[16]; // 3c - volatile uint32_t RXFR[16]; // 7c + volatile uint32_t MCR; // 0 + volatile uint32_t unused1;// 4 + volatile uint32_t TCR; // 8 + volatile uint32_t CTAR0; // c + volatile uint32_t CTAR1; // 10 + volatile uint32_t CTAR2; // 14 + volatile uint32_t CTAR3; // 18 + volatile uint32_t CTAR4; // 1c + volatile uint32_t CTAR5; // 20 + volatile uint32_t CTAR6; // 24 + volatile uint32_t CTAR7; // 28 + volatile uint32_t SR; // 2c + volatile uint32_t RSER; // 30 + volatile uint32_t PUSHR; // 34 + volatile uint32_t POPR; // 38 + volatile uint32_t TXFR[16]; // 3c + volatile uint32_t RXFR[16]; // 7c } SPI_t; -#define SPI0 (*(SPI_t *)0x4002C000) +#define SPI0 (*(SPI_t *)0x4002C000) // Chapter 44: Inter-Integrated Circuit (I2C) #define I2C0_A1 *(volatile uint8_t *)0x40066000 // I2C Address Register 1 #define I2C0_F *(volatile uint8_t *)0x40066001 // I2C Frequency Divider register #define I2C0_C1 *(volatile uint8_t *)0x40066002 // I2C Control Register 1 -#define I2C_C1_IICEN (uint8_t)0x80 // I2C Enable -#define I2C_C1_IICIE (uint8_t)0x40 // I2C Interrupt Enable -#define I2C_C1_MST (uint8_t)0x20 // Master Mode Select -#define I2C_C1_TX (uint8_t)0x10 // Transmit Mode Select -#define I2C_C1_TXAK (uint8_t)0x08 // Transmit Acknowledge Enable -#define I2C_C1_RSTA (uint8_t)0x04 // Repeat START -#define I2C_C1_WUEN (uint8_t)0x02 // Wakeup Enable -#define I2C_C1_DMAEN (uint8_t)0x01 // DMA Enable +#define I2C_C1_IICEN (uint8_t)0x80 // I2C Enable +#define I2C_C1_IICIE (uint8_t)0x40 // I2C Interrupt Enable +#define I2C_C1_MST (uint8_t)0x20 // Master Mode Select +#define I2C_C1_TX (uint8_t)0x10 // Transmit Mode Select +#define I2C_C1_TXAK (uint8_t)0x08 // Transmit Acknowledge Enable +#define I2C_C1_RSTA (uint8_t)0x04 // Repeat START +#define I2C_C1_WUEN (uint8_t)0x02 // Wakeup Enable +#define I2C_C1_DMAEN (uint8_t)0x01 // DMA Enable #define I2C0_S *(volatile uint8_t *)0x40066003 // I2C Status register -#define I2C_S_TCF (uint8_t)0x80 // Transfer Complete Flag -#define I2C_S_IAAS (uint8_t)0x40 // Addressed As A Slave -#define I2C_S_BUSY (uint8_t)0x20 // Bus Busy -#define I2C_S_ARBL (uint8_t)0x10 // Arbitration Lost -#define I2C_S_RAM (uint8_t)0x08 // Range Address Match -#define I2C_S_SRW (uint8_t)0x04 // Slave Read/Write -#define I2C_S_IICIF (uint8_t)0x02 // Interrupt Flag -#define I2C_S_RXAK (uint8_t)0x01 // Receive Acknowledge +#define I2C_S_TCF (uint8_t)0x80 // Transfer Complete Flag +#define I2C_S_IAAS (uint8_t)0x40 // Addressed As A Slave +#define I2C_S_BUSY (uint8_t)0x20 // Bus Busy +#define I2C_S_ARBL (uint8_t)0x10 // Arbitration Lost +#define I2C_S_RAM (uint8_t)0x08 // Range Address Match +#define I2C_S_SRW (uint8_t)0x04 // Slave Read/Write +#define I2C_S_IICIF (uint8_t)0x02 // Interrupt Flag +#define I2C_S_RXAK (uint8_t)0x01 // Receive Acknowledge #define I2C0_D *(volatile uint8_t *)0x40066004 // I2C Data I/O register #define I2C0_C2 *(volatile uint8_t *)0x40066005 // I2C Control Register 2 -#define I2C_C2_GCAEN (uint8_t)0x80 // General Call Address Enable -#define I2C_C2_ADEXT (uint8_t)0x40 // Address Extension -#define I2C_C2_HDRS (uint8_t)0x20 // High Drive Select -#define I2C_C2_SBRC (uint8_t)0x10 // Slave Baud Rate Control -#define I2C_C2_RMEN (uint8_t)0x08 // Range Address Matching Enable -#define I2C_C2_AD(n) ((n) & 7) // Slave Address, upper 3 bits +#define I2C_C2_GCAEN (uint8_t)0x80 // General Call Address Enable +#define I2C_C2_ADEXT (uint8_t)0x40 // Address Extension +#define I2C_C2_HDRS (uint8_t)0x20 // High Drive Select +#define I2C_C2_SBRC (uint8_t)0x10 // Slave Baud Rate Control +#define I2C_C2_RMEN (uint8_t)0x08 // Range Address Matching Enable +#define I2C_C2_AD(n) ((n) & 7) // Slave Address, upper 3 bits #define I2C0_FLT *(volatile uint8_t *)0x40066006 // I2C Programmable Input Glitch Filter register #define I2C0_RA *(volatile uint8_t *)0x40066007 // I2C Range Address register #define I2C0_SMB *(volatile uint8_t *)0x40066008 // I2C SMBus Control and Status register @@ -1429,57 +1429,59 @@ #define UART0_BDH *(volatile uint8_t *)0x4006A000 // UART Baud Rate Registers: High #define UART0_BDL *(volatile uint8_t *)0x4006A001 // UART Baud Rate Registers: Low #define UART0_C1 *(volatile uint8_t *)0x4006A002 // UART Control Register 1 -#define UART_C1_LOOPS (uint8_t)0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input -#define UART_C1_UARTSWAI (uint8_t)0x40 // UART Stops in Wait Mode -#define UART_C1_RSRC (uint8_t)0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input -#define UART_C1_M (uint8_t)0x10 // 9-bit or 8-bit Mode Select -#define UART_C1_WAKE (uint8_t)0x08 // Determines which condition wakes the UART -#define UART_C1_ILT (uint8_t)0x04 // Idle Line Type Select -#define UART_C1_PE (uint8_t)0x02 // Parity Enable -#define UART_C1_PT (uint8_t)0x01 // Parity Type, 0=even, 1=odd +#define UART_C1_LOOPS (uint8_t)0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input +#define UART_C1_UARTSWAI (uint8_t)0x40 // UART Stops in Wait Mode +#define UART_C1_RSRC (uint8_t)0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input +#define UART_C1_M (uint8_t)0x10 // 9-bit or 8-bit Mode Select +#define UART_C1_WAKE (uint8_t)0x08 // Determines which condition wakes the UART +#define UART_C1_ILT (uint8_t)0x04 // Idle Line Type Select +#define UART_C1_PE (uint8_t)0x02 // Parity Enable +#define UART_C1_PT (uint8_t)0x01 // Parity Type, 0=even, 1=odd #define UART0_C2 *(volatile uint8_t *)0x4006A003 // UART Control Register 2 -#define UART_C2_TIE (uint8_t)0x80 // Transmitter Interrupt or DMA Transfer Enable. -#define UART_C2_TCIE (uint8_t)0x40 // Transmission Complete Interrupt Enable -#define UART_C2_RIE (uint8_t)0x20 // Receiver Full Interrupt or DMA Transfer Enable -#define UART_C2_ILIE (uint8_t)0x10 // Idle Line Interrupt Enable -#define UART_C2_TE (uint8_t)0x08 // Transmitter Enable -#define UART_C2_RE (uint8_t)0x04 // Receiver Enable -#define UART_C2_RWU (uint8_t)0x02 // Receiver Wakeup Control -#define UART_C2_SBK (uint8_t)0x01 // Send Break +#define UART_C2_TIE (uint8_t)0x80 // Transmitter Interrupt or DMA Transfer Enable. +#define UART_C2_TCIE (uint8_t)0x40 // Transmission Complete Interrupt Enable +#define UART_C2_RIE (uint8_t)0x20 // Receiver Full Interrupt or DMA Transfer Enable +#define UART_C2_ILIE (uint8_t)0x10 // Idle Line Interrupt Enable +#define UART_C2_TE (uint8_t)0x08 // Transmitter Enable +#define UART_C2_RE (uint8_t)0x04 // Receiver Enable +#define UART_C2_RWU (uint8_t)0x02 // Receiver Wakeup Control +#define UART_C2_SBK (uint8_t)0x01 // Send Break #define UART0_S1 *(volatile uint8_t *)0x4006A004 // UART Status Register 1 -#define UART_S1_TDRE (uint8_t)0x80 // Transmit Data Register Empty Flag -#define UART_S1_TC (uint8_t)0x40 // Transmit Complete Flag -#define UART_S1_RDRF (uint8_t)0x20 // Receive Data Register Full Flag -#define UART_S1_IDLE (uint8_t)0x10 // Idle Line Flag -#define UART_S1_OR (uint8_t)0x08 // Receiver Overrun Flag -#define UART_S1_NF (uint8_t)0x04 // Noise Flag -#define UART_S1_FE (uint8_t)0x02 // Framing Error Flag -#define UART_S1_PF (uint8_t)0x01 // Parity Error Flag -#define UART0_S2 *(volatile uint8_t *)0x4006A005 // UART Status Register 2 -#define UART0_C3 *(volatile uint8_t *)0x4006A006 // UART Control Register 3 -#define UART0_D *(volatile uint8_t *)0x4006A007 // UART Data Register -#define UART0_MA1 *(volatile uint8_t *)0x4006A008 // UART Match Address Registers 1 -#define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2 -#define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4 -#define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5 -#define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register -#define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register -#define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register -#define UART0_PFIFO *(volatile uint8_t *)0x4006A010 // UART FIFO Parameters -#define UART_PFIFO_TXFE (uint8_t)0x80 -#define UART_PFIFO_RXFE (uint8_t)0x08 +#define UART_S1_TDRE (uint8_t)0x80 // Transmit Data Register Empty Flag +#define UART_S1_TC (uint8_t)0x40 // Transmit Complete Flag +#define UART_S1_RDRF (uint8_t)0x20 // Receive Data Register Full Flag +#define UART_S1_IDLE (uint8_t)0x10 // Idle Line Flag +#define UART_S1_OR (uint8_t)0x08 // Receiver Overrun Flag +#define UART_S1_NF (uint8_t)0x04 // Noise Flag +#define UART_S1_FE (uint8_t)0x02 // Framing Error Flag +#define UART_S1_PF (uint8_t)0x01 // Parity Error Flag +#define UART0_S2 *(volatile uint8_t *)0x4006A005 // UART Status Register 2 +#define UART0_C3 *(volatile uint8_t *)0x4006A006 // UART Control Register 3 +#define UART0_D *(volatile uint8_t *)0x4006A007 // UART Data Register +#define UART0_MA1 *(volatile uint8_t *)0x4006A008 // UART Match Address Registers 1 +#define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2 +#define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4 +#define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5 +#define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register +#define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register +#define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register +#define UART0_PFIFO *(volatile uint8_t *)0x4006A010 // UART FIFO Parameters +#define UART_PFIFO_TXFE (uint8_t)0x80 +#define UART_PFIFO_TXFIFOSIZE (uint8_t)0x70 +#define UART_PFIFO_RXFE (uint8_t)0x08 +#define UART_PFIFO_RXFIFOSIZE (uint8_t)0x07 #define UART0_CFIFO *(volatile uint8_t *)0x4006A011 // UART FIFO Control Register -#define UART_CFIFO_TXFLUSH (uint8_t)0x80 // -#define UART_CFIFO_RXFLUSH (uint8_t)0x40 // -#define UART_CFIFO_RXOFE (uint8_t)0x04 // -#define UART_CFIFO_TXOFE (uint8_t)0x02 // -#define UART_CFIFO_RXUFE (uint8_t)0x01 // +#define UART_CFIFO_TXFLUSH (uint8_t)0x80 // +#define UART_CFIFO_RXFLUSH (uint8_t)0x40 // +#define UART_CFIFO_RXOFE (uint8_t)0x04 // +#define UART_CFIFO_TXOFE (uint8_t)0x02 // +#define UART_CFIFO_RXUFE (uint8_t)0x01 // #define UART0_SFIFO *(volatile uint8_t *)0x4006A012 // UART FIFO Status Register -#define UART_SFIFO_TXEMPT (uint8_t)0x80 -#define UART_SFIFO_RXEMPT (uint8_t)0x40 -#define UART_SFIFO_RXOF (uint8_t)0x04 -#define UART_SFIFO_TXOF (uint8_t)0x02 -#define UART_SFIFO_RXUF (uint8_t)0x01 +#define UART_SFIFO_TXEMPT (uint8_t)0x80 +#define UART_SFIFO_RXEMPT (uint8_t)0x40 +#define UART_SFIFO_RXOF (uint8_t)0x04 +#define UART_SFIFO_TXOF (uint8_t)0x02 +#define UART_SFIFO_RXUF (uint8_t)0x01 #define UART0_TWFIFO *(volatile uint8_t *)0x4006A013 // UART FIFO Transmit Watermark #define UART0_TCFIFO *(volatile uint8_t *)0x4006A014 // UART FIFO Transmit Count #define UART0_RWFIFO *(volatile uint8_t *)0x4006A015 // UART FIFO Receive Watermark @@ -1608,111 +1610,111 @@ #define UART2_TIDT *(volatile uint8_t *)0x4006C031 // UART CEA709.1-B Transmit Indeterminate Time // Chapter 46: Synchronous Audio Interface (SAI) -#define I2S0_TCSR *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register -#define I2S_TCSR_TE (uint32_t)0x80000000 // Transmitter Enable -#define I2S_TCSR_STOPE (uint32_t)0x40000000 // Transmitter Enable in Stop mode -#define I2S_TCSR_DBGE (uint32_t)0x20000000 // Transmitter Enable in Debug mode -#define I2S_TCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable -#define I2S_TCSR_FR (uint32_t)0x02000000 // FIFO Reset -#define I2S_TCSR_SR (uint32_t)0x01000000 // Software Reset -#define I2S_TCSR_WSF (uint32_t)0x00100000 // Word Start Flag -#define I2S_TCSR_SEF (uint32_t)0x00080000 // Sync Error Flag -#define I2S_TCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun) -#define I2S_TCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty) -#define I2S_TCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready) -#define I2S_TCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable -#define I2S_TCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable -#define I2S_TCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable -#define I2S_TCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable -#define I2S_TCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable -#define I2S_TCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable -#define I2S_TCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable -#define I2S0_TCR1 *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register -#define I2S_TCR1_TFW(n) ((uint32_t)n & 0x03) // Transmit FIFO watermark -#define I2S0_TCR2 *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register -#define I2S_TCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2 -#define I2S_TCR2_BCD ((uint32_t)1<<24) // Bit clock direction -#define I2S_TCR2_BCP ((uint32_t)1<<25) // Bit clock polarity -#define I2S_TCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK -#define I2S_TCR2_BCI ((uint32_t)1<<28) // Bit clock input -#define I2S_TCR2_BCS ((uint32_t)1<<29) // Bit clock swap -#define I2S_TCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver -#define I2S0_TCR3 *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register -#define I2S_TCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration -#define I2S_TCR3_TCE ((uint32_t)0x10000) // transmit channel enable -#define I2S0_TCR4 *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register -#define I2S_TCR4_FSD ((uint32_t)1) // Frame Sync Direction -#define I2S_TCR4_FSP ((uint32_t)2) // Frame Sync Polarity -#define I2S_TCR4_FSE ((uint32_t)8) // Frame Sync Early -#define I2S_TCR4_MF ((uint32_t)0x10) // MSB First -#define I2S_TCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width -#define I2S_TCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size -#define I2S0_TCR5 *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register -#define I2S_TCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted -#define I2S_TCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width -#define I2S_TCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width -#define I2S0_TDR0 *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register -#define I2S0_TFR0 *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register -#define I2S_TFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer -#define I2S_TFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer -#define I2S0_TMR *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register -#define I2S_TMR_TWM(n) ((uint32_t)n & 0xFFFFFFFF) -#define I2S0_RCSR *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register -#define I2S_RCSR_RE (uint32_t)0x80000000 // Receiver Enable -#define I2S_RCSR_STOPE (uint32_t)0x40000000 // Receiver Enable in Stop mode -#define I2S_RCSR_DBGE (uint32_t)0x20000000 // Receiver Enable in Debug mode -#define I2S_RCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable -#define I2S_RCSR_FR (uint32_t)0x02000000 // FIFO Reset -#define I2S_RCSR_SR (uint32_t)0x01000000 // Software Reset -#define I2S_RCSR_WSF (uint32_t)0x00100000 // Word Start Flag -#define I2S_RCSR_SEF (uint32_t)0x00080000 // Sync Error Flag -#define I2S_RCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun) -#define I2S_RCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty) -#define I2S_RCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready) -#define I2S_RCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable -#define I2S_RCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable -#define I2S_RCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable -#define I2S_RCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable -#define I2S_RCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable -#define I2S_RCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable -#define I2S_RCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable -#define I2S0_RCR1 *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register -#define I2S_RCR1_RFW(n) ((uint32_t)n & 0x03) // Receive FIFO watermark -#define I2S0_RCR2 *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register -#define I2S_RCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2 -#define I2S_RCR2_BCD ((uint32_t)1<<24) // Bit clock direction -#define I2S_RCR2_BCP ((uint32_t)1<<25) // Bit clock polarity -#define I2S_RCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK -#define I2S_RCR2_BCI ((uint32_t)1<<28) // Bit clock input -#define I2S_RCR2_BCS ((uint32_t)1<<29) // Bit clock swap -#define I2S_RCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver -#define I2S0_RCR3 *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register -#define I2S_RCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration -#define I2S_RCR3_RCE ((uint32_t)0x10000) // receive channel enable -#define I2S0_RCR4 *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register -#define I2S_RCR4_FSD ((uint32_t)1) // Frame Sync Direction -#define I2S_RCR4_FSP ((uint32_t)2) // Frame Sync Polarity -#define I2S_RCR4_FSE ((uint32_t)8) // Frame Sync Early -#define I2S_RCR4_MF ((uint32_t)0x10) // MSB First -#define I2S_RCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width -#define I2S_RCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size -#define I2S0_RCR5 *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register -#define I2S_RCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted -#define I2S_RCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width -#define I2S_RCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width -#define I2S0_RDR0 *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register -#define I2S0_RFR0 *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register -#define I2S_RFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer -#define I2S_RFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer -#define I2S0_RMR *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register -#define I2S_RMR_RWM(n) ((uint32_t)n & 0xFFFFFFFF) -#define I2S0_MCR *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register -#define I2S_MCR_DUF ((uint32_t)1<<31) // Divider Update Flag -#define I2S_MCR_MOE ((uint32_t)1<<30) // MCLK Output Enable -#define I2S_MCR_MICS(n) ((uint32_t)(n & 3)<<24) // MCLK Input Clock Select -#define I2S0_MDR *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register -#define I2S_MDR_FRACT(n) ((uint32_t)(n & 0xff)<<12) // MCLK Fraction -#define I2S_MDR_DIVIDE(n) ((uint32_t)(n & 0xfff)) // MCLK Divide +#define I2S0_TCSR *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register +#define I2S_TCSR_TE (uint32_t)0x80000000 // Transmitter Enable +#define I2S_TCSR_STOPE (uint32_t)0x40000000 // Transmitter Enable in Stop mode +#define I2S_TCSR_DBGE (uint32_t)0x20000000 // Transmitter Enable in Debug mode +#define I2S_TCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable +#define I2S_TCSR_FR (uint32_t)0x02000000 // FIFO Reset +#define I2S_TCSR_SR (uint32_t)0x01000000 // Software Reset +#define I2S_TCSR_WSF (uint32_t)0x00100000 // Word Start Flag +#define I2S_TCSR_SEF (uint32_t)0x00080000 // Sync Error Flag +#define I2S_TCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun) +#define I2S_TCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty) +#define I2S_TCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready) +#define I2S_TCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable +#define I2S_TCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable +#define I2S_TCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable +#define I2S_TCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable +#define I2S_TCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable +#define I2S_TCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable +#define I2S_TCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable +#define I2S0_TCR1 *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register +#define I2S_TCR1_TFW(n) ((uint32_t)n & 0x03) // Transmit FIFO watermark +#define I2S0_TCR2 *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register +#define I2S_TCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2 +#define I2S_TCR2_BCD ((uint32_t)1<<24) // Bit clock direction +#define I2S_TCR2_BCP ((uint32_t)1<<25) // Bit clock polarity +#define I2S_TCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK +#define I2S_TCR2_BCI ((uint32_t)1<<28) // Bit clock input +#define I2S_TCR2_BCS ((uint32_t)1<<29) // Bit clock swap +#define I2S_TCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver +#define I2S0_TCR3 *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register +#define I2S_TCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration +#define I2S_TCR3_TCE ((uint32_t)0x10000) // transmit channel enable +#define I2S0_TCR4 *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register +#define I2S_TCR4_FSD ((uint32_t)1) // Frame Sync Direction +#define I2S_TCR4_FSP ((uint32_t)2) // Frame Sync Polarity +#define I2S_TCR4_FSE ((uint32_t)8) // Frame Sync Early +#define I2S_TCR4_MF ((uint32_t)0x10) // MSB First +#define I2S_TCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width +#define I2S_TCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size +#define I2S0_TCR5 *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register +#define I2S_TCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted +#define I2S_TCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width +#define I2S_TCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width +#define I2S0_TDR0 *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register +#define I2S0_TFR0 *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register +#define I2S_TFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer +#define I2S_TFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer +#define I2S0_TMR *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register +#define I2S_TMR_TWM(n) ((uint32_t)n & 0xFFFFFFFF) +#define I2S0_RCSR *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register +#define I2S_RCSR_RE (uint32_t)0x80000000 // Receiver Enable +#define I2S_RCSR_STOPE (uint32_t)0x40000000 // Receiver Enable in Stop mode +#define I2S_RCSR_DBGE (uint32_t)0x20000000 // Receiver Enable in Debug mode +#define I2S_RCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable +#define I2S_RCSR_FR (uint32_t)0x02000000 // FIFO Reset +#define I2S_RCSR_SR (uint32_t)0x01000000 // Software Reset +#define I2S_RCSR_WSF (uint32_t)0x00100000 // Word Start Flag +#define I2S_RCSR_SEF (uint32_t)0x00080000 // Sync Error Flag +#define I2S_RCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun) +#define I2S_RCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty) +#define I2S_RCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready) +#define I2S_RCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable +#define I2S_RCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable +#define I2S_RCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable +#define I2S_RCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable +#define I2S_RCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable +#define I2S_RCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable +#define I2S_RCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable +#define I2S0_RCR1 *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register +#define I2S_RCR1_RFW(n) ((uint32_t)n & 0x03) // Receive FIFO watermark +#define I2S0_RCR2 *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register +#define I2S_RCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2 +#define I2S_RCR2_BCD ((uint32_t)1<<24) // Bit clock direction +#define I2S_RCR2_BCP ((uint32_t)1<<25) // Bit clock polarity +#define I2S_RCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK +#define I2S_RCR2_BCI ((uint32_t)1<<28) // Bit clock input +#define I2S_RCR2_BCS ((uint32_t)1<<29) // Bit clock swap +#define I2S_RCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver +#define I2S0_RCR3 *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register +#define I2S_RCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration +#define I2S_RCR3_RCE ((uint32_t)0x10000) // receive channel enable +#define I2S0_RCR4 *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register +#define I2S_RCR4_FSD ((uint32_t)1) // Frame Sync Direction +#define I2S_RCR4_FSP ((uint32_t)2) // Frame Sync Polarity +#define I2S_RCR4_FSE ((uint32_t)8) // Frame Sync Early +#define I2S_RCR4_MF ((uint32_t)0x10) // MSB First +#define I2S_RCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width +#define I2S_RCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size +#define I2S0_RCR5 *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register +#define I2S_RCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted +#define I2S_RCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width +#define I2S_RCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width +#define I2S0_RDR0 *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register +#define I2S0_RFR0 *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register +#define I2S_RFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer +#define I2S_RFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer +#define I2S0_RMR *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register +#define I2S_RMR_RWM(n) ((uint32_t)n & 0xFFFFFFFF) +#define I2S0_MCR *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register +#define I2S_MCR_DUF ((uint32_t)1<<31) // Divider Update Flag +#define I2S_MCR_MOE ((uint32_t)1<<30) // MCLK Output Enable +#define I2S_MCR_MICS(n) ((uint32_t)(n & 3)<<24) // MCLK Input Clock Select +#define I2S0_MDR *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register +#define I2S_MDR_FRACT(n) ((uint32_t)(n & 0xff)<<12) // MCLK Fraction +#define I2S_MDR_DIVIDE(n) ((uint32_t)(n & 0xfff)) // MCLK Divide // Chapter 47: General-Purpose Input/Output (GPIO) #define GPIOA_PDOR *(volatile uint32_t *)0x400FF000 // Port Data Output Register @@ -1748,28 +1750,28 @@ // Chapter 48: Touch sense input (TSI) #define TSI0_GENCS *(volatile uint32_t *)0x40045000 // General Control and Status Register -#define TSI_GENCS_LPCLKS (uint32_t)0x10000000 // -#define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) // -#define TSI_GENCS_NSCN(n) (((n) & 31) << 19) // -#define TSI_GENCS_PS(n) (((n) & 7) << 16) // -#define TSI_GENCS_EOSF (uint32_t)0x00008000 // -#define TSI_GENCS_OUTRGF (uint32_t)0x00004000 // -#define TSI_GENCS_EXTERF (uint32_t)0x00002000 // -#define TSI_GENCS_OVRF (uint32_t)0x00001000 // -#define TSI_GENCS_SCNIP (uint32_t)0x00000200 // -#define TSI_GENCS_SWTS (uint32_t)0x00000100 // -#define TSI_GENCS_TSIEN (uint32_t)0x00000080 // -#define TSI_GENCS_TSIIE (uint32_t)0x00000040 // -#define TSI_GENCS_ERIE (uint32_t)0x00000020 // -#define TSI_GENCS_ESOR (uint32_t)0x00000010 // -#define TSI_GENCS_STM (uint32_t)0x00000002 // -#define TSI_GENCS_STPE (uint32_t)0x00000001 // +#define TSI_GENCS_LPCLKS (uint32_t)0x10000000 // +#define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) // +#define TSI_GENCS_NSCN(n) (((n) & 31) << 19) // +#define TSI_GENCS_PS(n) (((n) & 7) << 16) // +#define TSI_GENCS_EOSF (uint32_t)0x00008000 // +#define TSI_GENCS_OUTRGF (uint32_t)0x00004000 // +#define TSI_GENCS_EXTERF (uint32_t)0x00002000 // +#define TSI_GENCS_OVRF (uint32_t)0x00001000 // +#define TSI_GENCS_SCNIP (uint32_t)0x00000200 // +#define TSI_GENCS_SWTS (uint32_t)0x00000100 // +#define TSI_GENCS_TSIEN (uint32_t)0x00000080 // +#define TSI_GENCS_TSIIE (uint32_t)0x00000040 // +#define TSI_GENCS_ERIE (uint32_t)0x00000020 // +#define TSI_GENCS_ESOR (uint32_t)0x00000010 // +#define TSI_GENCS_STM (uint32_t)0x00000002 // +#define TSI_GENCS_STPE (uint32_t)0x00000001 // #define TSI0_SCANC *(volatile uint32_t *)0x40045004 // SCAN Control Register -#define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) // -#define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) // -#define TSI_SCANC_SMOD(n) (((n) & 255) << 8) // -#define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) // -#define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) // +#define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) // +#define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) // +#define TSI_SCANC_SMOD(n) (((n) & 255) << 8) // +#define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) // +#define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) // #define TSI0_PEN *(volatile uint32_t *)0x40045008 // Pin Enable Register #define TSI0_WUCNTR *(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register #define TSI0_CNTR1 *(volatile uint32_t *)0x40045100 // Counter Register @@ -1783,15 +1785,15 @@ #define TSI0_THRESHOLD *(volatile uint32_t *)0x40045120 // Low Power Channel Threshold Register // Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750) -#define NVIC_ENABLE_IRQ(n) (*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31))) -#define NVIC_DISABLE_IRQ(n) (*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31))) -#define NVIC_SET_PENDING(n) (*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31))) -#define NVIC_CLEAR_PENDING(n) (*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31))) +#define NVIC_ENABLE_IRQ(n) (*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31))) +#define NVIC_DISABLE_IRQ(n) (*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31))) +#define NVIC_SET_PENDING(n) (*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31))) +#define NVIC_CLEAR_PENDING(n) (*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31))) -#define NVIC_ISER0 *(volatile uint32_t *)0xE000E100 -#define NVIC_ISER1 *(volatile uint32_t *)0xE000E104 -#define NVIC_ICER0 *(volatile uint32_t *)0xE000E180 -#define NVIC_ICER1 *(volatile uint32_t *)0xE000E184 +#define NVIC_ISER0 *(volatile uint32_t *)0xE000E100 +#define NVIC_ISER1 *(volatile uint32_t *)0xE000E104 +#define NVIC_ICER0 *(volatile uint32_t *)0xE000E180 +#define NVIC_ICER1 *(volatile uint32_t *)0xE000E184 // 0 = highest priority // Cortex-M4: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240 @@ -1800,124 +1802,124 @@ #define NVIC_GET_PRIORITY(irqnum) (*((uint8_t *)0xE000E400 + (irqnum))) #if defined(_mk20dx128_) || defined(_mk20dx128vlf5_) -#define IRQ_DMA_CH0 0 -#define IRQ_DMA_CH1 1 -#define IRQ_DMA_CH2 2 -#define IRQ_DMA_CH3 3 -#define IRQ_DMA_ERROR 4 -#define IRQ_FTFL_COMPLETE 6 -#define IRQ_FTFL_COLLISION 7 -#define IRQ_LOW_VOLTAGE 8 -#define IRQ_LLWU 9 -#define IRQ_WDOG 10 -#define IRQ_I2C0 11 -#define IRQ_SPI0 12 -#define IRQ_I2S0_TX 13 -#define IRQ_I2S0_RX 14 -#define IRQ_UART0_LON 15 -#define IRQ_UART0_STATUS 16 -#define IRQ_UART0_ERROR 17 -#define IRQ_UART1_STATUS 18 -#define IRQ_UART1_ERROR 19 -#define IRQ_UART2_STATUS 20 -#define IRQ_UART2_ERROR 21 -#define IRQ_ADC0 22 -#define IRQ_CMP0 23 -#define IRQ_CMP1 24 -#define IRQ_FTM0 25 -#define IRQ_FTM1 26 -#define IRQ_CMT 27 -#define IRQ_RTC_ALARM 28 -#define IRQ_RTC_SECOND 29 -#define IRQ_PIT_CH0 30 -#define IRQ_PIT_CH1 31 -#define IRQ_PIT_CH2 32 -#define IRQ_PIT_CH3 33 -#define IRQ_PDB 34 -#define IRQ_USBOTG 35 -#define IRQ_USBDCD 36 -#define IRQ_TSI 37 -#define IRQ_MCG 38 -#define IRQ_LPTMR 39 -#define IRQ_PORTA 40 -#define IRQ_PORTB 41 -#define IRQ_PORTC 42 -#define IRQ_PORTD 43 -#define IRQ_PORTE 44 -#define IRQ_SOFTWARE 45 -#define NVIC_NUM_INTERRUPTS 46 +#define IRQ_DMA_CH0 0 +#define IRQ_DMA_CH1 1 +#define IRQ_DMA_CH2 2 +#define IRQ_DMA_CH3 3 +#define IRQ_DMA_ERROR 4 +#define IRQ_FTFL_COMPLETE 6 +#define IRQ_FTFL_COLLISION 7 +#define IRQ_LOW_VOLTAGE 8 +#define IRQ_LLWU 9 +#define IRQ_WDOG 10 +#define IRQ_I2C0 11 +#define IRQ_SPI0 12 +#define IRQ_I2S0_TX 13 +#define IRQ_I2S0_RX 14 +#define IRQ_UART0_LON 15 +#define IRQ_UART0_STATUS 16 +#define IRQ_UART0_ERROR 17 +#define IRQ_UART1_STATUS 18 +#define IRQ_UART1_ERROR 19 +#define IRQ_UART2_STATUS 20 +#define IRQ_UART2_ERROR 21 +#define IRQ_ADC0 22 +#define IRQ_CMP0 23 +#define IRQ_CMP1 24 +#define IRQ_FTM0 25 +#define IRQ_FTM1 26 +#define IRQ_CMT 27 +#define IRQ_RTC_ALARM 28 +#define IRQ_RTC_SECOND 29 +#define IRQ_PIT_CH0 30 +#define IRQ_PIT_CH1 31 +#define IRQ_PIT_CH2 32 +#define IRQ_PIT_CH3 33 +#define IRQ_PDB 34 +#define IRQ_USBOTG 35 +#define IRQ_USBDCD 36 +#define IRQ_TSI 37 +#define IRQ_MCG 38 +#define IRQ_LPTMR 39 +#define IRQ_PORTA 40 +#define IRQ_PORTB 41 +#define IRQ_PORTC 42 +#define IRQ_PORTD 43 +#define IRQ_PORTE 44 +#define IRQ_SOFTWARE 45 +#define NVIC_NUM_INTERRUPTS 46 #elif defined(_mk20dx256_) || defined(_mk20dx256vlh7_) -#define IRQ_DMA_CH0 0 -#define IRQ_DMA_CH1 1 -#define IRQ_DMA_CH2 2 -#define IRQ_DMA_CH3 3 -#define IRQ_DMA_CH4 4 -#define IRQ_DMA_CH5 5 -#define IRQ_DMA_CH6 6 -#define IRQ_DMA_CH7 7 -#define IRQ_DMA_CH8 8 -#define IRQ_DMA_CH9 9 -#define IRQ_DMA_CH10 10 -#define IRQ_DMA_CH11 11 -#define IRQ_DMA_CH12 12 -#define IRQ_DMA_CH13 13 -#define IRQ_DMA_CH14 14 -#define IRQ_DMA_CH15 15 -#define IRQ_DMA_ERROR 16 -#define IRQ_FTFL_COMPLETE 18 -#define IRQ_FTFL_COLLISION 19 -#define IRQ_LOW_VOLTAGE 20 -#define IRQ_LLWU 21 -#define IRQ_WDOG 22 -#define IRQ_I2C0 24 -#define IRQ_I2C1 25 -#define IRQ_SPI0 26 -#define IRQ_SPI1 27 -#define IRQ_CAN_MESSAGE 29 -#define IRQ_CAN_BUS_OFF 30 -#define IRQ_CAN_ERROR 31 -#define IRQ_CAN_TX_WARN 32 -#define IRQ_CAN_RX_WARN 33 -#define IRQ_CAN_WAKEUP 34 -#define IRQ_I2S0_TX 35 -#define IRQ_I2S0_RX 36 -#define IRQ_UART0_LON 44 -#define IRQ_UART0_STATUS 45 -#define IRQ_UART0_ERROR 46 -#define IRQ_UART1_STATUS 47 -#define IRQ_UART1_ERROR 48 -#define IRQ_UART2_STATUS 49 -#define IRQ_UART2_ERROR 50 -#define IRQ_ADC0 57 -#define IRQ_ADC1 58 -#define IRQ_CMP0 59 -#define IRQ_CMP1 60 -#define IRQ_CMP2 61 -#define IRQ_FTM0 62 -#define IRQ_FTM1 63 -#define IRQ_FTM2 64 -#define IRQ_CMT 65 -#define IRQ_RTC_ALARM 66 -#define IRQ_RTC_SECOND 67 -#define IRQ_PIT_CH0 68 -#define IRQ_PIT_CH1 69 -#define IRQ_PIT_CH2 70 -#define IRQ_PIT_CH3 71 -#define IRQ_PDB 72 -#define IRQ_USBOTG 73 -#define IRQ_USBDCD 74 -#define IRQ_DAC0 81 -#define IRQ_TSI 83 -#define IRQ_MCG 84 -#define IRQ_LPTMR 85 -#define IRQ_PORTA 87 -#define IRQ_PORTB 88 -#define IRQ_PORTC 89 -#define IRQ_PORTD 90 -#define IRQ_PORTE 91 -#define IRQ_SOFTWARE 94 -#define NVIC_NUM_INTERRUPTS 95 +#define IRQ_DMA_CH0 0 +#define IRQ_DMA_CH1 1 +#define IRQ_DMA_CH2 2 +#define IRQ_DMA_CH3 3 +#define IRQ_DMA_CH4 4 +#define IRQ_DMA_CH5 5 +#define IRQ_DMA_CH6 6 +#define IRQ_DMA_CH7 7 +#define IRQ_DMA_CH8 8 +#define IRQ_DMA_CH9 9 +#define IRQ_DMA_CH10 10 +#define IRQ_DMA_CH11 11 +#define IRQ_DMA_CH12 12 +#define IRQ_DMA_CH13 13 +#define IRQ_DMA_CH14 14 +#define IRQ_DMA_CH15 15 +#define IRQ_DMA_ERROR 16 +#define IRQ_FTFL_COMPLETE 18 +#define IRQ_FTFL_COLLISION 19 +#define IRQ_LOW_VOLTAGE 20 +#define IRQ_LLWU 21 +#define IRQ_WDOG 22 +#define IRQ_I2C0 24 +#define IRQ_I2C1 25 +#define IRQ_SPI0 26 +#define IRQ_SPI1 27 +#define IRQ_CAN_MESSAGE 29 +#define IRQ_CAN_BUS_OFF 30 +#define IRQ_CAN_ERROR 31 +#define IRQ_CAN_TX_WARN 32 +#define IRQ_CAN_RX_WARN 33 +#define IRQ_CAN_WAKEUP 34 +#define IRQ_I2S0_TX 35 +#define IRQ_I2S0_RX 36 +#define IRQ_UART0_LON 44 +#define IRQ_UART0_STATUS 45 +#define IRQ_UART0_ERROR 46 +#define IRQ_UART1_STATUS 47 +#define IRQ_UART1_ERROR 48 +#define IRQ_UART2_STATUS 49 +#define IRQ_UART2_ERROR 50 +#define IRQ_ADC0 57 +#define IRQ_ADC1 58 +#define IRQ_CMP0 59 +#define IRQ_CMP1 60 +#define IRQ_CMP2 61 +#define IRQ_FTM0 62 +#define IRQ_FTM1 63 +#define IRQ_FTM2 64 +#define IRQ_CMT 65 +#define IRQ_RTC_ALARM 66 +#define IRQ_RTC_SECOND 67 +#define IRQ_PIT_CH0 68 +#define IRQ_PIT_CH1 69 +#define IRQ_PIT_CH2 70 +#define IRQ_PIT_CH3 71 +#define IRQ_PDB 72 +#define IRQ_USBOTG 73 +#define IRQ_USBDCD 74 +#define IRQ_DAC0 81 +#define IRQ_TSI 83 +#define IRQ_MCG 84 +#define IRQ_LPTMR 85 +#define IRQ_PORTA 87 +#define IRQ_PORTB 88 +#define IRQ_PORTC 89 +#define IRQ_PORTD 90 +#define IRQ_PORTE 91 +#define IRQ_SOFTWARE 94 +#define NVIC_NUM_INTERRUPTS 95 #endif @@ -1926,37 +1928,37 @@ #define __disable_irq() asm volatile("CPSID i"); -#define __enable_irq() asm volatile("CPSIE i"); +#define __enable_irq() asm volatile("CPSIE i"); // System Control Space (SCS), ARMv7 ref manual, B3.2, page 708 -#define SCB_CPUID *(const uint32_t *)0xE000ED00 // CPUID Base Register -#define SCB_ICSR *(volatile uint32_t *)0xE000ED04 // Interrupt Control and State -#define SCB_ICSR_PENDSTSET (uint32_t)0x04000000 -#define SCB_VTOR *(volatile uint32_t *)0xE000ED08 // Vector Table Offset -#define SCB_AIRCR *(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control -#define SCB_SCR *(volatile uint32_t *)0xE000ED10 // System Control Register -#define SCB_CCR *(volatile uint32_t *)0xE000ED14 // Configuration and Control -#define SCB_SHPR1 *(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1 -#define SCB_SHPR2 *(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2 -#define SCB_SHPR3 *(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3 -#define SCB_SHCSR *(volatile uint32_t *)0xE000ED24 // System Handler Control and State -#define SCB_CFSR *(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register -#define SCB_HFSR *(volatile uint32_t *)0xE000ED2C // HardFault Status -#define SCB_DFSR *(volatile uint32_t *)0xE000ED30 // Debug Fault Status -#define SCB_MMFAR *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address +#define SCB_CPUID *(const uint32_t *)0xE000ED00 // CPUID Base Register +#define SCB_ICSR *(volatile uint32_t *)0xE000ED04 // Interrupt Control and State +#define SCB_ICSR_PENDSTSET (uint32_t)0x04000000 +#define SCB_VTOR *(volatile uint32_t *)0xE000ED08 // Vector Table Offset +#define SCB_AIRCR *(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control +#define SCB_SCR *(volatile uint32_t *)0xE000ED10 // System Control Register +#define SCB_CCR *(volatile uint32_t *)0xE000ED14 // Configuration and Control +#define SCB_SHPR1 *(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1 +#define SCB_SHPR2 *(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2 +#define SCB_SHPR3 *(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3 +#define SCB_SHCSR *(volatile uint32_t *)0xE000ED24 // System Handler Control and State +#define SCB_CFSR *(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register +#define SCB_HFSR *(volatile uint32_t *)0xE000ED2C // HardFault Status +#define SCB_DFSR *(volatile uint32_t *)0xE000ED30 // Debug Fault Status +#define SCB_MMFAR *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address -#define SYST_CSR *(volatile uint32_t *)0xE000E010 // SysTick Control and Status -#define SYST_CSR_COUNTFLAG (uint32_t)0x00010000 -#define SYST_CSR_CLKSOURCE (uint32_t)0x00000004 -#define SYST_CSR_TICKINT (uint32_t)0x00000002 -#define SYST_CSR_ENABLE (uint32_t)0x00000001 -#define SYST_RVR *(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register -#define SYST_CVR *(volatile uint32_t *)0xE000E018 // SysTick Current Value Register -#define SYST_CALIB *(const uint32_t *)0xE000E01C // SysTick Calibration Value +#define SYST_CSR *(volatile uint32_t *)0xE000E010 // SysTick Control and Status +#define SYST_CSR_COUNTFLAG (uint32_t)0x00010000 +#define SYST_CSR_CLKSOURCE (uint32_t)0x00000004 +#define SYST_CSR_TICKINT (uint32_t)0x00000002 +#define SYST_CSR_ENABLE (uint32_t)0x00000001 +#define SYST_RVR *(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register +#define SYST_CVR *(volatile uint32_t *)0xE000E018 // SysTick Current Value Register +#define SYST_CALIB *(const uint32_t *)0xE000E01C // SysTick Calibration Value #define ARM_DEMCR *(volatile uint32_t *)0xE000EDFC // Debug Exception and Monitor Control -#define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks +#define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks #define ARM_DWT_CTRL *(volatile uint32_t *)0xE0001000 // DWT control register #define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count #define ARM_DWT_CYCCNT *(volatile uint32_t *)0xE0001004 // Cycle count register
--- a/Lib/mk20dx256vlh7.bootloader.ld Sun Mar 08 22:35:55 2015 -0700 +++ b/Lib/mk20dx256vlh7.bootloader.ld Fri Jun 12 18:31:55 2015 -0700 @@ -55,8 +55,8 @@ . = 0; KEEP(* (.vectors)) *(.startup*) + . = 0x400; *(.rodata*) - . = 0x400; KEEP(* (.flashconfig)) *(.text*) . = ALIGN(4);
--- a/LoadFile/load.teensy Sun Mar 08 22:35:55 2015 -0700 +++ b/LoadFile/load.teensy Fri Jun 12 18:31:55 2015 -0700 @@ -69,7 +69,7 @@ # Load Screen Session if specified if (( "$EXIT_STATUS" == "0" )) && [[ "$AUTO_SCREEN_SESSION" != "" ]]; then if type screen &>/dev/null; then - sleep 0.1 + sleep 2 screen $AUTO_SCREEN_SESSION else echo "screen is not installed"
--- a/LoadFile/teensy_loader_cli.c Sun Mar 08 22:35:55 2015 -0700 +++ b/LoadFile/teensy_loader_cli.c Fri Jun 12 18:31:55 2015 -0700 @@ -134,7 +134,7 @@ num = read_intel_hex(filename); if (num < 0) die("error reading intel hex file \"%s\"", filename); printf_verbose("Read \"%s\": %d bytes, %.1f%% usage\n", - filename, num, (double)num / (double)code_size * 100.0); + filename, num, (double)num / (double)code_size * 100.0); } // program the data @@ -690,23 +690,23 @@ parse_hex_line(char *line) { int addr, code, num; - int sum, len, cksum, i; - char *ptr; + int sum, len, cksum, i; + char *ptr; - num = 0; - if (line[0] != ':') return 0; - if (strlen(line) < 11) return 0; - ptr = line+1; - if (!sscanf(ptr, "%02x", &len)) return 0; - ptr += 2; - if ((int)strlen(line) < (11 + (len * 2)) ) return 0; - if (!sscanf(ptr, "%04x", &addr)) return 0; - ptr += 4; - /* printf("Line: length=%d Addr=%d\n", len, addr); */ - if (!sscanf(ptr, "%02x", &code)) return 0; + num = 0; + if (line[0] != ':') return 0; + if (strlen(line) < 11) return 0; + ptr = line+1; + if (!sscanf(ptr, "%02x", &len)) return 0; + ptr += 2; + if ((int)strlen(line) < (11 + (len * 2)) ) return 0; + if (!sscanf(ptr, "%04x", &addr)) return 0; + ptr += 4; + /* printf("Line: length=%d Addr=%d\n", len, addr); */ + if (!sscanf(ptr, "%02x", &code)) return 0; if (addr + extended_addr + len >= MAX_MEMORY_SIZE) return 0; - ptr += 2; - sum = (len & 255) + ((addr >> 8) & 255) + (addr & 255) + (code & 255); + ptr += 2; + sum = (len & 255) + ((addr >> 8) & 255) + (addr & 255) + (code & 255); if (code != 0) { if (code == 1) { end_record_seen = 1; @@ -716,7 +716,7 @@ if (!sscanf(ptr, "%04x", &i)) return 1; ptr += 4; sum += ((i >> 8) & 255) + (i & 255); - if (!sscanf(ptr, "%02x", &cksum)) return 1; + if (!sscanf(ptr, "%02x", &cksum)) return 1; if (((sum & 255) + (cksum & 255)) & 255) return 1; extended_addr = i << 4; //printf("ext addr = %05X\n", extended_addr); @@ -725,27 +725,27 @@ if (!sscanf(ptr, "%04x", &i)) return 1; ptr += 4; sum += ((i >> 8) & 255) + (i & 255); - if (!sscanf(ptr, "%02x", &cksum)) return 1; + if (!sscanf(ptr, "%02x", &cksum)) return 1; if (((sum & 255) + (cksum & 255)) & 255) return 1; extended_addr = i << 16; //printf("ext addr = %08X\n", extended_addr); } - return 1; // non-data line + return 1; // non-data line } byte_count += len; - while (num != len) { - if (sscanf(ptr, "%02x", &i) != 1) return 0; + while (num != len) { + if (sscanf(ptr, "%02x", &i) != 1) return 0; i &= 255; firmware_image[addr + extended_addr + num] = i; firmware_mask[addr + extended_addr + num] = 1; - ptr += 2; - sum += i; - (num)++; - if (num >= 256) return 0; - } - if (!sscanf(ptr, "%02x", &cksum)) return 0; - if (((sum & 255) + (cksum & 255)) & 255) return 0; /* checksum error */ - return 1; + ptr += 2; + sum += i; + (num)++; + if (num >= 256) return 0; + } + if (!sscanf(ptr, "%02x", &cksum)) return 0; + if (((sum & 255) + (cksum & 255)) & 255) return 0; /* checksum error */ + return 1; } int ihex_bytes_within_range(int begin, int end)
--- a/Macro/PartialMap/macro.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Macro/PartialMap/macro.c Fri Jun 12 18:31:55 2015 -0700 @@ -393,6 +393,16 @@ } +// Update the scancode using a list of TriggerGuides +// TODO Handle led state and analog +inline void Macro_triggerState( void *triggers, uint8_t num ) +{ + // Copy each of the TriggerGuides to the TriggerListBuffer + for ( uint8_t c = 0; c < num; c++ ) + macroTriggerListBuffer[ macroTriggerListBufferSize++ ] = ((TriggerGuide*)triggers)[ c ]; +} + + // Update the scancode key state // States: // * 0x00 - Off
--- a/Macro/PartialMap/macro.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Macro/PartialMap/macro.h Fri Jun 12 18:31:55 2015 -0700 @@ -35,9 +35,10 @@ // ----- Functions ----- +void Macro_analogState( uint8_t scanCode, uint8_t state ); void Macro_keyState( uint8_t scanCode, uint8_t state ); -void Macro_analogState( uint8_t scanCode, uint8_t state ); void Macro_ledState( uint8_t ledCode, uint8_t state ); +void Macro_triggerState( void *triggers, uint8_t num ); // triggers is of type TriggerGuide, void* for circular dependencies void Macro_process(); void Macro_setup();
--- a/Macro/buffer/Keymap/usb_keys.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Macro/buffer/Keymap/usb_keys.h Fri Jun 12 18:31:55 2015 -0700 @@ -27,8 +27,8 @@ // List of Modifiers #define KEY_CTRL 0x01 #define KEY_SHIFT 0x02 -#define KEY_ALT 0x04 -#define KEY_GUI 0x08 +#define KEY_ALT 0x04 +#define KEY_GUI 0x08 #define KEY_LEFT_CTRL 0x01 #define KEY_LEFT_SHIFT 0x02 #define KEY_LEFT_ALT 0x04
--- a/Output/pjrcUSB/arm/usb_desc.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/pjrcUSB/arm/usb_desc.c Fri Jun 12 18:31:55 2015 -0700 @@ -48,33 +48,33 @@ // USB Device Descriptor. The USB host reads this first, to learn // what type of device is connected. static uint8_t device_descriptor[] = { - 18, // bLength - 1, // bDescriptorType - 0x00, 0x02, // bcdUSB - DEVICE_CLASS, // bDeviceClass - DEVICE_SUBCLASS, // bDeviceSubClass - DEVICE_PROTOCOL, // bDeviceProtocol - EP0_SIZE, // bMaxPacketSize0 - LSB(VENDOR_ID), MSB(VENDOR_ID), // idVendor - LSB(PRODUCT_ID), MSB(PRODUCT_ID), // idProduct - 0x00, 0x01, // bcdDevice - 1, // iManufacturer - 2, // iProduct - 3, // iSerialNumber - 1 // bNumConfigurations + 18, // bLength + 1, // bDescriptorType + 0x00, 0x02, // bcdUSB + DEVICE_CLASS, // bDeviceClass + DEVICE_SUBCLASS, // bDeviceSubClass + DEVICE_PROTOCOL, // bDeviceProtocol + EP0_SIZE, // bMaxPacketSize0 + LSB(VENDOR_ID), MSB(VENDOR_ID), // idVendor + LSB(PRODUCT_ID), MSB(PRODUCT_ID), // idProduct + 0x00, 0x01, // bcdDevice + 1, // iManufacturer + 2, // iProduct + 3, // iSerialNumber + 1 // bNumConfigurations }; // USB Device Qualifier Descriptor static uint8_t device_qualifier_descriptor[] = { 0 // Indicate only single speed /* Device qualifier example (used for specifying multiple USB speeds) - 10, // bLength - 6, // bDescriptorType - 0x00, 0x02, // bcdUSB - DEVICE_CLASS, // bDeviceClass - DEVICE_SUBCLASS, // bDeviceSubClass - DEVICE_PROTOCOL, // bDeviceProtocol - EP0_SIZE, // bMaxPacketSize0 + 10, // bLength + 6, // bDescriptorType + 0x00, 0x02, // bcdUSB + DEVICE_CLASS, // bDeviceClass + DEVICE_SUBCLASS, // bDeviceSubClass + DEVICE_PROTOCOL, // bDeviceProtocol + EP0_SIZE, // bMaxPacketSize0 0, // bNumOtherSpeedConfigurations 0 // bReserved */ @@ -102,70 +102,70 @@ // Keyboard Protocol 1, HID 1.11 spec, Appendix B, page 59-60 static uint8_t keyboard_report_desc[] = { // Keyboard Collection - 0x05, 0x01, // Usage Page (Generic Desktop), - 0x09, 0x06, // Usage (Keyboard), - 0xA1, 0x01, // Collection (Application) - Keyboard, + 0x05, 0x01, // Usage Page (Generic Desktop), + 0x09, 0x06, // Usage (Keyboard), + 0xA1, 0x01, // Collection (Application) - Keyboard, // Modifier Byte - 0x75, 0x01, // Report Size (1), - 0x95, 0x08, // Report Count (8), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0xE0, // Usage Minimum (224), - 0x29, 0xE7, // Usage Maximum (231), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x81, 0x02, // Input (Data, Variable, Absolute), + 0x75, 0x01, // Report Size (1), + 0x95, 0x08, // Report Count (8), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0xE0, // Usage Minimum (224), + 0x29, 0xE7, // Usage Maximum (231), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x81, 0x02, // Input (Data, Variable, Absolute), // Reserved Byte - 0x75, 0x08, // Report Size (8), - 0x95, 0x01, // Report Count (1), - 0x81, 0x03, // Output (Constant), + 0x75, 0x08, // Report Size (8), + 0x95, 0x01, // Report Count (1), + 0x81, 0x03, // Output (Constant), // LED Report - 0x75, 0x01, // Report Size (1), - 0x95, 0x05, // Report Count (5), - 0x05, 0x08, // Usage Page (LEDs), - 0x19, 0x01, // Usage Minimum (1), - 0x29, 0x05, // Usage Maximum (5), - 0x91, 0x02, // Output (Data, Variable, Absolute), + 0x75, 0x01, // Report Size (1), + 0x95, 0x05, // Report Count (5), + 0x05, 0x08, // Usage Page (LEDs), + 0x19, 0x01, // Usage Minimum (1), + 0x29, 0x05, // Usage Maximum (5), + 0x91, 0x02, // Output (Data, Variable, Absolute), // LED Report Padding - 0x75, 0x03, // Report Size (3), - 0x95, 0x01, // Report Count (1), - 0x91, 0x03, // Output (Constant), + 0x75, 0x03, // Report Size (3), + 0x95, 0x01, // Report Count (1), + 0x91, 0x03, // Output (Constant), // Normal Keys - 0x75, 0x08, // Report Size (8), - 0x95, 0x06, // Report Count (6), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x7F, // Logical Maximum(104), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0x00, // Usage Minimum (0), - 0x29, 0x7F, // Usage Maximum (104), - 0x81, 0x00, // Input (Data, Array), - 0xc0, // End Collection - Keyboard + 0x75, 0x08, // Report Size (8), + 0x95, 0x06, // Report Count (6), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x7F, // Logical Maximum(104), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0x00, // Usage Minimum (0), + 0x29, 0x7F, // Usage Maximum (104), + 0x81, 0x00, // Input (Data, Array), + 0xc0, // End Collection - Keyboard }; // Keyboard Protocol 1, HID 1.11 spec, Appendix B, page 59-60 static uint8_t nkro_keyboard_report_desc[] = { // Keyboard Collection - 0x05, 0x01, // Usage Page (Generic Desktop), - 0x09, 0x06, // Usage (Keyboard), - 0xA1, 0x01, // Collection (Application) - Keyboard, + 0x05, 0x01, // Usage Page (Generic Desktop), + 0x09, 0x06, // Usage (Keyboard), + 0xA1, 0x01, // Collection (Application) - Keyboard, // LED Report - 0x85, 0x01, // Report ID (1), - 0x75, 0x01, // Report Size (1), - 0x95, 0x05, // Report Count (5), - 0x05, 0x08, // Usage Page (LEDs), - 0x19, 0x01, // Usage Minimum (1), - 0x29, 0x05, // Usage Maximum (5), - 0x91, 0x02, // Output (Data, Variable, Absolute), + 0x85, 0x01, // Report ID (1), + 0x75, 0x01, // Report Size (1), + 0x95, 0x05, // Report Count (5), + 0x05, 0x08, // Usage Page (LEDs), + 0x19, 0x01, // Usage Minimum (1), + 0x29, 0x05, // Usage Maximum (5), + 0x91, 0x02, // Output (Data, Variable, Absolute), // LED Report Padding - 0x75, 0x03, // Report Size (3), - 0x95, 0x01, // Report Count (1), - 0x91, 0x03, // Output (Constant), + 0x75, 0x03, // Report Size (3), + 0x95, 0x01, // Report Count (1), + 0x91, 0x03, // Output (Constant), // Normal Keys - Using an NKRO Bitmap // @@ -196,24 +196,24 @@ // 224-231 : 1 byte (0xE0-0xE7) ( 8 bits) // Modifier Byte - 0x75, 0x01, // Report Size (1), - 0x95, 0x08, // Report Count (8), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0xE0, // Usage Minimum (224), - 0x29, 0xE7, // Usage Maximum (231), - 0x81, 0x02, // Input (Data, Variable, Absolute), + 0x75, 0x01, // Report Size (1), + 0x95, 0x08, // Report Count (8), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0xE0, // Usage Minimum (224), + 0x29, 0xE7, // Usage Maximum (231), + 0x81, 0x02, // Input (Data, Variable, Absolute), // 4-49 (6 bytes/46 bits) - MainKeys - 0x75, 0x01, // Report Size (1), - 0x95, 0x2E, // Report Count (46), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0x04, // Usage Minimum (4), - 0x29, 0x31, // Usage Maximum (49), - 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), + 0x75, 0x01, // Report Size (1), + 0x95, 0x2E, // Report Count (46), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0x04, // Usage Minimum (4), + 0x29, 0x31, // Usage Maximum (49), + 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), // Padding (2 bits) 0x75, 0x02, // Report Size (2), @@ -221,14 +221,14 @@ 0x81, 0x03, // Input (Constant), // 51-155 (14 bytes/105 bits) - SecondaryKeys - 0x75, 0x01, // Report Size (1), - 0x95, 0x69, // Report Count (105), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0x33, // Usage Minimum (51), - 0x29, 0x9B, // Usage Maximum (155), - 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), + 0x75, 0x01, // Report Size (1), + 0x95, 0x69, // Report Count (105), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0x33, // Usage Minimum (51), + 0x29, 0x9B, // Usage Maximum (155), + 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), // Padding (7 bits) 0x75, 0x07, // Report Size (7), @@ -236,101 +236,101 @@ 0x81, 0x03, // Input (Constant), // 157-164 (1 byte/8 bits) - TertiaryKeys - 0x75, 0x01, // Report Size (1), - 0x95, 0x08, // Report Count (8), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0x9D, // Usage Minimum (157), - 0x29, 0xA4, // Usage Maximum (164), - 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), + 0x75, 0x01, // Report Size (1), + 0x95, 0x08, // Report Count (8), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0x9D, // Usage Minimum (157), + 0x29, 0xA4, // Usage Maximum (164), + 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), // 176-221 (6 bytes/46 bits) - QuartiaryKeys - 0x75, 0x01, // Report Size (1), - 0x95, 0x2E, // Report Count (46), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0xB0, // Usage Minimum (176), - 0x29, 0xDD, // Usage Maximum (221), - 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), + 0x75, 0x01, // Report Size (1), + 0x95, 0x2E, // Report Count (46), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0xB0, // Usage Minimum (176), + 0x29, 0xDD, // Usage Maximum (221), + 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), // Padding (2 bits) 0x75, 0x02, // Report Size (2), 0x95, 0x01, // Report Count (1), 0x81, 0x03, // Input (Constant), - 0xc0, // End Collection - Keyboard + 0xc0, // End Collection - Keyboard // System Control Collection // // NOTES: // Not bothering with NKRO for this table. If there's need, I can implement it. -HaaTa // Using a 1KRO scheme - 0x05, 0x01, // Usage Page (Generic Desktop), - 0x09, 0x80, // Usage (System Control), - 0xA1, 0x01, // Collection (Application), - 0x85, 0x02, // Report ID (2), - 0x75, 0x08, // Report Size (8), - 0x95, 0x01, // Report Count (1), - 0x16, 0x81, 0x00, // Logical Minimum (129), - 0x26, 0xB7, 0x00, // Logical Maximum (183), - 0x19, 0x81, // Usage Minimum (129), - 0x29, 0xB7, // Usage Maximum (183), - 0x81, 0x00, // Input (Data, Array), - 0xc0, // End Collection - System Control + 0x05, 0x01, // Usage Page (Generic Desktop), + 0x09, 0x80, // Usage (System Control), + 0xA1, 0x01, // Collection (Application), + 0x85, 0x02, // Report ID (2), + 0x75, 0x08, // Report Size (8), + 0x95, 0x01, // Report Count (1), + 0x16, 0x81, 0x00, // Logical Minimum (129), + 0x26, 0xB7, 0x00, // Logical Maximum (183), + 0x19, 0x81, // Usage Minimum (129), + 0x29, 0xB7, // Usage Maximum (183), + 0x81, 0x00, // Input (Data, Array), + 0xc0, // End Collection - System Control // Consumer Control Collection - Media Keys // // NOTES: // Not bothering with NKRO for this table. If there's a need, I can implement it. -HaaTa // Using a 1KRO scheme - 0x05, 0x0c, // Usage Page (Consumer), - 0x09, 0x01, // Usage (Consumer Control), - 0xA1, 0x01, // Collection (Application), - 0x85, 0x03, // Report ID (3), - 0x75, 0x10, // Report Size (16), - 0x95, 0x01, // Report Count (1), - 0x16, 0x20, 0x00, // Logical Minimum (32), - 0x26, 0x9C, 0x02, // Logical Maximum (668), - 0x05, 0x0C, // Usage Page (Consumer), - 0x19, 0x20, // Usage Minimum (32), - 0x2A, 0x9C, 0x02, // Usage Maximum (668), - 0x81, 0x00, // Input (Data, Array), - 0xc0, // End Collection - Consumer Control + 0x05, 0x0c, // Usage Page (Consumer), + 0x09, 0x01, // Usage (Consumer Control), + 0xA1, 0x01, // Collection (Application), + 0x85, 0x03, // Report ID (3), + 0x75, 0x10, // Report Size (16), + 0x95, 0x01, // Report Count (1), + 0x16, 0x20, 0x00, // Logical Minimum (32), + 0x26, 0x9C, 0x02, // Logical Maximum (668), + 0x05, 0x0C, // Usage Page (Consumer), + 0x19, 0x20, // Usage Minimum (32), + 0x2A, 0x9C, 0x02, // Usage Maximum (668), + 0x81, 0x00, // Input (Data, Array), + 0xc0, // End Collection - Consumer Control }; /* MOUSE // Mouse Protocol 1, HID 1.11 spec, Appendix B, page 59-60, with wheel extension static uint8_t mouse_report_desc[] = { - 0x05, 0x01, // Usage Page (Generic Desktop) - 0x09, 0x02, // Usage (Mouse) - 0xA1, 0x01, // Collection (Application) - 0x05, 0x09, // Usage Page (Button) - 0x19, 0x01, // Usage Minimum (Button #1) - 0x29, 0x03, // Usage Maximum (Button #3) - 0x15, 0x00, // Logical Minimum (0) - 0x25, 0x01, // Logical Maximum (1) - 0x95, 0x03, // Report Count (3) - 0x75, 0x01, // Report Size (1) - 0x81, 0x02, // Input (Data, Variable, Absolute) - 0x95, 0x01, // Report Count (1) - 0x75, 0x05, // Report Size (5) - 0x81, 0x03, // Input (Constant) - 0x05, 0x01, // Usage Page (Generic Desktop) - 0x09, 0x30, // Usage (X) - 0x09, 0x31, // Usage (Y) - 0x15, 0x00, // Logical Minimum (0) - 0x26, 0xFF, 0x7F, // Logical Maximum (32767) - 0x75, 0x10, // Report Size (16), - 0x95, 0x02, // Report Count (2), - 0x81, 0x02, // Input (Data, Variable, Absolute) - 0x09, 0x38, // Usage (Wheel) - 0x15, 0x81, // Logical Minimum (-127) - 0x25, 0x7F, // Logical Maximum (127) - 0x75, 0x08, // Report Size (8), - 0x95, 0x01, // Report Count (1), - 0x81, 0x06, // Input (Data, Variable, Relative) - 0xC0 // End Collection + 0x05, 0x01, // Usage Page (Generic Desktop) + 0x09, 0x02, // Usage (Mouse) + 0xA1, 0x01, // Collection (Application) + 0x05, 0x09, // Usage Page (Button) + 0x19, 0x01, // Usage Minimum (Button #1) + 0x29, 0x03, // Usage Maximum (Button #3) + 0x15, 0x00, // Logical Minimum (0) + 0x25, 0x01, // Logical Maximum (1) + 0x95, 0x03, // Report Count (3) + 0x75, 0x01, // Report Size (1) + 0x81, 0x02, // Input (Data, Variable, Absolute) + 0x95, 0x01, // Report Count (1) + 0x75, 0x05, // Report Size (5) + 0x81, 0x03, // Input (Constant) + 0x05, 0x01, // Usage Page (Generic Desktop) + 0x09, 0x30, // Usage (X) + 0x09, 0x31, // Usage (Y) + 0x15, 0x00, // Logical Minimum (0) + 0x26, 0xFF, 0x7F, // Logical Maximum (32767) + 0x75, 0x10, // Report Size (16), + 0x95, 0x02, // Report Count (2), + 0x81, 0x02, // Input (Data, Variable, Absolute) + 0x09, 0x38, // Usage (Wheel) + 0x15, 0x81, // Logical Minimum (-127) + 0x25, 0x7F, // Logical Maximum (127) + 0x75, 0x08, // Report Size (8), + 0x95, 0x01, // Report Count (1), + 0x81, 0x06, // Input (Data, Variable, Relative) + 0xC0 // End Collection }; */ @@ -343,196 +343,196 @@ static uint8_t config_descriptor[CONFIG_DESC_SIZE] = { // --- Configuration --- // - 9 bytes - - // configuration descriptor, USB spec 9.6.3, page 264-266, Table 9-10 - 9, // bLength; - 2, // bDescriptorType; - LSB(CONFIG_DESC_SIZE), // wTotalLength - MSB(CONFIG_DESC_SIZE), - NUM_INTERFACE, // bNumInterfaces - 1, // bConfigurationValue - 0, // iConfiguration - 0xA0, // bmAttributes - 250, // bMaxPower + // configuration descriptor, USB spec 9.6.3, page 264-266, Table 9-10 + 9, // bLength; + 2, // bDescriptorType; + LSB(CONFIG_DESC_SIZE), // wTotalLength + MSB(CONFIG_DESC_SIZE), + NUM_INTERFACE, // bNumInterfaces + 1, // bConfigurationValue + 0, // iConfiguration + 0xA0, // bmAttributes + 250, // bMaxPower // --- Keyboard HID --- Boot Mode Keyboard Interface // - 9 bytes - - // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 - 9, // bLength - 4, // bDescriptorType - KEYBOARD_INTERFACE, // bInterfaceNumber - 0, // bAlternateSetting - 1, // bNumEndpoints - 0x03, // bInterfaceClass (0x03 = HID) - 0x01, // bInterfaceSubClass (0x00 = Non-Boot, 0x01 = Boot) - 0x01, // bInterfaceProtocol (0x01 = Keyboard) - 0, // iInterface + // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 + 9, // bLength + 4, // bDescriptorType + KEYBOARD_INTERFACE, // bInterfaceNumber + 0, // bAlternateSetting + 1, // bNumEndpoints + 0x03, // bInterfaceClass (0x03 = HID) + 0x01, // bInterfaceSubClass (0x00 = Non-Boot, 0x01 = Boot) + 0x01, // bInterfaceProtocol (0x01 = Keyboard) + 0, // iInterface // - 9 bytes - - // HID interface descriptor, HID 1.11 spec, section 6.2.1 - 9, // bLength - 0x21, // bDescriptorType - 0x11, 0x01, // bcdHID - 0, // bCountryCode - 1, // bNumDescriptors - 0x22, // bDescriptorType - LSB(sizeof(keyboard_report_desc)), // wDescriptorLength - MSB(sizeof(keyboard_report_desc)), + // HID interface descriptor, HID 1.11 spec, section 6.2.1 + 9, // bLength + 0x21, // bDescriptorType + 0x11, 0x01, // bcdHID + 0, // bCountryCode + 1, // bNumDescriptors + 0x22, // bDescriptorType + LSB(sizeof(keyboard_report_desc)), // wDescriptorLength + MSB(sizeof(keyboard_report_desc)), // - 7 bytes - - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - KEYBOARD_ENDPOINT | 0x80, // bEndpointAddress - 0x03, // bmAttributes (0x03=intr) - KEYBOARD_SIZE, 0, // wMaxPacketSize - KEYBOARD_INTERVAL, // bInterval + // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 + 7, // bLength + 5, // bDescriptorType + KEYBOARD_ENDPOINT | 0x80, // bEndpointAddress + 0x03, // bmAttributes (0x03=intr) + KEYBOARD_SIZE, 0, // wMaxPacketSize + KEYBOARD_INTERVAL, // bInterval // --- NKRO Keyboard HID --- OS Mode Keyboard Interface // - 9 bytes - - // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 - 9, // bLength - 4, // bDescriptorType - NKRO_KEYBOARD_INTERFACE, // bInterfaceNumber - 0, // bAlternateSetting - 1, // bNumEndpoints - 0x03, // bInterfaceClass (0x03 = HID) - 0x00, // bInterfaceSubClass (0x00 = Non-Boot, 0x01 = Boot) - 0x01, // bInterfaceProtocol (0x01 = Keyboard) - 0, // iInterface + // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 + 9, // bLength + 4, // bDescriptorType + NKRO_KEYBOARD_INTERFACE, // bInterfaceNumber + 0, // bAlternateSetting + 1, // bNumEndpoints + 0x03, // bInterfaceClass (0x03 = HID) + 0x00, // bInterfaceSubClass (0x00 = Non-Boot, 0x01 = Boot) + 0x01, // bInterfaceProtocol (0x01 = Keyboard) + 0, // iInterface // - 9 bytes - - // HID interface descriptor, HID 1.11 spec, section 6.2.1 - 9, // bLength - 0x21, // bDescriptorType - 0x11, 0x01, // bcdHID - 0, // bCountryCode - 1, // bNumDescriptors - 0x22, // bDescriptorType - LSB(sizeof(nkro_keyboard_report_desc)), // wDescriptorLength - MSB(sizeof(nkro_keyboard_report_desc)), + // HID interface descriptor, HID 1.11 spec, section 6.2.1 + 9, // bLength + 0x21, // bDescriptorType + 0x11, 0x01, // bcdHID + 0, // bCountryCode + 1, // bNumDescriptors + 0x22, // bDescriptorType + LSB(sizeof(nkro_keyboard_report_desc)), // wDescriptorLength + MSB(sizeof(nkro_keyboard_report_desc)), // - 7 bytes - - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - NKRO_KEYBOARD_ENDPOINT | 0x80, // bEndpointAddress - 0x03, // bmAttributes (0x03=intr) - NKRO_KEYBOARD_SIZE, 0, // wMaxPacketSize - NKRO_KEYBOARD_INTERVAL, // bInterval + // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 + 7, // bLength + 5, // bDescriptorType + NKRO_KEYBOARD_ENDPOINT | 0x80, // bEndpointAddress + 0x03, // bmAttributes (0x03=intr) + NKRO_KEYBOARD_SIZE, 0, // wMaxPacketSize + NKRO_KEYBOARD_INTERVAL, // bInterval // --- Serial CDC --- CDC IAD Descriptor // - 8 bytes - - // interface association descriptor, USB ECN, Table 9-Z - 8, // bLength - 11, // bDescriptorType - CDC_STATUS_INTERFACE, // bFirstInterface - 2, // bInterfaceCount - 0x02, // bFunctionClass - 0x02, // bFunctionSubClass - 0x01, // bFunctionProtocol - 0, // iFunction + // interface association descriptor, USB ECN, Table 9-Z + 8, // bLength + 11, // bDescriptorType + CDC_STATUS_INTERFACE, // bFirstInterface + 2, // bInterfaceCount + 0x02, // bFunctionClass + 0x02, // bFunctionSubClass + 0x01, // bFunctionProtocol + 0, // iFunction // --- Serial CDC --- CDC Data Interface // - 9 bytes - - // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 - 9, // bLength - 4, // bDescriptorType - CDC_STATUS_INTERFACE, // bInterfaceNumber - 0, // bAlternateSetting - 1, // bNumEndpoints - 0x02, // bInterfaceClass - 0x02, // bInterfaceSubClass - 0x01, // bInterfaceProtocol - 0, // iInterface + // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 + 9, // bLength + 4, // bDescriptorType + CDC_STATUS_INTERFACE, // bInterfaceNumber + 0, // bAlternateSetting + 1, // bNumEndpoints + 0x02, // bInterfaceClass + 0x02, // bInterfaceSubClass + 0x01, // bInterfaceProtocol + 0, // iInterface // - 5 bytes - - // CDC Header Functional Descriptor, CDC Spec 5.2.3.1, Table 26 - 5, // bFunctionLength - 0x24, // bDescriptorType - 0x00, // bDescriptorSubtype - 0x10, 0x01, // bcdCDC + // CDC Header Functional Descriptor, CDC Spec 5.2.3.1, Table 26 + 5, // bFunctionLength + 0x24, // bDescriptorType + 0x00, // bDescriptorSubtype + 0x10, 0x01, // bcdCDC // - 5 bytes - - // Call Management Functional Descriptor, CDC Spec 5.2.3.2, Table 27 - 5, // bFunctionLength - 0x24, // bDescriptorType - 0x01, // bDescriptorSubtype - 0x01, // bmCapabilities - CDC_DATA_INTERFACE, // bDataInterface + // Call Management Functional Descriptor, CDC Spec 5.2.3.2, Table 27 + 5, // bFunctionLength + 0x24, // bDescriptorType + 0x01, // bDescriptorSubtype + 0x01, // bmCapabilities + CDC_DATA_INTERFACE, // bDataInterface // - 4 bytes - - // Abstract Control Management Functional Descriptor, CDC Spec 5.2.3.3, Table 28 - 4, // bFunctionLength - 0x24, // bDescriptorType - 0x02, // bDescriptorSubtype - 0x06, // bmCapabilities + // Abstract Control Management Functional Descriptor, CDC Spec 5.2.3.3, Table 28 + 4, // bFunctionLength + 0x24, // bDescriptorType + 0x02, // bDescriptorSubtype + 0x06, // bmCapabilities // - 5 bytes - - // Union Functional Descriptor, CDC Spec 5.2.3.8, Table 33 - 5, // bFunctionLength - 0x24, // bDescriptorType - 0x06, // bDescriptorSubtype - CDC_STATUS_INTERFACE, // bMasterInterface - CDC_DATA_INTERFACE, // bSlaveInterface0 + // Union Functional Descriptor, CDC Spec 5.2.3.8, Table 33 + 5, // bFunctionLength + 0x24, // bDescriptorType + 0x06, // bDescriptorSubtype + CDC_STATUS_INTERFACE, // bMasterInterface + CDC_DATA_INTERFACE, // bSlaveInterface0 // - 7 bytes - - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - CDC_ACM_ENDPOINT | 0x80, // bEndpointAddress - 0x03, // bmAttributes (0x03=intr) - CDC_ACM_SIZE, 0, // wMaxPacketSize - 64, // bInterval + // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 + 7, // bLength + 5, // bDescriptorType + CDC_ACM_ENDPOINT | 0x80, // bEndpointAddress + 0x03, // bmAttributes (0x03=intr) + CDC_ACM_SIZE, 0, // wMaxPacketSize + 64, // bInterval // - 9 bytes - - // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 - 9, // bLength - 4, // bDescriptorType - CDC_DATA_INTERFACE, // bInterfaceNumber - 0, // bAlternateSetting - 2, // bNumEndpoints - 0x0A, // bInterfaceClass - 0x00, // bInterfaceSubClass - 0x00, // bInterfaceProtocol - 0, // iInterface + // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 + 9, // bLength + 4, // bDescriptorType + CDC_DATA_INTERFACE, // bInterfaceNumber + 0, // bAlternateSetting + 2, // bNumEndpoints + 0x0A, // bInterfaceClass + 0x00, // bInterfaceSubClass + 0x00, // bInterfaceProtocol + 0, // iInterface // - 7 bytes - - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - CDC_RX_ENDPOINT, // bEndpointAddress - 0x02, // bmAttributes (0x02=bulk) - CDC_RX_SIZE, 0, // wMaxPacketSize - 0, // bInterval + // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 + 7, // bLength + 5, // bDescriptorType + CDC_RX_ENDPOINT, // bEndpointAddress + 0x02, // bmAttributes (0x02=bulk) + CDC_RX_SIZE, 0, // wMaxPacketSize + 0, // bInterval // - 7 bytes - - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - CDC_TX_ENDPOINT | 0x80, // bEndpointAddress - 0x02, // bmAttributes (0x02=bulk) - CDC_TX_SIZE, 0, // wMaxPacketSize - 0, // bInterval + // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 + 7, // bLength + 5, // bDescriptorType + CDC_TX_ENDPOINT | 0x80, // bEndpointAddress + 0x02, // bmAttributes (0x02=bulk) + CDC_TX_SIZE, 0, // wMaxPacketSize + 0, // bInterval /* // Mouse Interface // - 9 bytes - - // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 - 9, // bLength - 4, // bDescriptorType - MOUSE_INTERFACE, // bInterfaceNumber - 0, // bAlternateSetting - 1, // bNumEndpoints - 0x03, // bInterfaceClass (0x03 = HID) - 0x00, // bInterfaceSubClass (0x01 = Boot) - 0x00, // bInterfaceProtocol (0x02 = Mouse) - 0, // iInterface + // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 + 9, // bLength + 4, // bDescriptorType + MOUSE_INTERFACE, // bInterfaceNumber + 0, // bAlternateSetting + 1, // bNumEndpoints + 0x03, // bInterfaceClass (0x03 = HID) + 0x00, // bInterfaceSubClass (0x01 = Boot) + 0x00, // bInterfaceProtocol (0x02 = Mouse) + 0, // iInterface // - 9 bytes - - // HID interface descriptor, HID 1.11 spec, section 6.2.1 - 9, // bLength - 0x21, // bDescriptorType - 0x11, 0x01, // bcdHID - 0, // bCountryCode - 1, // bNumDescriptors - 0x22, // bDescriptorType - LSB(sizeof(mouse_report_desc)), // wDescriptorLength - MSB(sizeof(mouse_report_desc)), + // HID interface descriptor, HID 1.11 spec, section 6.2.1 + 9, // bLength + 0x21, // bDescriptorType + 0x11, 0x01, // bcdHID + 0, // bCountryCode + 1, // bNumDescriptors + 0x22, // bDescriptorType + LSB(sizeof(mouse_report_desc)), // wDescriptorLength + MSB(sizeof(mouse_report_desc)), // - 7 bytes - - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - MOUSE_ENDPOINT | 0x80, // bEndpointAddress - 0x03, // bmAttributes (0x03=intr) - MOUSE_SIZE, 0, // wMaxPacketSize - MOUSE_INTERVAL, // bInterval + // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 + 7, // bLength + 5, // bDescriptorType + MOUSE_ENDPOINT | 0x80, // bEndpointAddress + 0x03, // bmAttributes (0x03=intr) + MOUSE_SIZE, 0, // wMaxPacketSize + MOUSE_INTERVAL, // bInterval #endif // MOUSE_INTERFACE */ }; @@ -546,37 +546,37 @@ // actual string data struct usb_string_descriptor_struct { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wString[]; + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wString[]; }; extern struct usb_string_descriptor_struct usb_string_manufacturer_name - __attribute__ ((weak, alias("usb_string_manufacturer_name_default"))); + __attribute__ ((weak, alias("usb_string_manufacturer_name_default"))); extern struct usb_string_descriptor_struct usb_string_product_name - __attribute__ ((weak, alias("usb_string_product_name_default"))); + __attribute__ ((weak, alias("usb_string_product_name_default"))); extern struct usb_string_descriptor_struct usb_string_serial_number - __attribute__ ((weak, alias("usb_string_serial_number_default"))); + __attribute__ ((weak, alias("usb_string_serial_number_default"))); struct usb_string_descriptor_struct string0 = { - 4, - 3, - {0x0409} + 4, + 3, + {0x0409} }; struct usb_string_descriptor_struct usb_string_manufacturer_name_default = { - sizeof(STR_MANUFACTURER), - 3, - {STR_MANUFACTURER} + sizeof(STR_MANUFACTURER), + 3, + {STR_MANUFACTURER} }; struct usb_string_descriptor_struct usb_string_product_name_default = { sizeof(STR_PRODUCT), - 3, - {STR_PRODUCT} + 3, + {STR_PRODUCT} }; struct usb_string_descriptor_struct usb_string_serial_number_default = { sizeof(STR_SERIAL), - 3, + 3, {STR_SERIAL} }; @@ -592,18 +592,18 @@ {0x0200, 0x0000, config_descriptor, sizeof(config_descriptor)}, {0x0600, 0x0000, device_qualifier_descriptor, sizeof(device_qualifier_descriptor)}, {0x0A00, 0x0000, usb_debug_descriptor, sizeof(usb_debug_descriptor)}, - {0x2200, KEYBOARD_INTERFACE, keyboard_report_desc, sizeof(keyboard_report_desc)}, - {0x2100, KEYBOARD_INTERFACE, config_descriptor + KEYBOARD_DESC_OFFSET, 9}, - {0x2200, NKRO_KEYBOARD_INTERFACE, nkro_keyboard_report_desc, sizeof(nkro_keyboard_report_desc)}, - {0x2100, NKRO_KEYBOARD_INTERFACE, config_descriptor + NKRO_KEYBOARD_DESC_OFFSET, 9}, + {0x2200, KEYBOARD_INTERFACE, keyboard_report_desc, sizeof(keyboard_report_desc)}, + {0x2100, KEYBOARD_INTERFACE, config_descriptor + KEYBOARD_DESC_OFFSET, 9}, + {0x2200, NKRO_KEYBOARD_INTERFACE, nkro_keyboard_report_desc, sizeof(nkro_keyboard_report_desc)}, + {0x2100, NKRO_KEYBOARD_INTERFACE, config_descriptor + NKRO_KEYBOARD_DESC_OFFSET, 9}, /* MOUSE - {0x2200, MOUSE_INTERFACE, mouse_report_desc, sizeof(mouse_report_desc)}, - {0x2100, MOUSE_INTERFACE, config_descriptor+MOUSE_DESC_OFFSET, 9}, + {0x2200, MOUSE_INTERFACE, mouse_report_desc, sizeof(mouse_report_desc)}, + {0x2100, MOUSE_INTERFACE, config_descriptor+MOUSE_DESC_OFFSET, 9}, */ - {0x0300, 0x0000, (const uint8_t *)&string0, 0}, - {0x0301, 0x0409, (const uint8_t *)&usb_string_manufacturer_name, 0}, - {0x0302, 0x0409, (const uint8_t *)&usb_string_product_name, 0}, - {0x0303, 0x0409, (const uint8_t *)&usb_string_serial_number, 0}, + {0x0300, 0x0000, (const uint8_t *)&string0, 0}, + {0x0301, 0x0409, (const uint8_t *)&usb_string_manufacturer_name, 0}, + {0x0302, 0x0409, (const uint8_t *)&usb_string_product_name, 0}, + {0x0303, 0x0409, (const uint8_t *)&usb_string_serial_number, 0}, {0, 0, NULL, 0} };
--- a/Output/pjrcUSB/arm/usb_desc.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/pjrcUSB/arm/usb_desc.h Fri Jun 12 18:31:55 2015 -0700 @@ -45,10 +45,10 @@ // ----- Defines ----- -#define ENDPOINT_UNUSED 0x00 -#define ENDPOINT_TRANSIMIT_ONLY 0x15 -#define ENDPOINT_RECEIVE_ONLY 0x19 -#define ENDPOINT_TRANSMIT_AND_RECEIVE 0x1D +#define ENDPOINT_UNUSED 0x00 +#define ENDPOINT_TRANSIMIT_ONLY 0x15 +#define ENDPOINT_RECEIVE_ONLY 0x19 +#define ENDPOINT_TRANSMIT_AND_RECEIVE 0x1D #define DEVICE_CLASS 0x00 // Keep 0x00 to indicate each sub device will indicate what it is @@ -98,23 +98,23 @@ #define MOUSE_DESC_OFFSET (9 + 9+9+7 + 9+9+7 + 8+9+5+5+4+5+7+9+7+7 + 9) #define JOYSTICK_DESC_OFFSET (9 + 9+9+7 + 9+9+7 + 8+9+5+5+4+5+7+9+7+7 + 9+9+7 + 9) -#define ENDPOINT1_CONFIG ENDPOINT_TRANSIMIT_ONLY -#define ENDPOINT2_CONFIG ENDPOINT_TRANSIMIT_ONLY -#define ENDPOINT3_CONFIG ENDPOINT_TRANSIMIT_ONLY -#define ENDPOINT4_CONFIG ENDPOINT_RECEIVE_ONLY -#define ENDPOINT5_CONFIG ENDPOINT_TRANSIMIT_ONLY -#define ENDPOINT6_CONFIG ENDPOINT_TRANSIMIT_ONLY -#define ENDPOINT7_CONFIG ENDPOINT_TRANSIMIT_ONLY +#define ENDPOINT1_CONFIG ENDPOINT_TRANSIMIT_ONLY +#define ENDPOINT2_CONFIG ENDPOINT_TRANSIMIT_ONLY +#define ENDPOINT3_CONFIG ENDPOINT_TRANSIMIT_ONLY +#define ENDPOINT4_CONFIG ENDPOINT_RECEIVE_ONLY +#define ENDPOINT5_CONFIG ENDPOINT_TRANSIMIT_ONLY +#define ENDPOINT6_CONFIG ENDPOINT_TRANSIMIT_ONLY +#define ENDPOINT7_CONFIG ENDPOINT_TRANSIMIT_ONLY // ----- Enumerations ----- typedef struct { - uint16_t wValue; - uint16_t wIndex; - const uint8_t *addr; - uint16_t length; + uint16_t wValue; + uint16_t wIndex; + const uint8_t *addr; + uint16_t length; } usb_descriptor_list_t;
--- a/Output/pjrcUSB/arm/usb_serial.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/pjrcUSB/arm/usb_serial.c Fri Jun 12 18:31:55 2015 -0700 @@ -45,7 +45,7 @@ // ----- Defines ----- -#define TRANSMIT_FLUSH_TIMEOUT 5 /* in milliseconds */ +#define TRANSMIT_FLUSH_TIMEOUT 5 /* in milliseconds */ // Maximum number of transmit packets to queue so we don't starve other endpoints for memory #define TX_PACKET_LIMIT 8
--- a/Output/pjrcUSB/avr/usb_keyboard_serial.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/pjrcUSB/avr/usb_keyboard_serial.c Fri Jun 12 18:31:55 2015 -0700 @@ -595,16 +595,16 @@ // Check to see if a usb cable has been plugged in // XXX Not tested (also, not currently needed) -HaaTa //if ( USB0_STAT & (1 << 1) - // return 0; + // return 0; HW_CONFIG(); - USB_FREEZE(); // enable USB - PLL_CONFIG(); // config PLL - while (!(PLLCSR & (1<<PLOCK))) ; // wait for PLL lock - USB_CONFIG(); // start USB clock - UDCON = 0; // enable attach resistor + USB_FREEZE(); // enable USB + PLL_CONFIG(); // config PLL + while (!(PLLCSR & (1<<PLOCK))) ; // wait for PLL lock + USB_CONFIG(); // start USB clock + UDCON = 0; // enable attach resistor usb_configuration = 0; - UDIEN = (1<<EORSTE) | (1<<SOFE); + UDIEN = (1<<EORSTE) | (1<<SOFE); sei(); // Disable watchdog timer after possible software reset @@ -627,9 +627,9 @@ { uint8_t intbits, t_cdc; - intbits = UDINT; - UDINT = 0; - if ( intbits & (1 << EORSTI) ) + intbits = UDINT; + UDINT = 0; + if ( intbits & (1 << EORSTI) ) { UENUM = 0; UECONX = 1; @@ -638,7 +638,7 @@ UEIENX = (1 << RXSTPE); usb_configuration = 0; cdc_line_rtsdtr = 0; - } + } if ( (intbits & (1 << SOFI)) && usb_configuration ) { t_cdc = transmit_flush_timer; @@ -701,9 +701,9 @@ // ISR( USB_COM_vect ) { - uint8_t intbits; + uint8_t intbits; const uint8_t *list; - const uint8_t *cfg; + const uint8_t *cfg; uint8_t i, n, len, en; uint8_t *p; uint8_t bmRequestType; @@ -713,23 +713,23 @@ uint16_t wLength; uint16_t desc_val; const uint8_t *desc_addr; - uint8_t desc_length; + uint8_t desc_length; - UENUM = 0; + UENUM = 0; intbits = UEINTX; if (intbits & (1<<RXSTPI)) { - bmRequestType = UEDATX; - bRequest = UEDATX; - wValue = UEDATX; - wValue |= (UEDATX << 8); - wIndex = UEDATX; - wIndex |= (UEDATX << 8); - wLength = UEDATX; - wLength |= (UEDATX << 8); - UEINTX = ~((1<<RXSTPI) | (1<<RXOUTI) | (1<<TXINI)); + bmRequestType = UEDATX; + bRequest = UEDATX; + wValue = UEDATX; + wValue |= (UEDATX << 8); + wIndex = UEDATX; + wIndex |= (UEDATX << 8); + wLength = UEDATX; + wLength |= (UEDATX << 8); + UEINTX = ~((1<<RXSTPI) | (1<<RXOUTI) | (1<<TXINI)); - if ( bRequest == GET_DESCRIPTOR ) + if ( bRequest == GET_DESCRIPTOR ) { list = (const uint8_t *)descriptor_list; for ( i = 0; ; i++ ) @@ -765,7 +765,7 @@ do { i = UEINTX; } while (!(i & ((1<<TXINI)|(1<<RXOUTI)))); - if (i & (1<<RXOUTI)) return; // abort + if (i & (1<<RXOUTI)) return; // abort // send IN packet n = len < ENDPOINT0_SIZE ? len : ENDPOINT0_SIZE; for (i = n; i; i--) { @@ -775,7 +775,7 @@ usb_send_in(); } while (len || n == ENDPOINT0_SIZE); return; - } + } if (bRequest == SET_ADDRESS) { usb_send_in(); @@ -803,8 +803,8 @@ UECFG1X = pgm_read_byte(cfg++); } } - UERST = 0x7E; - UERST = 0; + UERST = 0x7E; + UERST = 0; return; } @@ -940,6 +940,6 @@ } } } - UECONX = (1 << STALLRQ) | (1 << EPEN); // stall + UECONX = (1 << STALLRQ) | (1 << EPEN); // stall }
--- a/Output/pjrcUSB/avr/usb_keyboard_serial.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/pjrcUSB/avr/usb_keyboard_serial.h Fri Jun 12 18:31:55 2015 -0700 @@ -46,8 +46,8 @@ // ----- Function Declarations ----- // Basic USB Configuration -uint8_t usb_init(); // initialize everything -uint8_t usb_configured(); // is the USB port configured +uint8_t usb_init(); // initialize everything +uint8_t usb_configured(); // is the USB port configured // Keyboard HID Functions void usb_keyboard_send(); @@ -56,9 +56,9 @@ void usb_device_reload(); // Enable firmware reflash mode // USB Serial CDC Functions -int16_t usb_serial_getchar(); // receive a character (-1 if timeout/error) -uint8_t usb_serial_available(); // number of bytes in receive buffer -void usb_serial_flush_input(); // discard any buffered input +int16_t usb_serial_getchar(); // receive a character (-1 if timeout/error) +uint8_t usb_serial_available(); // number of bytes in receive buffer +void usb_serial_flush_input(); // discard any buffered input // transmitting data int8_t usb_serial_putchar(uint8_t c); // transmit a character @@ -82,7 +82,7 @@ #define usb_device_software_reset() do { wdt_enable( WDTO_15MS ); for(;;); } while(0) // See EPSIZE -> UECFG1X - 128 and 256 bytes are for endpoint 1 only -#define EP_SIZE(s) ((s) == 256 ? 0x50 : \ +#define EP_SIZE(s) ((s) == 256 ? 0x50 : \ ((s) == 128 ? 0x40 : \ ((s) == 64 ? 0x30 : \ ((s) == 32 ? 0x20 : \ @@ -97,36 +97,36 @@ // ----- Defines ----- // constants corresponding to the various serial parameters -#define USB_SERIAL_DTR 0x01 -#define USB_SERIAL_RTS 0x02 -#define USB_SERIAL_1_STOP 0 -#define USB_SERIAL_1_5_STOP 1 -#define USB_SERIAL_2_STOP 2 -#define USB_SERIAL_PARITY_NONE 0 -#define USB_SERIAL_PARITY_ODD 1 -#define USB_SERIAL_PARITY_EVEN 2 -#define USB_SERIAL_PARITY_MARK 3 -#define USB_SERIAL_PARITY_SPACE 4 -#define USB_SERIAL_DCD 0x01 -#define USB_SERIAL_DSR 0x02 -#define USB_SERIAL_BREAK 0x04 -#define USB_SERIAL_RI 0x08 -#define USB_SERIAL_FRAME_ERR 0x10 -#define USB_SERIAL_PARITY_ERR 0x20 -#define USB_SERIAL_OVERRUN_ERR 0x40 +#define USB_SERIAL_DTR 0x01 +#define USB_SERIAL_RTS 0x02 +#define USB_SERIAL_1_STOP 0 +#define USB_SERIAL_1_5_STOP 1 +#define USB_SERIAL_2_STOP 2 +#define USB_SERIAL_PARITY_NONE 0 +#define USB_SERIAL_PARITY_ODD 1 +#define USB_SERIAL_PARITY_EVEN 2 +#define USB_SERIAL_PARITY_MARK 3 +#define USB_SERIAL_PARITY_SPACE 4 +#define USB_SERIAL_DCD 0x01 +#define USB_SERIAL_DSR 0x02 +#define USB_SERIAL_BREAK 0x04 +#define USB_SERIAL_RI 0x08 +#define USB_SERIAL_FRAME_ERR 0x10 +#define USB_SERIAL_PARITY_ERR 0x20 +#define USB_SERIAL_OVERRUN_ERR 0x40 -#define EP_TYPE_CONTROL 0x00 -#define EP_TYPE_BULK_IN 0x81 -#define EP_TYPE_BULK_OUT 0x80 -#define EP_TYPE_INTERRUPT_IN 0xC1 -#define EP_TYPE_INTERRUPT_OUT 0xC0 -#define EP_TYPE_ISOCHRONOUS_IN 0x41 -#define EP_TYPE_ISOCHRONOUS_OUT 0x40 +#define EP_TYPE_CONTROL 0x00 +#define EP_TYPE_BULK_IN 0x81 +#define EP_TYPE_BULK_OUT 0x80 +#define EP_TYPE_INTERRUPT_IN 0xC1 +#define EP_TYPE_INTERRUPT_OUT 0xC0 +#define EP_TYPE_ISOCHRONOUS_IN 0x41 +#define EP_TYPE_ISOCHRONOUS_OUT 0x40 -#define EP_SINGLE_BUFFER 0x02 -#define EP_DOUBLE_BUFFER 0x06 +#define EP_SINGLE_BUFFER 0x02 +#define EP_DOUBLE_BUFFER 0x06 -#define MAX_ENDPOINT 4 +#define MAX_ENDPOINT 4 #if defined(__AVR_AT90USB162__) #define HW_CONFIG() @@ -154,28 +154,28 @@ #endif // standard control endpoint request types -#define GET_STATUS 0 -#define CLEAR_FEATURE 1 -#define SET_FEATURE 3 -#define SET_ADDRESS 5 -#define GET_DESCRIPTOR 6 -#define GET_CONFIGURATION 8 -#define SET_CONFIGURATION 9 -#define GET_INTERFACE 10 -#define SET_INTERFACE 11 +#define GET_STATUS 0 +#define CLEAR_FEATURE 1 +#define SET_FEATURE 3 +#define SET_ADDRESS 5 +#define GET_DESCRIPTOR 6 +#define GET_CONFIGURATION 8 +#define SET_CONFIGURATION 9 +#define GET_INTERFACE 10 +#define SET_INTERFACE 11 // HID (human interface device) -#define HID_GET_REPORT 1 -#define HID_GET_IDLE 2 -#define HID_GET_PROTOCOL 3 -#define HID_SET_REPORT 9 -#define HID_SET_IDLE 10 -#define HID_SET_PROTOCOL 11 +#define HID_GET_REPORT 1 +#define HID_GET_IDLE 2 +#define HID_GET_PROTOCOL 3 +#define HID_SET_REPORT 9 +#define HID_SET_IDLE 10 +#define HID_SET_PROTOCOL 11 // CDC (communication class device) -#define CDC_SET_LINE_CODING 0x20 -#define CDC_GET_LINE_CODING 0x21 -#define CDC_SET_CONTROL_LINE_STATE 0x22 +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 // CDC Configuration // When you write data, it goes into a USB endpoint buffer, which @@ -185,7 +185,7 @@ // that tells the PC no more data is expected and it should pass // any buffered data to the application that may be waiting. If // you want data sent immediately, call usb_serial_flush_output(). -#define TRANSMIT_FLUSH_TIMEOUT 5 /* in milliseconds */ +#define TRANSMIT_FLUSH_TIMEOUT 5 /* in milliseconds */ // If the PC is connected but not "listening", this is the length // of time before usb_serial_getchar() returns with an error. This @@ -193,13 +193,13 @@ // bits on a wire where nobody is listening, except you get an error // code which you can ignore for serial-like discard of data, or // use to know your data wasn't sent. -#define TRANSMIT_TIMEOUT 25 /* in milliseconds */ +#define TRANSMIT_TIMEOUT 25 /* in milliseconds */ // ----- Endpoint Configuration ----- -#define ENDPOINT0_SIZE 32 +#define ENDPOINT0_SIZE 32 #define KEYBOARD_NKRO_INTERFACE 0 #define KEYBOARD_NKRO_ENDPOINT 1 @@ -208,29 +208,29 @@ #define KEYBOARD_INTERFACE 1 #define KEYBOARD_ENDPOINT 2 -#define KEYBOARD_SIZE 8 +#define KEYBOARD_SIZE 8 #define KEYBOARD_HID_BUFFER EP_DOUBLE_BUFFER #define CDC_IAD_DESCRIPTOR 1 #define CDC_STATUS_INTERFACE 2 #define CDC_DATA_INTERFACE 3 #define CDC_ACM_ENDPOINT 3 -#define CDC_RX_ENDPOINT 4 -#define CDC_TX_ENDPOINT 5 +#define CDC_RX_ENDPOINT 4 +#define CDC_TX_ENDPOINT 5 #if defined(__AVR_AT90USB162__) -#define CDC_ACM_SIZE 16 -#define CDC_ACM_BUFFER EP_SINGLE_BUFFER -#define CDC_RX_SIZE 32 -#define CDC_RX_BUFFER EP_DOUBLE_BUFFER -#define CDC_TX_SIZE 32 -#define CDC_TX_BUFFER EP_DOUBLE_BUFFER +#define CDC_ACM_SIZE 16 +#define CDC_ACM_BUFFER EP_SINGLE_BUFFER +#define CDC_RX_SIZE 32 +#define CDC_RX_BUFFER EP_DOUBLE_BUFFER +#define CDC_TX_SIZE 32 +#define CDC_TX_BUFFER EP_DOUBLE_BUFFER #else -#define CDC_ACM_SIZE 16 -#define CDC_ACM_BUFFER EP_SINGLE_BUFFER -#define CDC_RX_SIZE 64 -#define CDC_RX_BUFFER EP_DOUBLE_BUFFER -#define CDC_TX_SIZE 64 -#define CDC_TX_BUFFER EP_DOUBLE_BUFFER +#define CDC_ACM_SIZE 16 +#define CDC_ACM_BUFFER EP_SINGLE_BUFFER +#define CDC_RX_SIZE 64 +#define CDC_RX_BUFFER EP_DOUBLE_BUFFER +#define CDC_TX_SIZE 64 +#define CDC_TX_BUFFER EP_DOUBLE_BUFFER #endif // Endpoint 0 is reserved for the control endpoint @@ -257,20 +257,20 @@ static const uint8_t PROGMEM device_descriptor[] = { - 18, // bLength - 1, // bDescriptorType - 0x00, 0x02, // bcdUSB - 0x00, // bDeviceClass - Composite device, 0x00 is required for Windows - 0, // bDeviceSubClass - 0, // bDeviceProtocol - ENDPOINT0_SIZE, // bMaxPacketSize0 - LSB(VENDOR_ID), MSB(VENDOR_ID), // idVendor - LSB(PRODUCT_ID), MSB(PRODUCT_ID), // idProduct - 0x00, 0x01, // bcdDevice - 1, // iManufacturer - 2, // iProduct - 3, // iSerialNumber - 1 // bNumConfigurations + 18, // bLength + 1, // bDescriptorType + 0x00, 0x02, // bcdUSB + 0x00, // bDeviceClass - Composite device, 0x00 is required for Windows + 0, // bDeviceSubClass + 0, // bDeviceProtocol + ENDPOINT0_SIZE, // bMaxPacketSize0 + LSB(VENDOR_ID), MSB(VENDOR_ID), // idVendor + LSB(PRODUCT_ID), MSB(PRODUCT_ID), // idProduct + 0x00, 0x01, // bcdDevice + 1, // iManufacturer + 2, // iProduct + 3, // iSerialNumber + 1 // bNumConfigurations }; // Specify only a single USB speed @@ -286,70 +286,70 @@ // Keyboard Protocol 1, HID 1.11 spec, Appendix B, page 59-60 static const uint8_t PROGMEM keyboard_hid_report_desc[] = { // Keyboard Collection - 0x05, 0x01, // Usage Page (Generic Desktop), - 0x09, 0x06, // Usage (Keyboard), - 0xA1, 0x01, // Collection (Application) - Keyboard, + 0x05, 0x01, // Usage Page (Generic Desktop), + 0x09, 0x06, // Usage (Keyboard), + 0xA1, 0x01, // Collection (Application) - Keyboard, // Modifier Byte - 0x75, 0x01, // Report Size (1), - 0x95, 0x08, // Report Count (8), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0xE0, // Usage Minimum (224), - 0x29, 0xE7, // Usage Maximum (231), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x81, 0x02, // Input (Data, Variable, Absolute), + 0x75, 0x01, // Report Size (1), + 0x95, 0x08, // Report Count (8), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0xE0, // Usage Minimum (224), + 0x29, 0xE7, // Usage Maximum (231), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x81, 0x02, // Input (Data, Variable, Absolute), // Reserved Byte - 0x75, 0x08, // Report Size (8), - 0x95, 0x01, // Report Count (1), - 0x81, 0x03, // Output (Constant), + 0x75, 0x08, // Report Size (8), + 0x95, 0x01, // Report Count (1), + 0x81, 0x03, // Output (Constant), // LED Report - 0x75, 0x01, // Report Size (1), - 0x95, 0x05, // Report Count (5), - 0x05, 0x08, // Usage Page (LEDs), - 0x19, 0x01, // Usage Minimum (1), - 0x29, 0x05, // Usage Maximum (5), - 0x91, 0x02, // Output (Data, Variable, Absolute), + 0x75, 0x01, // Report Size (1), + 0x95, 0x05, // Report Count (5), + 0x05, 0x08, // Usage Page (LEDs), + 0x19, 0x01, // Usage Minimum (1), + 0x29, 0x05, // Usage Maximum (5), + 0x91, 0x02, // Output (Data, Variable, Absolute), // LED Report Padding - 0x75, 0x03, // Report Size (3), - 0x95, 0x01, // Report Count (1), - 0x91, 0x03, // Output (Constant), + 0x75, 0x03, // Report Size (3), + 0x95, 0x01, // Report Count (1), + 0x91, 0x03, // Output (Constant), // Normal Keys - 0x75, 0x08, // Report Size (8), - 0x95, 0x06, // Report Count (6), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x7F, // Logical Maximum(104), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0x00, // Usage Minimum (0), - 0x29, 0x7F, // Usage Maximum (104), - 0x81, 0x00, // Input (Data, Array), - 0xc0, // End Collection - Keyboard + 0x75, 0x08, // Report Size (8), + 0x95, 0x06, // Report Count (6), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x7F, // Logical Maximum(104), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0x00, // Usage Minimum (0), + 0x29, 0x7F, // Usage Maximum (104), + 0x81, 0x00, // Input (Data, Array), + 0xc0, // End Collection - Keyboard }; // Keyboard Protocol 1, HID 1.11 spec, Appendix B, page 59-60 static const uint8_t PROGMEM keyboard_nkro_hid_report_desc[] = { // Keyboard Collection - 0x05, 0x01, // Usage Page (Generic Desktop), - 0x09, 0x06, // Usage (Keyboard), - 0xA1, 0x01, // Collection (Application) - Keyboard, + 0x05, 0x01, // Usage Page (Generic Desktop), + 0x09, 0x06, // Usage (Keyboard), + 0xA1, 0x01, // Collection (Application) - Keyboard, // LED Report - 0x85, 0x01, // Report ID (1), - 0x75, 0x01, // Report Size (1), - 0x95, 0x05, // Report Count (5), - 0x05, 0x08, // Usage Page (LEDs), - 0x19, 0x01, // Usage Minimum (1), - 0x29, 0x05, // Usage Maximum (5), - 0x91, 0x02, // Output (Data, Variable, Absolute), + 0x85, 0x01, // Report ID (1), + 0x75, 0x01, // Report Size (1), + 0x95, 0x05, // Report Count (5), + 0x05, 0x08, // Usage Page (LEDs), + 0x19, 0x01, // Usage Minimum (1), + 0x29, 0x05, // Usage Maximum (5), + 0x91, 0x02, // Output (Data, Variable, Absolute), // LED Report Padding - 0x75, 0x03, // Report Size (3), - 0x95, 0x01, // Report Count (1), - 0x91, 0x03, // Output (Constant), + 0x75, 0x03, // Report Size (3), + 0x95, 0x01, // Report Count (1), + 0x91, 0x03, // Output (Constant), // Normal Keys - Using an NKRO Bitmap // @@ -380,24 +380,24 @@ // 224-231 : 1 byte (0xE0-0xE7) ( 8 bits) // Modifier Byte - 0x75, 0x01, // Report Size (1), - 0x95, 0x08, // Report Count (8), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0xE0, // Usage Minimum (224), - 0x29, 0xE7, // Usage Maximum (231), - 0x81, 0x02, // Input (Data, Variable, Absolute), + 0x75, 0x01, // Report Size (1), + 0x95, 0x08, // Report Count (8), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0xE0, // Usage Minimum (224), + 0x29, 0xE7, // Usage Maximum (231), + 0x81, 0x02, // Input (Data, Variable, Absolute), // 4-49 (6 bytes/46 bits) - MainKeys - 0x75, 0x01, // Report Size (1), - 0x95, 0x2E, // Report Count (46), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0x04, // Usage Minimum (4), - 0x29, 0x31, // Usage Maximum (49), - 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), + 0x75, 0x01, // Report Size (1), + 0x95, 0x2E, // Report Count (46), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0x04, // Usage Minimum (4), + 0x29, 0x31, // Usage Maximum (49), + 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), // Padding (2 bits) 0x75, 0x02, // Report Size (2), @@ -405,14 +405,14 @@ 0x81, 0x03, // Input (Constant), // 51-155 (14 bytes/105 bits) - SecondaryKeys - 0x75, 0x01, // Report Size (1), - 0x95, 0x69, // Report Count (105), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0x33, // Usage Minimum (51), - 0x29, 0x9B, // Usage Maximum (155), - 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), + 0x75, 0x01, // Report Size (1), + 0x95, 0x69, // Report Count (105), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0x33, // Usage Minimum (51), + 0x29, 0x9B, // Usage Maximum (155), + 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), // Padding (7 bits) 0x75, 0x07, // Report Size (7), @@ -420,67 +420,67 @@ 0x81, 0x03, // Input (Constant), // 157-164 (1 byte/8 bits) - TertiaryKeys - 0x75, 0x01, // Report Size (1), - 0x95, 0x08, // Report Count (8), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0x9D, // Usage Minimum (157), - 0x29, 0xA4, // Usage Maximum (164), - 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), + 0x75, 0x01, // Report Size (1), + 0x95, 0x08, // Report Count (8), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0x9D, // Usage Minimum (157), + 0x29, 0xA4, // Usage Maximum (164), + 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), // 176-221 (6 bytes/46 bits) - QuartiaryKeys - 0x75, 0x01, // Report Size (1), - 0x95, 0x2E, // Report Count (46), - 0x15, 0x00, // Logical Minimum (0), - 0x25, 0x01, // Logical Maximum (1), - 0x05, 0x07, // Usage Page (Key Codes), - 0x19, 0xB0, // Usage Minimum (176), - 0x29, 0xDD, // Usage Maximum (221), - 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), + 0x75, 0x01, // Report Size (1), + 0x95, 0x2E, // Report Count (46), + 0x15, 0x00, // Logical Minimum (0), + 0x25, 0x01, // Logical Maximum (1), + 0x05, 0x07, // Usage Page (Key Codes), + 0x19, 0xB0, // Usage Minimum (176), + 0x29, 0xDD, // Usage Maximum (221), + 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield), // Padding (2 bits) 0x75, 0x02, // Report Size (2), 0x95, 0x01, // Report Count (1), 0x81, 0x03, // Input (Constant), - 0xc0, // End Collection - Keyboard + 0xc0, // End Collection - Keyboard // System Control Collection // // NOTES: // Not bothering with NKRO for this table. If there's need, I can implement it. -HaaTa // Using a 1KRO scheme - 0x05, 0x01, // Usage Page (Generic Desktop), - 0x09, 0x80, // Usage (System Control), - 0xA1, 0x01, // Collection (Application), - 0x85, 0x02, // Report ID (2), - 0x75, 0x08, // Report Size (8), - 0x95, 0x01, // Report Count (1), - 0x16, 0x81, 0x00, // Logical Minimum (129), - 0x26, 0xB7, 0x00, // Logical Maximum (183), - 0x19, 0x81, // Usage Minimum (129), - 0x29, 0xB7, // Usage Maximum (183), - 0x81, 0x00, // Input (Data, Array), - 0xc0, // End Collection - System Control + 0x05, 0x01, // Usage Page (Generic Desktop), + 0x09, 0x80, // Usage (System Control), + 0xA1, 0x01, // Collection (Application), + 0x85, 0x02, // Report ID (2), + 0x75, 0x08, // Report Size (8), + 0x95, 0x01, // Report Count (1), + 0x16, 0x81, 0x00, // Logical Minimum (129), + 0x26, 0xB7, 0x00, // Logical Maximum (183), + 0x19, 0x81, // Usage Minimum (129), + 0x29, 0xB7, // Usage Maximum (183), + 0x81, 0x00, // Input (Data, Array), + 0xc0, // End Collection - System Control // Consumer Control Collection - Media Keys // // NOTES: // Not bothering with NKRO for this table. If there's a need, I can implement it. -HaaTa // Using a 1KRO scheme - 0x05, 0x0c, // Usage Page (Consumer), - 0x09, 0x01, // Usage (Consumer Control), - 0xA1, 0x01, // Collection (Application), - 0x85, 0x03, // Report ID (3), - 0x75, 0x10, // Report Size (16), - 0x95, 0x01, // Report Count (1), - 0x16, 0x20, 0x00, // Logical Minimum (32), - 0x26, 0x9C, 0x02, // Logical Maximum (668), - 0x05, 0x0C, // Usage Page (Consumer), - 0x19, 0x20, // Usage Minimum (32), - 0x2A, 0x9C, 0x02, // Usage Maximum (668), - 0x81, 0x00, // Input (Data, Array), - 0xc0, // End Collection - Consumer Control + 0x05, 0x0c, // Usage Page (Consumer), + 0x09, 0x01, // Usage (Consumer Control), + 0xA1, 0x01, // Collection (Application), + 0x85, 0x03, // Report ID (3), + 0x75, 0x10, // Report Size (16), + 0x95, 0x01, // Report Count (1), + 0x16, 0x20, 0x00, // Logical Minimum (32), + 0x26, 0x9C, 0x02, // Logical Maximum (668), + 0x05, 0x0C, // Usage Page (Consumer), + 0x19, 0x20, // Usage Minimum (32), + 0x2A, 0x9C, 0x02, // Usage Maximum (668), + 0x81, 0x00, // Input (Data, Array), + 0xc0, // End Collection - Consumer Control }; // <Configuration> + <Keyboard HID> + <NKRO Keyboard HID> + <Serial CDC> @@ -492,162 +492,162 @@ // --- Configuration --- // - 9 bytes - // configuration descriptor, USB spec 9.6.3, page 264-266, Table 9-10 - 9, // bLength; - 2, // bDescriptorType; - LSB(CONFIG1_DESC_SIZE), // wTotalLength + 9, // bLength; + 2, // bDescriptorType; + LSB(CONFIG1_DESC_SIZE), // wTotalLength MSB(CONFIG1_DESC_SIZE), - 4, // bNumInterfaces - 1, // bConfigurationValue - 0, // iConfiguration - 0x80, // bmAttributes - 250, // bMaxPower + 4, // bNumInterfaces + 1, // bConfigurationValue + 0, // iConfiguration + 0x80, // bmAttributes + 250, // bMaxPower // --- Keyboard HID --- // - 9 bytes - // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 - 9, // bLength - 4, // bDescriptorType - KEYBOARD_INTERFACE, // bInterfaceNumber - 0, // bAlternateSetting - 1, // bNumEndpoints - 0x03, // bInterfaceClass (0x03 = HID) - 0x01, // bInterfaceSubClass (0x00 = Non-Boot, 0x01 = Boot) - 0x01, // bInterfaceProtocol (0x01 = Keyboard) - 0, // iInterface + 9, // bLength + 4, // bDescriptorType + KEYBOARD_INTERFACE, // bInterfaceNumber + 0, // bAlternateSetting + 1, // bNumEndpoints + 0x03, // bInterfaceClass (0x03 = HID) + 0x01, // bInterfaceSubClass (0x00 = Non-Boot, 0x01 = Boot) + 0x01, // bInterfaceProtocol (0x01 = Keyboard) + 0, // iInterface // - 9 bytes - // HID interface descriptor, HID 1.11 spec, section 6.2.1 - 9, // bLength - 0x21, // bDescriptorType - 0x11, 0x01, // bcdHID - 0, // bCountryCode - Setting to 0/Undefined - 1, // bNumDescriptors - 0x22, // bDescriptorType - LSB(sizeof(keyboard_hid_report_desc)), // wDescriptorLength + 9, // bLength + 0x21, // bDescriptorType + 0x11, 0x01, // bcdHID + 0, // bCountryCode - Setting to 0/Undefined + 1, // bNumDescriptors + 0x22, // bDescriptorType + LSB(sizeof(keyboard_hid_report_desc)), // wDescriptorLength MSB(sizeof(keyboard_hid_report_desc)), // - 7 bytes - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - KEYBOARD_ENDPOINT | 0x80, // bEndpointAddress - 0x03, // bmAttributes (0x03=intr) - KEYBOARD_SIZE, 0, // wMaxPacketSize + 7, // bLength + 5, // bDescriptorType + KEYBOARD_ENDPOINT | 0x80, // bEndpointAddress + 0x03, // bmAttributes (0x03=intr) + KEYBOARD_SIZE, 0, // wMaxPacketSize 1, // bInterval // --- NKRO Keyboard HID --- // - 9 bytes - // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 - 9, // bLength - 4, // bDescriptorType - KEYBOARD_NKRO_INTERFACE, // bInterfaceNumber - 0, // bAlternateSetting - 1, // bNumEndpoints - 0x03, // bInterfaceClass (0x03 = HID) - 0x00, // bInterfaceSubClass (0x00 = Non-Boot, 0x01 = Boot) - 0x01, // bInterfaceProtocol (0x01 = Keyboard) - 0, // iInterface + 9, // bLength + 4, // bDescriptorType + KEYBOARD_NKRO_INTERFACE, // bInterfaceNumber + 0, // bAlternateSetting + 1, // bNumEndpoints + 0x03, // bInterfaceClass (0x03 = HID) + 0x00, // bInterfaceSubClass (0x00 = Non-Boot, 0x01 = Boot) + 0x01, // bInterfaceProtocol (0x01 = Keyboard) + 0, // iInterface // - 9 bytes - // HID interface descriptor, HID 1.11 spec, section 6.2.1 - 9, // bLength - 0x21, // bDescriptorType - 0x11, 0x01, // bcdHID - 0, // bCountryCode - Setting to 0/Undefined - 1, // bNumDescriptors - 0x22, // bDescriptorType - // wDescriptorLength + 9, // bLength + 0x21, // bDescriptorType + 0x11, 0x01, // bcdHID + 0, // bCountryCode - Setting to 0/Undefined + 1, // bNumDescriptors + 0x22, // bDescriptorType + // wDescriptorLength LSB(sizeof(keyboard_nkro_hid_report_desc)), MSB(sizeof(keyboard_nkro_hid_report_desc)), // - 7 bytes - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - KEYBOARD_NKRO_ENDPOINT | 0x80, // bEndpointAddress - 0x03, // bmAttributes (0x03=intr) - KEYBOARD_NKRO_SIZE, 0, // wMaxPacketSize + 7, // bLength + 5, // bDescriptorType + KEYBOARD_NKRO_ENDPOINT | 0x80, // bEndpointAddress + 0x03, // bmAttributes (0x03=intr) + KEYBOARD_NKRO_SIZE, 0, // wMaxPacketSize 1, // bInterval // --- Serial CDC --- // - 8 bytes - - // interface association descriptor, USB ECN, Table 9-Z - 8, // bLength - 11, // bDescriptorType - CDC_STATUS_INTERFACE, // bFirstInterface - 2, // bInterfaceCount - 0x02, // bFunctionClass - 0x02, // bFunctionSubClass - 0x01, // bFunctionProtocol - 4, // iFunction + // interface association descriptor, USB ECN, Table 9-Z + 8, // bLength + 11, // bDescriptorType + CDC_STATUS_INTERFACE, // bFirstInterface + 2, // bInterfaceCount + 0x02, // bFunctionClass + 0x02, // bFunctionSubClass + 0x01, // bFunctionProtocol + 4, // iFunction // - 9 bytes - // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 - 9, // bLength - 4, // bDescriptorType - CDC_STATUS_INTERFACE, // bInterfaceNumber - 0, // bAlternateSetting - 1, // bNumEndpoints - 0x02, // bInterfaceClass - 0x02, // bInterfaceSubClass - 0x01, // bInterfaceProtocol - 0, // iInterface + 9, // bLength + 4, // bDescriptorType + CDC_STATUS_INTERFACE, // bInterfaceNumber + 0, // bAlternateSetting + 1, // bNumEndpoints + 0x02, // bInterfaceClass + 0x02, // bInterfaceSubClass + 0x01, // bInterfaceProtocol + 0, // iInterface // - 5 bytes - // CDC Header Functional Descriptor, CDC Spec 5.2.3.1, Table 26 - 5, // bFunctionLength - 0x24, // bDescriptorType - 0x00, // bDescriptorSubtype - 0x10, 0x01, // bcdCDC + 5, // bFunctionLength + 0x24, // bDescriptorType + 0x00, // bDescriptorSubtype + 0x10, 0x01, // bcdCDC // - 5 bytes - // Call Management Functional Descriptor, CDC Spec 5.2.3.2, Table 27 - 5, // bFunctionLength - 0x24, // bDescriptorType - 0x01, // bDescriptorSubtype - 0x01, // bmCapabilities - 1, // bDataInterface + 5, // bFunctionLength + 0x24, // bDescriptorType + 0x01, // bDescriptorSubtype + 0x01, // bmCapabilities + 1, // bDataInterface // - 4 bytes - // Abstract Control Management Functional Descriptor, CDC Spec 5.2.3.3, Table 28 - 4, // bFunctionLength - 0x24, // bDescriptorType - 0x02, // bDescriptorSubtype - 0x06, // bmCapabilities + 4, // bFunctionLength + 0x24, // bDescriptorType + 0x02, // bDescriptorSubtype + 0x06, // bmCapabilities // - 5 bytes - // Union Functional Descriptor, CDC Spec 5.2.3.8, Table 33 - 5, // bFunctionLength - 0x24, // bDescriptorType - 0x06, // bDescriptorSubtype - CDC_STATUS_INTERFACE, // bMasterInterface - CDC_DATA_INTERFACE, // bSlaveInterface0 + 5, // bFunctionLength + 0x24, // bDescriptorType + 0x06, // bDescriptorSubtype + CDC_STATUS_INTERFACE, // bMasterInterface + CDC_DATA_INTERFACE, // bSlaveInterface0 // - 7 bytes - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - CDC_ACM_ENDPOINT | 0x80, // bEndpointAddress - 0x03, // bmAttributes (0x03=intr) - CDC_ACM_SIZE, 0, // wMaxPacketSize - 64, // bInterval + 7, // bLength + 5, // bDescriptorType + CDC_ACM_ENDPOINT | 0x80, // bEndpointAddress + 0x03, // bmAttributes (0x03=intr) + CDC_ACM_SIZE, 0, // wMaxPacketSize + 64, // bInterval // - 9 bytes - // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 - 9, // bLength - 4, // bDescriptorType - CDC_DATA_INTERFACE, // bInterfaceNumber - 0, // bAlternateSetting - 2, // bNumEndpoints - 0x0A, // bInterfaceClass - 0x00, // bInterfaceSubClass - 0x00, // bInterfaceProtocol - 0, // iInterface + 9, // bLength + 4, // bDescriptorType + CDC_DATA_INTERFACE, // bInterfaceNumber + 0, // bAlternateSetting + 2, // bNumEndpoints + 0x0A, // bInterfaceClass + 0x00, // bInterfaceSubClass + 0x00, // bInterfaceProtocol + 0, // iInterface // - 7 bytes - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - CDC_RX_ENDPOINT, // bEndpointAddress - 0x02, // bmAttributes (0x02=bulk) - CDC_RX_SIZE, 0, // wMaxPacketSize - 0, // bInterval + 7, // bLength + 5, // bDescriptorType + CDC_RX_ENDPOINT, // bEndpointAddress + 0x02, // bmAttributes (0x02=bulk) + CDC_RX_SIZE, 0, // wMaxPacketSize + 0, // bInterval // - 7 bytes - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - 7, // bLength - 5, // bDescriptorType - CDC_TX_ENDPOINT | 0x80, // bEndpointAddress - 0x02, // bmAttributes (0x02=bulk) - CDC_TX_SIZE, 0, // wMaxPacketSize - 0, // bInterval + 7, // bLength + 5, // bDescriptorType + CDC_TX_ENDPOINT | 0x80, // bEndpointAddress + 0x02, // bmAttributes (0x02=bulk) + CDC_TX_SIZE, 0, // wMaxPacketSize + 0, // bInterval }; @@ -681,10 +681,10 @@ // This table defines which descriptor data is sent for each specific // request from the host (in wValue and wIndex). static const struct descriptor_list_struct { - uint16_t wValue; - uint16_t wIndex; - const uint8_t *addr; - uint8_t length; + uint16_t wValue; + uint16_t wIndex; + const uint8_t *addr; + uint8_t length; } PROGMEM descriptor_list[] = { {0x0100, 0x0000, device_descriptor, sizeof(device_descriptor)}, {0x0200, 0x0000, config1_descriptor, sizeof(config1_descriptor)},
--- a/Output/pjrcUSB/capabilities.kll Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/pjrcUSB/capabilities.kll Fri Jun 12 18:31:55 2015 -0700 @@ -1,14 +1,15 @@ Name = pjrcUSBCapabilities; -Version = 0.3; -Author = "HaaTa (Jacob Alexander) 2014"; -KLL = 0.3; +Version = 0.4; +Author = "HaaTa (Jacob Alexander) 2014-2015"; +KLL = 0.3b; # Modified Date -Date = 2014-10-01; +Date = 2015-05-02; # Output capabilities consCtrlOut => Output_consCtrlSend_capability( consCode : 2 ); +noneOut => Output_noneSend_capability(); sysCtrlOut => Output_sysCtrlSend_capability( sysCode : 1 ); usbKeyOut => Output_usbCodeSend_capability( usbCode : 1 );
--- a/Output/pjrcUSB/output_com.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/pjrcUSB/output_com.c Fri Jun 12 18:31:55 2015 -0700 @@ -93,20 +93,20 @@ // Which modifier keys are currently pressed // 1=left ctrl, 2=left shift, 4=left alt, 8=left gui // 16=right ctrl, 32=right shift, 64=right alt, 128=right gui - uint8_t USBKeys_Modifiers = 0; - uint8_t USBKeys_ModifiersCLI = 0; // Separate CLI send buffer + uint8_t USBKeys_Modifiers = 0; + uint8_t USBKeys_ModifiersCLI = 0; // Separate CLI send buffer // Currently pressed keys, max is defined by USB_MAX_KEY_SEND - uint8_t USBKeys_Keys [USB_NKRO_BITFIELD_SIZE_KEYS]; - uint8_t USBKeys_KeysCLI[USB_NKRO_BITFIELD_SIZE_KEYS]; // Separate CLI send buffer + uint8_t USBKeys_Keys [USB_NKRO_BITFIELD_SIZE_KEYS]; + uint8_t USBKeys_KeysCLI[USB_NKRO_BITFIELD_SIZE_KEYS]; // Separate CLI send buffer // System Control and Consumer Control 1KRO containers - uint8_t USBKeys_SysCtrl; - uint16_t USBKeys_ConsCtrl; + uint8_t USBKeys_SysCtrl; + uint16_t USBKeys_ConsCtrl; // The number of keys sent to the usb in the array - uint8_t USBKeys_Sent = 0; - uint8_t USBKeys_SentCLI = 0; + uint8_t USBKeys_Sent = 0; + uint8_t USBKeys_SentCLI = 0; // 1=num lock, 2=caps lock, 4=scroll lock, 8=compose, 16=kana volatile uint8_t USBKeys_LEDs = 0; @@ -122,20 +122,20 @@ // the idle configuration, how often we send the report to the // host (ms * 4) even when it hasn't changed - uint8_t USBKeys_Idle_Config = 125; + uint8_t USBKeys_Idle_Config = 125; // count until idle timeout - uint8_t USBKeys_Idle_Count = 0; + uint8_t USBKeys_Idle_Count = 0; // Indicates whether the Output module is fully functional // 0 - Not fully functional, 1 - Fully functional // 0 is often used to show that a USB cable is not plugged in (but has power) - uint8_t Output_Available = 0; + uint8_t Output_Available = 0; // Debug control variable for Output modules // 0 - Debug disabled (default) // 1 - Debug enabled - uint8_t Output_DebugMode = 0; + uint8_t Output_DebugMode = 0; @@ -229,6 +229,21 @@ } +// Ignores the given key status update +// Used to prevent fall-through, this is the None keyword in KLL +void Output_noneSend_capability( uint8_t state, uint8_t stateType, uint8_t *args ) +{ + // Display capability name + if ( stateType == 0xFF && state == 0xFF ) + { + print("Output_noneSend()"); + return; + } + + // Nothing to do, because that's the point :P +} + + // Sends a System Control code to the USB Output buffer void Output_sysCtrlSend_capability( uint8_t state, uint8_t stateType, uint8_t *args ) {
--- a/Output/pjrcUSB/output_com.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/pjrcUSB/output_com.h Fri Jun 12 18:31:55 2015 -0700 @@ -89,6 +89,7 @@ // Output capabilities void Output_consCtrlSend_capability( uint8_t state, uint8_t stateType, uint8_t *args ); +void Output_noneSend_capability( uint8_t state, uint8_t stateType, uint8_t *args ); void Output_sysCtrlSend_capability( uint8_t state, uint8_t stateType, uint8_t *args ); void Output_usbCodeSend_capability( uint8_t state, uint8_t stateType, uint8_t *args );
--- a/Output/uartOut/output_com.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/uartOut/output_com.c Fri Jun 12 18:31:55 2015 -0700 @@ -73,20 +73,20 @@ // Which modifier keys are currently pressed // 1=left ctrl, 2=left shift, 4=left alt, 8=left gui // 16=right ctrl, 32=right shift, 64=right alt, 128=right gui - uint8_t USBKeys_Modifiers = 0; - uint8_t USBKeys_ModifiersCLI = 0; // Separate CLI send buffer + uint8_t USBKeys_Modifiers = 0; + uint8_t USBKeys_ModifiersCLI = 0; // Separate CLI send buffer // Currently pressed keys, max is defined by USB_MAX_KEY_SEND - uint8_t USBKeys_Keys [USB_NKRO_BITFIELD_SIZE_KEYS]; - uint8_t USBKeys_KeysCLI[USB_NKRO_BITFIELD_SIZE_KEYS]; // Separate CLI send buffer + uint8_t USBKeys_Keys [USB_NKRO_BITFIELD_SIZE_KEYS]; + uint8_t USBKeys_KeysCLI[USB_NKRO_BITFIELD_SIZE_KEYS]; // Separate CLI send buffer // System Control and Consumer Control 1KRO containers - uint8_t USBKeys_SysCtrl; - uint16_t USBKeys_ConsCtrl; + uint8_t USBKeys_SysCtrl; + uint16_t USBKeys_ConsCtrl; // The number of keys sent to the usb in the array - uint8_t USBKeys_Sent = 0; - uint8_t USBKeys_SentCLI = 0; + uint8_t USBKeys_Sent = 0; + uint8_t USBKeys_SentCLI = 0; // 1=num lock, 2=caps lock, 4=scroll lock, 8=compose, 16=kana volatile uint8_t USBKeys_LEDs = 0; @@ -102,15 +102,15 @@ // the idle configuration, how often we send the report to the // host (ms * 4) even when it hasn't changed - uint8_t USBKeys_Idle_Config = 125; + uint8_t USBKeys_Idle_Config = 125; // count until idle timeout - uint8_t USBKeys_Idle_Count = 0; + uint8_t USBKeys_Idle_Count = 0; // Indicates whether the Output module is fully functional // 0 - Not fully functional, 1 - Fully functional // 0 is often used to show that a USB cable is not plugged in (but has power) - uint8_t Output_Available = 0; + uint8_t Output_Available = 0;
--- a/Output/usbMuxUart/output_com.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/usbMuxUart/output_com.c Fri Jun 12 18:31:55 2015 -0700 @@ -96,20 +96,20 @@ // Which modifier keys are currently pressed // 1=left ctrl, 2=left shift, 4=left alt, 8=left gui // 16=right ctrl, 32=right shift, 64=right alt, 128=right gui - uint8_t USBKeys_Modifiers = 0; - uint8_t USBKeys_ModifiersCLI = 0; // Separate CLI send buffer + uint8_t USBKeys_Modifiers = 0; + uint8_t USBKeys_ModifiersCLI = 0; // Separate CLI send buffer // Currently pressed keys, max is defined by USB_MAX_KEY_SEND - uint8_t USBKeys_Keys [USB_NKRO_BITFIELD_SIZE_KEYS]; - uint8_t USBKeys_KeysCLI[USB_NKRO_BITFIELD_SIZE_KEYS]; // Separate CLI send buffer + uint8_t USBKeys_Keys [USB_NKRO_BITFIELD_SIZE_KEYS]; + uint8_t USBKeys_KeysCLI[USB_NKRO_BITFIELD_SIZE_KEYS]; // Separate CLI send buffer // System Control and Consumer Control 1KRO containers - uint8_t USBKeys_SysCtrl; - uint16_t USBKeys_ConsCtrl; + uint8_t USBKeys_SysCtrl; + uint16_t USBKeys_ConsCtrl; // The number of keys sent to the usb in the array - uint8_t USBKeys_Sent = 0; - uint8_t USBKeys_SentCLI = 0; + uint8_t USBKeys_Sent = 0; + uint8_t USBKeys_SentCLI = 0; // 1=num lock, 2=caps lock, 4=scroll lock, 8=compose, 16=kana volatile uint8_t USBKeys_LEDs = 0; @@ -125,20 +125,20 @@ // the idle configuration, how often we send the report to the // host (ms * 4) even when it hasn't changed - uint8_t USBKeys_Idle_Config = 125; + uint8_t USBKeys_Idle_Config = 125; // count until idle timeout - uint8_t USBKeys_Idle_Count = 0; + uint8_t USBKeys_Idle_Count = 0; // Indicates whether the Output module is fully functional // 0 - Not fully functional, 1 - Fully functional // 0 is often used to show that a USB cable is not plugged in (but has power) - uint8_t Output_Available = 0; + uint8_t Output_Available = 0; // Debug control variable for Output modules // 0 - Debug disabled (default) // 1 - Debug enabled - uint8_t Output_DebugMode = 0; + uint8_t Output_DebugMode = 0;
--- a/Output/usbMuxUart/setup.cmake Sun Mar 08 22:35:55 2015 -0700 +++ b/Output/usbMuxUart/setup.cmake Fri Jun 12 18:31:55 2015 -0700 @@ -35,6 +35,6 @@ # set( ModuleCompatibility arm -# avr # TODO +# avr # TODO )
--- a/README.markdown Sun Mar 08 22:35:55 2015 -0700 +++ b/README.markdown Fri Jun 12 18:31:55 2015 -0700 @@ -1,750 +1,87 @@ The Kiibohd Controller ====================== -This README is a bit long, just look at the sections you are interested in. -You only need to install avr-gcc if you want to build for the Teensy 2.0/2.0++. -Everything else needs an arm-none-eabi-gcc compiler (e.g. Infinity keyboard, -Teensy 3.0/3.1, McHCK). - -Linux is the ideal build environment (preferably recent'ish). In the near -future I'll make available an Arch Linux VM for building/manufacturing tests. - -Building on Mac should be ok for 99% of users with Macports or Homebrew. For -Homebrew, use `brew tap PX4/homebrew-px4` to get the arm-none-eabi-gcc installer. -The dfu Bootloader will not build correctly with the old version of -arm-none-eabi-gcc that Macports currently has (4.7.3). This is due to a bug -with lto (link time optimizations) which makes the resulting binary too big to -fit on the chip (must be less than 4096 Bytes). - -Building on Windows should also be fine for 99% of users, but takes a bunch of -work to setup (because Windows is a crappy dev environment). Cygwin is -currently required along with some non-Cygwin compilers and utilities (because -they are not available for Cygwin). The dfu Bootloader will not build because -of a Make 3.81+ bug/feature that removed support for non-Unix (Windows) -filenames as dependencies of targets. If you [replace the version of Make in -Cygwin](http://stackoverflow.com/questions/601516/cygwin-make-error-target-pattern-contains-no) -it should work. However, make sure that the flash size is no larger than 4096 -Bytes or the bootloader will not work. Things will likely break if there are -**SPACES IN YOUR PATHS**. I install cygwin to `C:\cygwin64`. If you are brave -and have programming knowledge, I will accept patches to fix any issues -regarding spaces in paths. - -Please give authors credit for modules used if you use in a distributed -product :D +This is the main Kiibohd Firmware. +In general, this should be the **only** git repo you need to clone. +The [KLL](https://github.com/kiibohd/kll) git repo is automatically cloned during the build process. - -General Dependencies --------------------- - -Below listed are the Arch Linux pacman names, AUR packages may be required. - -These depend a bit on which targets you are trying to build, but the general -one: - -- cmake (2.8 and higher) -- git -- ctags (recommended, not required) -- python3 -- libusb1.0 (and -devel) -- make +Please refer to the [KLL](https://github.com/kiibohd/kll) repo or [kiibohd.com](http://kiibohd.com) for details on the KLL (Keyboard Layout Language) Spec. -AVR Specific (Teensy 1.0/++,2.0/++) (try to use something recent, suggested -versions below) - -- avr-gcc (~4.8.0) -- avr-binutils (~2.23.2) -- avr-libc (~1.8.0) - -ARM Specific (Teensy 3.0/3.1, Infinity Keyboard, McHCK) - -- Arch Linux / Mac Ports - - arm-none-eabi-gcc - - arm-none-eabi-binutils - -- Windows (https://launchpad.net/gcc-arm-embedded/+download) - - gcc-arm-none-eabi (win32.zip) -Windows Setup -------------- - -Compiling on Windows does work, just it's a bunch more work. - -First make sure Cygwin is installed - http://www.cygwin.com/ - 32bit or 64bit -is fine. Make sure the following are installed: - -- make -- git (needed for some compilation info) -- cmake -- gcc-core -- gcc-g++ -- libusb1.0 -- libusb1.0-devel -- python3 -- ctags (recommended, not required) - -Please note, I use cygwin term exclusively for any command line options. -Unless mentioned otherwise, use it. Do NOT use CMD or Powershell. - -Also install the [Windows version of CMake](http://cmake.org/cmake/resources/software.html) -(3+ is ideal) - Select "Do not add CMake to system PATH". This is in addition -to the Cygwin version. This is an easier alternative to installing another C -compiler. Add the following line to your .bashrc, making sure the CMake path -is correct: - - echo "alias wincmake=\"PATH='/cygdrive/c/Program Files (x86)/CMake'/bin:'${PATH}' cmake -G 'Unix Makefiles'\"" >> ~/.bashrc +Official Keyboards +------------------ -Install the [PJRC Virtual Serial Port Driver](http://pjrc.com/teensy/serial_install.exe). - -Next, install the compiler(s) you want. - - -### AVR GCC - -You just need the -[Atmel AVR 8-bit Toolchain](http://www.atmel.com/tools/atmelavrtoolchainforwindows.aspx). -The latest should be fine, as of writing it was 3.4.3. - -Extract the files to a directory, say `C:\avr8-gnu-toolchain`. Then copy all -the folders in that directory to the Cygwin `/usr/local` directory. Mine is -`C:\cygwin64\usr\local`. (You can also just setup the paths, but this is -faster/simpler. Might screw up your Cygwin though). - - -### ARM EABI - -Download the latest -[GNU Tools for Embedded Processors -gcc-arm-none-eabi](https://launchpad.net/gcc-arm-embedded/+download). - -Download `gcc-arm-none-eabi*win32.zip`. - -Then extract all the folders/files in the zip to the Cygwin `/usr/local` -directory. Mine is `C:\cygwin64\usr\local`. Or, you can setup paths using -the installer (you have to be more careful, avoid spaces in paths). +* MD1 (Infinity Keyboard 2014/10/15) -CMake Info ----------- - -One of the big benefits of using CMake is the ability to build multiple -configurations (for different microcontrollers) at the same time. The -following sections explain in detail what each CMakeLists.txt configuration -option does and what you can change it to. However, it is possible to -configure each of these options using the `-D` command line flag. - -For example, to build the Infinity Keyboard default configuration: - -```bash -$ mkdir build_infinity -$ cd build_infinity -$ cmake -DCHIP=mk20dx128vlf5 -DScanModule=MD1 -DMacroModule=PartialMap \ - -DOutputModule=pjrcUSB -DDebugModule=full -DBaseMap=defaultMap \ - -DDefaultMap="md1Overlay stdFuncMap" -DPartialMaps="hhkbpro2" \ - .. -$ make -``` - -CMake defaults to the values specified in CMakeLists.txt if not overridden via -the command line. - -> NOTE: On Windows, you will have to use "wincmake" instead of "cmake". - +The Kiibohd firmware supports a lot of other keyboards, but these are more obscure/custom/lesser known. -Selecting Microcontroller -------------------------- - -This is where you select the chip you want to compile for. The build system -will automatically select the compiler needed to compile for your chip. - -Open up CMakeLists.txt in your favourite text editor. You are looking for: - -```cmake -### -# Chip Selection -# - -#| You _MUST_ set this to match the microcontroller you are trying to compile for -#| You _MUST_ clean the build directory if you change this value -#| -set( CHIP -# "at90usb162" # Teensy 1.0 (avr) -# "atmega32u4" # Teensy 2.0 (avr) -# "at90usb646" # Teensy++ 1.0 (avr) -# "at90usb1286" # Teensy++ 2.0 (avr) -# "mk20dx128" # Teensy 3.0 (arm) - "mk20dx128vlf5" # McHCK mk20dx128vlf5 -# "mk20dx256" # Teensy 3.1 (arm) - CACHE STRING "Microcontroller Chip" ) -``` - -Just uncomment the chip you want, and comment out the old one. - -> NOTE: If you change this option, you will *need* to delete the build -> directory that is created in the Building sections below. -Selecting Modules ------------------ - -> WARNING: Not all modules are compatible, and some modules may have -> dependencies on other modules. - -This is where the options start getting interesting. The Kiibohd Controller -is designed around a set of 4 types of modules that correspond to different -functionality: - -- Scan Module -- Macro Module -- Output Module -- Debug Module - -The Scan Module is where the most interesting stuff happens. These modules -take in "keypress data". A converter Scan Module will interpret a protocol -into key press/releases. A matrix Scan Module may inherit from the matrix -module to scan keypress from a matrix This module just has to give -press/release codes, but does have some callback control to other modules -depending on the lifecycle for press/release codes (this can be very -complicated depending on the protocol). Each Scan Module has it's own default -keymap/modifier map. (TODO recommend keymap changing in the Macro Module). - -Some scan modules have very specialized hardware requirements, each module -directory should have at least a link to the needed parts and/or schematics -(TODO!). - -The Macro Module takes care of the mapping of the key press/release code into -an Output (USB) scan code. Any layering, macros, keypress -intelligence/reaction is done here. - -The Output Module is the module dealing with output from the microcontroller. -Currently USB is the only output protocol. Different USB output -implementations are available, pjrc being the safest/least featureful one. -Debug capabilities may depend on the module selected. +Compilation +----------- -The Debug Module enables various things like the Teensy LED on errors, debug -terminal output. (TODO get true UART working in avr, not just arm) - -Open up CMakeLists.txt in your favourite text editor. Look for: - -```cmake -### -# Project Modules -# - -#| Note: This is the only section you probably want to modify -#| Each module is defined by it's own folder (e.g. Scan/Matrix represents the "Matrix" module) -#| All of the modules must be specified, as they generate the sources list of files to compile -#| Any modifications to this file will cause a complete rebuild of the project - -#| Please look at the {Scan,Macro,Output,Debug} for information on the modules and how to create new ones +Compilation is possible and tested on Windows/Linux/Mac. +Linux is the easiest using this [VM](https://s3.amazonaws.com/configurator-assets/ArchLinux_kiibohd_2015-02-13.tar.gz). -##| Deals with acquiring the keypress information and turning it into a key index -set( ScanModule "MD1" - CACHE STRING "Scan Module" ) - -##| Provides the mapping functions for DefaultMap and handles any macro processing before sending to the OutputModule -set( MacroModule "PartialMap" - CACHE STRING "Macro Module" ) - -##| Sends the current list of usb key codes through USB HID -set( OutputModule "pjrcUSB" - CACHE STRING "Output Module" ) +For most people refer [here](https://github.com/kiibohd/controller/tree/master/Keyboards). -##| Debugging source to use, each module has it's own set of defines that it sets -set( DebugModule "full" - CACHE STRING "Debug Module" ) -``` - -Look at each module individually for it's requirements. There is -chip/architecture dependency checking but some permutations of modules may not -be tested/compile. - -There are also CMake options for temporarily selecting modules. But it's -easier to just edit the file. e.g. `cmake -DScanModuleOverride=<module name>`. +For the full compilation details, please refer to the [wiki](https://github.com/kiibohd/controller/wiki). -Keymap Configuration --------------------- -This is where you define the layout for your keyboard. -Currently, the only way to define kebyoard layouts is using [KLL](https://www.overleaf.com/read/zzqbdwqjfwwf). - -KLL is built up of 3 different kinds of keymaps in total. -The BaseMap, DefaultMap and PartialMaps. - -For each type of keymap, it is possible to combine multiple .kll files together to create new ones using -the compiler. The order of the files matter, as the right-most file will overwrite any setting in the -previous files. - -> NOTE: Each keymap is done after the entire file is processed. This means that within the file the order -> of assignment doesa *not* matter (if you assign the same thing twice, then yes the most recent one -> takes priority). - - -BaseMap defines what the keyboard can do. This includes specific capabilities of the keyboard (such as USB), -the mapping of Scan Codes to USB Codes and any specific configurations for the keyboard. -In general, the BaseMap rarely needs to be changed. Usually only when adding a new keyboard to the firmware -does the Basemap need any modification. -The BaseMap is what both DefaultMap and PartialMaps are based upon. This allows for a common reference -when defining custom keymappings. - -> NOTE: Don't use defaultMap.kll to change your layouts. This will work, but they will not be portable. - - -The DefaultMap is the normal state of the keyboard, i.e. your default layer. -Using the BaseMap as a base, the DefaultMap is a modification of the BaseMap to what the keyboard should do. -Since the DefaultMap uses USB Code to USB Code translations, this means that keymaps used for one keyboard -will work with another keyboard. -For example, I use Colemak, so this means I only have to define Colemak once for every keyboard that supports -the kiibohd firmware. This is possible because every BaseMap defines the keyboard as a US ANSI like keyboard -layout. -The DefaultMap can also be thought of as Layer 0. - - -PartialMaps are optional keymaps that can be "stacked" on top of the DefaultMap. -They can be dynamically swapped out using the layer control capabilities: - -- layerLatch( `<layer number>` ) -- layerLock( `<layer number>` ) -- layerShift( `<layer number>` ) - -layerShift is usually what you want as it works just like a standard shift key. -layerLock is similar to the CapsLock key. While layerLatch is a latch, where only the next key you press -will use that layer (e.g. stickykeys). +Supported Microcontrollers +-------------------------- -A unique aspect of KLL layers is that it's a true stack of layers. -When a layer is activated, only the keys that are specified by the layer will change. -This means, if you define a layer that only sets `CapsLock -> LCtrl` and `LCtrl->Capslock` only those keys -will change when you active the layer. All the other keys will use the layer that is "underneath" to -lookup the keypress (usually the DefaultMap). - -This means that you can combine .kll files statically using the compiler or dynamically using the firmware. - -You can set the max number of layers by changing the `stateWordSize` define in one of your kll files. -By default it is set to 8 in Macro/PartialMap/capabilities.kll. This means you can have up to 256 layers -total (this includes the DefaultMap). -You can increase this number to either 16 or 32 (this will use more Flash and RAM btw) which will give you -2^16 and 2^32 possible layers respectively (65 535 and 4 294 967 295). - - -```cmake -### -# Keymap Configuration (do not include the .kll extension) -# - -#| Do not include the .kll extension -#| * BaseMap maps the native keyboard scan codes to USB Codes so the layout is compatible with all other layouts -#| * DefaultMap allows the default keymap to be modified from the BaseMap -#| * PartialMaps is a set of dynamically set layers (there is no limit, but too many may use up too much RAM...) -#| BaseMap generally does not need to be changed from "defaultMap" -#| -#| Syntax: -#| myMap -#| * defines a single .kll layout file, double-quotes are needed to distinguish between layers -#| "myMap specialLayer" -#| * defines myMap to be the main layout, then replace specialLayers on top of it -#| -#| - Only for PartialMaps - -#| "myMap specialLayer" "myMap colemak" dvorak -#| * As before, but also generates a second layer at index 2 and third at index 3 -#| -#| NOTE: Remember to add key(s) to enable each Partial Layer -#| NOTE2: Layers are always based up the BaseMap (which should be an ANSI-like mapping) -#| NOTE3: Compiler looks in kll/layouts and the build directory for layout files (precedence on build directory) - -##| Set the base keyboard .kll map, defaults to "defaultMap" if not found -##| Looks in Scan/<Module Name> for the available BaseMaps -set( BaseMap "defaultMap" - CACHE STRING "KLL BaseMap/Scancode Keymapping" ) - -##| Layer additonal .kll maps on the BaseMap, layers are in order from 1st to nth -##| Can be set to "" -set( DefaultMap "md1Overlay stdFuncMap" - CACHE STRING "KLL DefaultMap" ) - -##| ParitalMaps available on top of the BaseMap. See above for syntax on specifying multiple layers vs. layering -##| Can be set to "" -set( PartialMaps "hhkbpro2" - CACHE STRING "KLL PartialMaps/Layer Definitions" ) -``` +* Teensy 2.0 (Partial) +* Teensy 2.0++ +* Teesny 3.0 +* Teensy 3.1 +* mk20dx128vlf5 +* mk20dx256vlh7 -Linux Building --------------- - -From this directory. - -```bash -$ mkdir build -$ cd build -$ cmake .. -$ make -``` - -Example output: +Adding support for more microcontrollers is possible. +Some considerations for minimum specs: -``` -$ cmake .. --- Compiler Family: -arm --- Chip Selected: -mk20dx128vlf5 --- Chip Family: -mk20dx --- CPU Selected: -cortex-m4 --- Compiler Source Files: -Lib/mk20dx.c;Lib/delay.c --- Bootloader Type: -dfu --- Detected Scan Module Source Files: -Scan/MD1/scan_loop.c;Scan/MD1/../MatrixARM/matrix_scan.c --- Detected Macro Module Source Files: -Macro/PartialMap/macro.c --- Detected Output Module Source Files: -Output/pjrcUSB/output_com.c;Output/pjrcUSB/arm/usb_desc.c;Output/pjrcUSB/arm/usb_dev.c; -Output/pjrcUSB/arm/usb_keyboard.c;Output/pjrcUSB/arm/usb_mem.c;Output/pjrcUSB/arm/usb_serial.c --- Detected Debug Module Source Files: -Debug/full/../cli/cli.c;Debug/full/../led/led.c;Debug/full/../print/print.c --- Found Git: /usr/bin/git (found version "2.2.1") --- Found Ctags: /usr/bin/ctags (found version "5.8") --- Checking for latest kll version: -Current branch master is up to date. --- Detected Layout Files: -/home/hyatt/Source/controller/Macro/PartialMap/capabilities.kll -/home/hyatt/Source/controller/Output/pjrcUSB/capabilities.kll -/home/hyatt/Source/controller/Scan/MD1/defaultMap.kll -/home/hyatt/Source/controller/kll/layouts/md1Overlay.kll -/home/hyatt/Source/controller/kll/layouts/stdFuncMap.kll -/home/hyatt/Source/controller/kll/layouts/hhkbpro2.kll --- Configuring done --- Generating done --- Build files have been written to: /home/hyatt/Source/controller/build -[master]: make [~/Source/controller/build](hyatt@x230mas:pts/6) -[ 5%] Generating KLL Layout -Scanning dependencies of target kiibohd.elf -[ 11%] Building C object CMakeFiles/kiibohd.elf.dir/main.c.o -[ 17%] Building C object CMakeFiles/kiibohd.elf.dir/Lib/mk20dx.c.o -[ 23%] Building C object CMakeFiles/kiibohd.elf.dir/Lib/delay.c.o -[ 29%] Building C object CMakeFiles/kiibohd.elf.dir/Scan/MD1/scan_loop.c.o -[ 35%] Building C object CMakeFiles/kiibohd.elf.dir/Scan/MatrixARM/matrix_scan.c.o -[ 41%] Building C object CMakeFiles/kiibohd.elf.dir/Macro/PartialMap/macro.c.o -[ 47%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/output_com.c.o -[ 52%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_desc.c.o -[ 58%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_dev.c.o -[ 64%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_keyboard.c.o -[ 70%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_mem.c.o -[ 76%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_serial.c.o -[ 82%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/cli/cli.c.o -[ 88%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/led/led.c.o -[ 94%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/print/print.c.o -Linking C executable kiibohd.elf -[ 94%] Built target kiibohd.elf -Scanning dependencies of target SizeAfter -[100%] Chip usage for mk20dx128vlf5 - SRAM: 32% 5384/16384 bytes - Flash: 18% 23384/126976 bytes -[100%] Built target SizeAfter -``` +* ~8 kB of SRAM +* ~25 kB of Flash -Linux Loading Firmware ----------------------- +It's possible to port chips with lower specs, but will be more effort and have fewer features. -First place the keyboard into re-flash mode. This can be done either by -pressing the re-flash button on the PCB/Teensy. Or by entering the Kiibohd -Virtual Serial Port and using the 'reload' command. - -The `load` script that is created during the build can load the firmware over -USB. Either run it with sudo, or install the `98-kiibohd.rules` to -`/etc/udev/rules.d` and run: `udevadm control --reload-rules`. - -To load the newly built firmware: `./load`. -Linux Building Bootloader -------------------------- - -> NOTE: Does not apply to Teensy based builds. - -From this directory. +Contributions +------------- -```bash -$ cd Bootloader -$ mkdir build -$ cd build -$ cmake .. -$ make -``` - -Example output: +Contributions welcome! -```bash -$ cmake .. --- Compiler Family: -arm --- Chip Selected: -mk20dx128vlf5 --- Chip Family: -mk20dx --- CPU Selected: -cortex-m4 --- Compiler Source Files: -Lib/mk20dx.c;Lib/delay.c --- Bootloader Type: -dfu --- Bootloader Source Files: -main.c;dfu.c;dfu.desc.c;flash.c;kinetis.c;usb.c --- Found Git: /usr/bin/git (found version "2.2.1") --- Found Ctags: /usr/bin/ctags (found version "5.8") --- Configuring done --- Generating done --- Build files have been written to: /home/hyatt/Source/controller/Bootloader/build -[master]: make [~/Source/controller/Bootloader/build](hyatt@x230mas:pts/6) -Scanning dependencies of target kiibohd_bootloader.elf -[ 11%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/main.c.o -[ 22%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/dfu.c.o -[ 33%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/dfu.desc.c.o -[ 44%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/flash.c.o -[ 55%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/kinetis.c.o -[ 66%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/usb.c.o -[ 77%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/home/hyatt/Source/controller/Lib/mk20dx.c.o -[ 88%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/home/hyatt/Source/controller/Lib/delay.c.o -Linking C executable kiibohd_bootloader.elf -[ 88%] Built target kiibohd_bootloader.elf -Scanning dependencies of target SizeAfter -[100%] Chip usage for mk20dx128vlf5 - SRAM: 19% 3176/16384 bytes - Flash: 2% 3736/126976 bytes -[100%] Built target SizeAfter -``` +* Bug reports +* Documentation and Wiki editing +* Patches (including new features) -Linux Loading Bootloader ------------------------- - -> NOTE: Does not apply to Teensy based builds. - -It's recommended to use an SWD-type flasher like a Bus Pirate. There is a -convenience script for loading the firmware once the system is setup. - -```bash -$ cd Bootloader/Scripts -$ ./swdLoad.bash -``` - -The above script requires Ruby, Ruby serial port module, git, and a -`/dev/buspirate` udev rule. - -Additional Notes: - -* https://github.com/mchck/mchck/wiki/Getting-Started (See Bus-Pirate section) -* https://wiki.archlinux.org/index.php/Bus_pirate - -Windows Building ----------------- - -From this directory. - -```bash -$ mkdir build -$ cd build -$ wincmake .. -$ make -``` - -Example output: - -```bash -$ wincmake .. --- Compiler Family: -arm --- Chip Selected: -mk20dx128vlf5 --- Chip Family: -mk20dx --- CPU Selected: -cortex-m4 --- Compiler Source Files: -Lib/mk20dx.c;Lib/delay.c --- Bootloader Type: -dfu --- Detected Scan Module Source Files: -Scan/MD1/scan_loop.c;Scan/MD1/../MatrixARM/matrix_scan.c --- Detected Macro Module Source Files: -Macro/PartialMap/macro.c --- Detected Output Module Source Files: -Output/pjrcUSB/output_com.c;Output/pjrcUSB/arm/usb_desc.c;Output/pjrcUSB/arm/usb_dev.c;Output/pjrcUSB/arm/usb_keyboard.c;Output/pjrcUSB/arm/usb_mem.c;Output/pjrcUSB/arm/usb_serial.c --- Detected Debug Module Source Files: -Debug/full/../cli/cli.c;Debug/full/../led/led.c;Debug/full/../print/print.c --- Found Git: C:/cygwin64/bin/git.exe (found version "2.1.1") --- Found Ctags: C:/cygwin64/bin/ctags.exe (found version "5.8") --- Checking for latest kll version: -Current branch master is up to date. --- Detected Layout Files: -C:/cygwin64/home/Jacob/controller/Macro/PartialMap/capabilities.kll -C:/cygwin64/home/Jacob/controller/Output/pjrcUSB/capabilities.kll -C:/cygwin64/home/Jacob/controller/Scan/MD1/defaultMap.kll -C:/cygwin64/home/Jacob/controller/kll/layouts/md1Overlay.kll -C:/cygwin64/home/Jacob/controller/kll/layouts/stdFuncMap.kll -C:/cygwin64/home/Jacob/controller/kll/layouts/hhkbpro2.kll --- Configuring done --- Generating done --- Build files have been written to: C:/cygwin64/home/Jacob/controller/build +Licensing +--------- -$ make -[ 5%] Generating KLL Layout -Scanning dependencies of target kiibohd.elf -[ 11%] Building C object CMakeFiles/kiibohd.elf.dir/main.c.obj -[ 17%] Building C object CMakeFiles/kiibohd.elf.dir/Lib/mk20dx.c.obj -[ 23%] Building C object CMakeFiles/kiibohd.elf.dir/Lib/delay.c.obj -[ 29%] Building C object CMakeFiles/kiibohd.elf.dir/Scan/MD1/scan_loop.c.obj -[ 35%] Building C object CMakeFiles/kiibohd.elf.dir/Scan/MatrixARM/matrix_scan.c.obj -[ 41%] Building C object CMakeFiles/kiibohd.elf.dir/Macro/PartialMap/macro.c.obj -[ 47%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/output_com.c.obj -[ 52%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_desc.c.obj -[ 58%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_dev.c.obj -[ 64%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_keyboard.c.obj -[ 70%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_mem.c.obj -[ 76%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_serial.c.obj -[ 82%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/cli/cli.c.obj -[ 88%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/led/led.c.obj -[ 94%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/print/print.c.obj -Linking C executable kiibohd.elf -[ 94%] Built target kiibohd.elf -Scanning dependencies of target SizeAfter -[100%] Chip usage for mk20dx128vlf5 - SRAM: 32% 5384/16384 bytes - Flash: 18% 23296/126976 bytes -[100%] Built target SizeAfter -``` +Licensing is done on a per-file basis. +Some of the source code is from [PJRC/Teensy](http://pjrc.com), other source code is from the [McHck Project](https://mchck.org). +Code written specifically for the Kiibohd Controller use the following licenses: -### NOTES: - -If you get the following error, you have not setup wincmake correctly: - -```bash -$ make -[ 5%] Generating KLL Layout -Scanning dependencies of target kiibohd.elf -[ 11%] Building C object CMakeFiles/kiibohd.elf.dir/main.c.o -../main.c:28:19: fatal error: macro.h: No such file or directory - #include <macro.h> - ^ -compilation terminated. -CMakeFiles/kiibohd.elf.dir/build.make:67: recipe for target 'CMakeFiles/kiibohd.elf.dir/main.c.o' failed -make[2]: *** [CMakeFiles/kiibohd.elf.dir/main.c.o] Error 1 -CMakeFiles/Makefile2:98: recipe for target 'CMakeFiles/kiibohd.elf.dir/all' failed -make[1]: *** [CMakeFiles/kiibohd.elf.dir/all] Error 2 -Makefile:75: recipe for target 'all' failed -make: *** [all] Error 2 -``` - -If you have already added the line to your `~/.bashrc` try restarting your -cygwin shell. +* MIT +* GPLv3 +* Public Domain -Windows Loading Firmware ------------------------- -First place the keyboard into re-flash mode. This can be done either by -pressing the re-flash button on the PCB/Teensy. Or by entering the Kiibohd -Virtual Serial Interface and using the `reload` command. - -The `load` script that is created during the build can load the firmware over -USB. - -To load the newly built firmware: `./load` - -Be patient the couple of times, Windows is slow at installing drivers... - - -Mac OS X Building ------------------ - -From this directory. - -```bash -$ mkdir build -$ cd build -$ cmake .. -$ make -``` - -Example output: - -> TODO - - -Mac OS X Loading Firmware -------------------------- - -First place the keyboard into re-flash mode. This can be done either by -pressing the re-flash button on the PCB/Teensy. Or by entering the Kiibohd -Virtual Serial Port and using the `reload` command. - -The `load` script that is created during the build can load the firmware over -USB. - -To load the newly built firmware: `./load`. - - -Virtual Serial Port - CLI -------------------------- - -Rather than use a special program that can interpret Raw HID, this controller exposes a USB Serial CDC endpoint. -This allows for you to use a generic serial terminal to debug/control the keyboard firmware (e.g. Tera Term, minicom, screen) - +Contact +------- -### Linux - -I generally use screen. You will need sudo/root priviledges if you haven't -installed the `98-kiibohd.rules` file to `/etc/udev/rules.d`. - -``` -$ screen /dev/ttyACM0 -# (Might be ACM1, ACM2, etc.) -``` - -### Windows - -Make sure the Teensy Virtual Serial Port driver is installed. If possible use -screen (as part of Cygwin). Check which COM port the virtual serial port has -been assigned to: `Device Manager->Ports (COM & LPT)->Teensy USB Serial`. In -brackets it will say which COM port (e.g. COM3) - -putty works well when using DTR/DSR or RTS/CTS flow control. - -| Setting | Value | -| --------------- | ------------------------------------- | -| Connection type | Serial | -| Serial line | Your COM port, e.g. COM3 | -| Speed | doesn't matter, it's auto-negotiated | +If you really need to get a hold of HaaTa, email is best: `haata@kiibohd.com` -Under `Category->Connections->Serial`: `Flow control: DTR/DSR`. - -If stuff is hard to read (you have a dumb colour scheme): -`Category->Window->Colours->Use system color`. That seems to make text at -least readable - -> I use a custom colour scheme that makes each colour easy to see. -> -HaaTa. - -Unfortunately, screen for Cygwin seems to be broken for serial ports, but you -can try it... +IRC is likely faster though. +`#geekhack@irc.freenode.net` +`#deskthority@irc.freenode.net` -```bash -$ screen /dev/ttyS2 -# Might be a different file, ttyS0, ttyACM0, ttyUSB0, etc. -``` - -Gnu screen doesn't seem to echo all the characters (it works though). -I believe it's a problem with stty, but I don't know how to fix it... - -### Mac OS X - -I recommend screen (can be installed via Macports). - -```bash -$ screen /dev/tty.<usb something> -```
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/README.old.markdown Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,750 @@ +The Kiibohd Controller +====================== + +This README is a bit long, just look at the sections you are interested in. +You only need to install avr-gcc if you want to build for the Teensy 2.0/2.0++. +Everything else needs an arm-none-eabi-gcc compiler (e.g. Infinity keyboard, +Teensy 3.0/3.1, McHCK). + +Linux is the ideal build environment (preferably recent'ish). In the near +future I'll make available an Arch Linux VM for building/manufacturing tests. + +Building on Mac should be ok for 99% of users with Macports or Homebrew. For +Homebrew, use `brew tap PX4/homebrew-px4` to get the arm-none-eabi-gcc installer. +The dfu Bootloader will not build correctly with the old version of +arm-none-eabi-gcc that Macports currently has (4.7.3). This is due to a bug +with lto (link time optimizations) which makes the resulting binary too big to +fit on the chip (must be less than 4096 Bytes). + +Building on Windows should also be fine for 99% of users, but takes a bunch of +work to setup (because Windows is a crappy dev environment). Cygwin is +currently required along with some non-Cygwin compilers and utilities (because +they are not available for Cygwin). The dfu Bootloader will not build because +of a Make 3.81+ bug/feature that removed support for non-Unix (Windows) +filenames as dependencies of targets. If you [replace the version of Make in +Cygwin](http://stackoverflow.com/questions/601516/cygwin-make-error-target-pattern-contains-no) +it should work. However, make sure that the flash size is no larger than 4096 +Bytes or the bootloader will not work. Things will likely break if there are +**SPACES IN YOUR PATHS**. I install cygwin to `C:\cygwin64`. If you are brave +and have programming knowledge, I will accept patches to fix any issues +regarding spaces in paths. + +Please give authors credit for modules used if you use in a distributed +product :D + + +General Dependencies +-------------------- + +Below listed are the Arch Linux pacman names, AUR packages may be required. + +These depend a bit on which targets you are trying to build, but the general +one: + +- cmake (2.8 and higher) +- git +- ctags (recommended, not required) +- python3 +- libusb1.0 (and -devel) +- make + +AVR Specific (Teensy 1.0/++,2.0/++) (try to use something recent, suggested +versions below) + +- avr-gcc (~4.8.0) +- avr-binutils (~2.23.2) +- avr-libc (~1.8.0) + +ARM Specific (Teensy 3.0/3.1, Infinity Keyboard, McHCK) + +- Arch Linux / Mac Ports + - arm-none-eabi-gcc + - arm-none-eabi-binutils + +- Windows (https://launchpad.net/gcc-arm-embedded/+download) + - gcc-arm-none-eabi (win32.zip) + + +Windows Setup +------------- + +Compiling on Windows does work, just it's a bunch more work. + +First make sure Cygwin is installed - http://www.cygwin.com/ - 32bit or 64bit +is fine. Make sure the following are installed: + +- make +- git (needed for some compilation info) +- cmake +- gcc-core +- gcc-g++ +- libusb1.0 +- libusb1.0-devel +- python3 +- ctags (recommended, not required) + +Please note, I use cygwin term exclusively for any command line options. +Unless mentioned otherwise, use it. Do NOT use CMD or Powershell. + +Also install the [Windows version of CMake](http://cmake.org/cmake/resources/software.html) +(3+ is ideal) - Select "Do not add CMake to system PATH". This is in addition +to the Cygwin version. This is an easier alternative to installing another C +compiler. Add the following line to your .bashrc, making sure the CMake path +is correct: + + echo "alias wincmake=\"PATH='/cygdrive/c/Program Files (x86)/CMake'/bin:'${PATH}' cmake -G 'Unix Makefiles'\"" >> ~/.bashrc + +Install the [PJRC Virtual Serial Port Driver](http://pjrc.com/teensy/serial_install.exe). + +Next, install the compiler(s) you want. + + +### AVR GCC + +You just need the +[Atmel AVR 8-bit Toolchain](http://www.atmel.com/tools/atmelavrtoolchainforwindows.aspx). +The latest should be fine, as of writing it was 3.4.3. + +Extract the files to a directory, say `C:\avr8-gnu-toolchain`. Then copy all +the folders in that directory to the Cygwin `/usr/local` directory. Mine is +`C:\cygwin64\usr\local`. (You can also just setup the paths, but this is +faster/simpler. Might screw up your Cygwin though). + + +### ARM EABI + +Download the latest +[GNU Tools for Embedded Processors +gcc-arm-none-eabi](https://launchpad.net/gcc-arm-embedded/+download). + +Download `gcc-arm-none-eabi*win32.zip`. + +Then extract all the folders/files in the zip to the Cygwin `/usr/local` +directory. Mine is `C:\cygwin64\usr\local`. Or, you can setup paths using +the installer (you have to be more careful, avoid spaces in paths). + + +CMake Info +---------- + +One of the big benefits of using CMake is the ability to build multiple +configurations (for different microcontrollers) at the same time. The +following sections explain in detail what each CMakeLists.txt configuration +option does and what you can change it to. However, it is possible to +configure each of these options using the `-D` command line flag. + +For example, to build the Infinity Keyboard default configuration: + +```bash +$ mkdir build_infinity +$ cd build_infinity +$ cmake -DCHIP=mk20dx128vlf5 -DScanModule=MD1 -DMacroModule=PartialMap \ + -DOutputModule=pjrcUSB -DDebugModule=full -DBaseMap=defaultMap \ + -DDefaultMap="md1Overlay stdFuncMap" -DPartialMaps="hhkbpro2" \ + .. +$ make +``` + +CMake defaults to the values specified in CMakeLists.txt if not overridden via +the command line. + +> NOTE: On Windows, you will have to use "wincmake" instead of "cmake". + + +Selecting Microcontroller +------------------------- + +This is where you select the chip you want to compile for. The build system +will automatically select the compiler needed to compile for your chip. + +Open up CMakeLists.txt in your favourite text editor. You are looking for: + +```cmake +### +# Chip Selection +# + +#| You _MUST_ set this to match the microcontroller you are trying to compile for +#| You _MUST_ clean the build directory if you change this value +#| +set( CHIP +# "at90usb162" # Teensy 1.0 (avr) +# "atmega32u4" # Teensy 2.0 (avr) +# "at90usb646" # Teensy++ 1.0 (avr) +# "at90usb1286" # Teensy++ 2.0 (avr) +# "mk20dx128" # Teensy 3.0 (arm) + "mk20dx128vlf5" # McHCK mk20dx128vlf5 +# "mk20dx256" # Teensy 3.1 (arm) + CACHE STRING "Microcontroller Chip" ) +``` + +Just uncomment the chip you want, and comment out the old one. + +> NOTE: If you change this option, you will *need* to delete the build +> directory that is created in the Building sections below. + + +Selecting Modules +----------------- + +> WARNING: Not all modules are compatible, and some modules may have +> dependencies on other modules. + +This is where the options start getting interesting. The Kiibohd Controller +is designed around a set of 4 types of modules that correspond to different +functionality: + +- Scan Module +- Macro Module +- Output Module +- Debug Module + +The Scan Module is where the most interesting stuff happens. These modules +take in "keypress data". A converter Scan Module will interpret a protocol +into key press/releases. A matrix Scan Module may inherit from the matrix +module to scan keypress from a matrix This module just has to give +press/release codes, but does have some callback control to other modules +depending on the lifecycle for press/release codes (this can be very +complicated depending on the protocol). Each Scan Module has it's own default +keymap/modifier map. (TODO recommend keymap changing in the Macro Module). + +Some scan modules have very specialized hardware requirements, each module +directory should have at least a link to the needed parts and/or schematics +(TODO!). + +The Macro Module takes care of the mapping of the key press/release code into +an Output (USB) scan code. Any layering, macros, keypress +intelligence/reaction is done here. + +The Output Module is the module dealing with output from the microcontroller. +Currently USB is the only output protocol. Different USB output +implementations are available, pjrc being the safest/least featureful one. +Debug capabilities may depend on the module selected. + +The Debug Module enables various things like the Teensy LED on errors, debug +terminal output. (TODO get true UART working in avr, not just arm) + +Open up CMakeLists.txt in your favourite text editor. Look for: + +```cmake +### +# Project Modules +# + +#| Note: This is the only section you probably want to modify +#| Each module is defined by it's own folder (e.g. Scan/Matrix represents the "Matrix" module) +#| All of the modules must be specified, as they generate the sources list of files to compile +#| Any modifications to this file will cause a complete rebuild of the project + +#| Please look at the {Scan,Macro,Output,Debug} for information on the modules and how to create new ones + +##| Deals with acquiring the keypress information and turning it into a key index +set( ScanModule "MD1" + CACHE STRING "Scan Module" ) + +##| Provides the mapping functions for DefaultMap and handles any macro processing before sending to the OutputModule +set( MacroModule "PartialMap" + CACHE STRING "Macro Module" ) + +##| Sends the current list of usb key codes through USB HID +set( OutputModule "pjrcUSB" + CACHE STRING "Output Module" ) + +##| Debugging source to use, each module has it's own set of defines that it sets +set( DebugModule "full" + CACHE STRING "Debug Module" ) +``` + +Look at each module individually for it's requirements. There is +chip/architecture dependency checking but some permutations of modules may not +be tested/compile. + +There are also CMake options for temporarily selecting modules. But it's +easier to just edit the file. e.g. `cmake -DScanModuleOverride=<module name>`. + + +Keymap Configuration +-------------------- + +This is where you define the layout for your keyboard. +Currently, the only way to define kebyoard layouts is using [KLL](https://www.overleaf.com/read/zzqbdwqjfwwf). + +KLL is built up of 3 different kinds of keymaps in total. +The BaseMap, DefaultMap and PartialMaps. + +For each type of keymap, it is possible to combine multiple .kll files together to create new ones using +the compiler. The order of the files matter, as the right-most file will overwrite any setting in the +previous files. + +> NOTE: Each keymap is done after the entire file is processed. This means that within the file the order +> of assignment doesa *not* matter (if you assign the same thing twice, then yes the most recent one +> takes priority). + + +BaseMap defines what the keyboard can do. This includes specific capabilities of the keyboard (such as USB), +the mapping of Scan Codes to USB Codes and any specific configurations for the keyboard. +In general, the BaseMap rarely needs to be changed. Usually only when adding a new keyboard to the firmware +does the Basemap need any modification. +The BaseMap is what both DefaultMap and PartialMaps are based upon. This allows for a common reference +when defining custom keymappings. + +> NOTE: Don't use defaultMap.kll to change your layouts. This will work, but they will not be portable. + + +The DefaultMap is the normal state of the keyboard, i.e. your default layer. +Using the BaseMap as a base, the DefaultMap is a modification of the BaseMap to what the keyboard should do. +Since the DefaultMap uses USB Code to USB Code translations, this means that keymaps used for one keyboard +will work with another keyboard. +For example, I use Colemak, so this means I only have to define Colemak once for every keyboard that supports +the kiibohd firmware. This is possible because every BaseMap defines the keyboard as a US ANSI like keyboard +layout. +The DefaultMap can also be thought of as Layer 0. + + +PartialMaps are optional keymaps that can be "stacked" on top of the DefaultMap. +They can be dynamically swapped out using the layer control capabilities: + +- layerLatch( `<layer number>` ) +- layerLock( `<layer number>` ) +- layerShift( `<layer number>` ) + +layerShift is usually what you want as it works just like a standard shift key. +layerLock is similar to the CapsLock key. While layerLatch is a latch, where only the next key you press +will use that layer (e.g. stickykeys). + +A unique aspect of KLL layers is that it's a true stack of layers. +When a layer is activated, only the keys that are specified by the layer will change. +This means, if you define a layer that only sets `CapsLock -> LCtrl` and `LCtrl->Capslock` only those keys +will change when you active the layer. All the other keys will use the layer that is "underneath" to +lookup the keypress (usually the DefaultMap). + +This means that you can combine .kll files statically using the compiler or dynamically using the firmware. + +You can set the max number of layers by changing the `stateWordSize` define in one of your kll files. +By default it is set to 8 in Macro/PartialMap/capabilities.kll. This means you can have up to 256 layers +total (this includes the DefaultMap). +You can increase this number to either 16 or 32 (this will use more Flash and RAM btw) which will give you +2^16 and 2^32 possible layers respectively (65 535 and 4 294 967 295). + + +```cmake +### +# Keymap Configuration (do not include the .kll extension) +# + +#| Do not include the .kll extension +#| * BaseMap maps the native keyboard scan codes to USB Codes so the layout is compatible with all other layouts +#| * DefaultMap allows the default keymap to be modified from the BaseMap +#| * PartialMaps is a set of dynamically set layers (there is no limit, but too many may use up too much RAM...) +#| BaseMap generally does not need to be changed from "defaultMap" +#| +#| Syntax: +#| myMap +#| * defines a single .kll layout file, double-quotes are needed to distinguish between layers +#| "myMap specialLayer" +#| * defines myMap to be the main layout, then replace specialLayers on top of it +#| +#| - Only for PartialMaps - +#| "myMap specialLayer" "myMap colemak" dvorak +#| * As before, but also generates a second layer at index 2 and third at index 3 +#| +#| NOTE: Remember to add key(s) to enable each Partial Layer +#| NOTE2: Layers are always based up the BaseMap (which should be an ANSI-like mapping) +#| NOTE3: Compiler looks in kll/layouts and the build directory for layout files (precedence on build directory) + +##| Set the base keyboard .kll map, defaults to "defaultMap" if not found +##| Looks in Scan/<Module Name> for the available BaseMaps +set( BaseMap "defaultMap" + CACHE STRING "KLL BaseMap/Scancode Keymapping" ) + +##| Layer additonal .kll maps on the BaseMap, layers are in order from 1st to nth +##| Can be set to "" +set( DefaultMap "md1Overlay stdFuncMap" + CACHE STRING "KLL DefaultMap" ) + +##| ParitalMaps available on top of the BaseMap. See above for syntax on specifying multiple layers vs. layering +##| Can be set to "" +set( PartialMaps "hhkbpro2" + CACHE STRING "KLL PartialMaps/Layer Definitions" ) +``` + + +Linux Building +-------------- + +From this directory. + +```bash +$ mkdir build +$ cd build +$ cmake .. +$ make +``` + +Example output: + +``` +$ cmake .. +-- Compiler Family: +arm +-- Chip Selected: +mk20dx128vlf5 +-- Chip Family: +mk20dx +-- CPU Selected: +cortex-m4 +-- Compiler Source Files: +Lib/mk20dx.c;Lib/delay.c +-- Bootloader Type: +dfu +-- Detected Scan Module Source Files: +Scan/MD1/scan_loop.c;Scan/MD1/../MatrixARM/matrix_scan.c +-- Detected Macro Module Source Files: +Macro/PartialMap/macro.c +-- Detected Output Module Source Files: +Output/pjrcUSB/output_com.c;Output/pjrcUSB/arm/usb_desc.c;Output/pjrcUSB/arm/usb_dev.c; +Output/pjrcUSB/arm/usb_keyboard.c;Output/pjrcUSB/arm/usb_mem.c;Output/pjrcUSB/arm/usb_serial.c +-- Detected Debug Module Source Files: +Debug/full/../cli/cli.c;Debug/full/../led/led.c;Debug/full/../print/print.c +-- Found Git: /usr/bin/git (found version "2.2.1") +-- Found Ctags: /usr/bin/ctags (found version "5.8") +-- Checking for latest kll version: +Current branch master is up to date. +-- Detected Layout Files: +/home/hyatt/Source/controller/Macro/PartialMap/capabilities.kll +/home/hyatt/Source/controller/Output/pjrcUSB/capabilities.kll +/home/hyatt/Source/controller/Scan/MD1/defaultMap.kll +/home/hyatt/Source/controller/kll/layouts/md1Overlay.kll +/home/hyatt/Source/controller/kll/layouts/stdFuncMap.kll +/home/hyatt/Source/controller/kll/layouts/hhkbpro2.kll +-- Configuring done +-- Generating done +-- Build files have been written to: /home/hyatt/Source/controller/build +[master]: make [~/Source/controller/build](hyatt@x230mas:pts/6) +[ 5%] Generating KLL Layout +Scanning dependencies of target kiibohd.elf +[ 11%] Building C object CMakeFiles/kiibohd.elf.dir/main.c.o +[ 17%] Building C object CMakeFiles/kiibohd.elf.dir/Lib/mk20dx.c.o +[ 23%] Building C object CMakeFiles/kiibohd.elf.dir/Lib/delay.c.o +[ 29%] Building C object CMakeFiles/kiibohd.elf.dir/Scan/MD1/scan_loop.c.o +[ 35%] Building C object CMakeFiles/kiibohd.elf.dir/Scan/MatrixARM/matrix_scan.c.o +[ 41%] Building C object CMakeFiles/kiibohd.elf.dir/Macro/PartialMap/macro.c.o +[ 47%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/output_com.c.o +[ 52%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_desc.c.o +[ 58%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_dev.c.o +[ 64%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_keyboard.c.o +[ 70%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_mem.c.o +[ 76%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_serial.c.o +[ 82%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/cli/cli.c.o +[ 88%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/led/led.c.o +[ 94%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/print/print.c.o +Linking C executable kiibohd.elf +[ 94%] Built target kiibohd.elf +Scanning dependencies of target SizeAfter +[100%] Chip usage for mk20dx128vlf5 + SRAM: 32% 5384/16384 bytes + Flash: 18% 23384/126976 bytes +[100%] Built target SizeAfter +``` + +Linux Loading Firmware +---------------------- + +First place the keyboard into re-flash mode. This can be done either by +pressing the re-flash button on the PCB/Teensy. Or by entering the Kiibohd +Virtual Serial Port and using the 'reload' command. + +The `load` script that is created during the build can load the firmware over +USB. Either run it with sudo, or install the `98-kiibohd.rules` to +`/etc/udev/rules.d` and run: `udevadm control --reload-rules`. + +To load the newly built firmware: `./load`. + + +Linux Building Bootloader +------------------------- + +> NOTE: Does not apply to Teensy based builds. + +From this directory. + +```bash +$ cd Bootloader +$ mkdir build +$ cd build +$ cmake .. +$ make +``` + +Example output: + +```bash +$ cmake .. +-- Compiler Family: +arm +-- Chip Selected: +mk20dx128vlf5 +-- Chip Family: +mk20dx +-- CPU Selected: +cortex-m4 +-- Compiler Source Files: +Lib/mk20dx.c;Lib/delay.c +-- Bootloader Type: +dfu +-- Bootloader Source Files: +main.c;dfu.c;dfu.desc.c;flash.c;kinetis.c;usb.c +-- Found Git: /usr/bin/git (found version "2.2.1") +-- Found Ctags: /usr/bin/ctags (found version "5.8") +-- Configuring done +-- Generating done +-- Build files have been written to: /home/hyatt/Source/controller/Bootloader/build +[master]: make [~/Source/controller/Bootloader/build](hyatt@x230mas:pts/6) +Scanning dependencies of target kiibohd_bootloader.elf +[ 11%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/main.c.o +[ 22%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/dfu.c.o +[ 33%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/dfu.desc.c.o +[ 44%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/flash.c.o +[ 55%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/kinetis.c.o +[ 66%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/usb.c.o +[ 77%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/home/hyatt/Source/controller/Lib/mk20dx.c.o +[ 88%] Building C object CMakeFiles/kiibohd_bootloader.elf.dir/home/hyatt/Source/controller/Lib/delay.c.o +Linking C executable kiibohd_bootloader.elf +[ 88%] Built target kiibohd_bootloader.elf +Scanning dependencies of target SizeAfter +[100%] Chip usage for mk20dx128vlf5 + SRAM: 19% 3176/16384 bytes + Flash: 2% 3736/126976 bytes +[100%] Built target SizeAfter +``` + + +Linux Loading Bootloader +------------------------ + +> NOTE: Does not apply to Teensy based builds. + +It's recommended to use an SWD-type flasher like a Bus Pirate. There is a +convenience script for loading the firmware once the system is setup. + +```bash +$ cd Bootloader/Scripts +$ ./swdLoad.bash +``` + +The above script requires Ruby, Ruby serial port module, git, and a +`/dev/buspirate` udev rule. + +Additional Notes: + +* https://github.com/mchck/mchck/wiki/Getting-Started (See Bus-Pirate section) +* https://wiki.archlinux.org/index.php/Bus_pirate + + +Windows Building +---------------- + +From this directory. + +```bash +$ mkdir build +$ cd build +$ wincmake .. +$ make +``` + +Example output: + +```bash +$ wincmake .. +-- Compiler Family: +arm +-- Chip Selected: +mk20dx128vlf5 +-- Chip Family: +mk20dx +-- CPU Selected: +cortex-m4 +-- Compiler Source Files: +Lib/mk20dx.c;Lib/delay.c +-- Bootloader Type: +dfu +-- Detected Scan Module Source Files: +Scan/MD1/scan_loop.c;Scan/MD1/../MatrixARM/matrix_scan.c +-- Detected Macro Module Source Files: +Macro/PartialMap/macro.c +-- Detected Output Module Source Files: +Output/pjrcUSB/output_com.c;Output/pjrcUSB/arm/usb_desc.c;Output/pjrcUSB/arm/usb_dev.c;Output/pjrcUSB/arm/usb_keyboard.c;Output/pjrcUSB/arm/usb_mem.c;Output/pjrcUSB/arm/usb_serial.c +-- Detected Debug Module Source Files: +Debug/full/../cli/cli.c;Debug/full/../led/led.c;Debug/full/../print/print.c +-- Found Git: C:/cygwin64/bin/git.exe (found version "2.1.1") +-- Found Ctags: C:/cygwin64/bin/ctags.exe (found version "5.8") +-- Checking for latest kll version: +Current branch master is up to date. +-- Detected Layout Files: +C:/cygwin64/home/Jacob/controller/Macro/PartialMap/capabilities.kll +C:/cygwin64/home/Jacob/controller/Output/pjrcUSB/capabilities.kll +C:/cygwin64/home/Jacob/controller/Scan/MD1/defaultMap.kll +C:/cygwin64/home/Jacob/controller/kll/layouts/md1Overlay.kll +C:/cygwin64/home/Jacob/controller/kll/layouts/stdFuncMap.kll +C:/cygwin64/home/Jacob/controller/kll/layouts/hhkbpro2.kll +-- Configuring done +-- Generating done +-- Build files have been written to: C:/cygwin64/home/Jacob/controller/build + +$ make +[ 5%] Generating KLL Layout +Scanning dependencies of target kiibohd.elf +[ 11%] Building C object CMakeFiles/kiibohd.elf.dir/main.c.obj +[ 17%] Building C object CMakeFiles/kiibohd.elf.dir/Lib/mk20dx.c.obj +[ 23%] Building C object CMakeFiles/kiibohd.elf.dir/Lib/delay.c.obj +[ 29%] Building C object CMakeFiles/kiibohd.elf.dir/Scan/MD1/scan_loop.c.obj +[ 35%] Building C object CMakeFiles/kiibohd.elf.dir/Scan/MatrixARM/matrix_scan.c.obj +[ 41%] Building C object CMakeFiles/kiibohd.elf.dir/Macro/PartialMap/macro.c.obj +[ 47%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/output_com.c.obj +[ 52%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_desc.c.obj +[ 58%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_dev.c.obj +[ 64%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_keyboard.c.obj +[ 70%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_mem.c.obj +[ 76%] Building C object CMakeFiles/kiibohd.elf.dir/Output/pjrcUSB/arm/usb_serial.c.obj +[ 82%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/cli/cli.c.obj +[ 88%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/led/led.c.obj +[ 94%] Building C object CMakeFiles/kiibohd.elf.dir/Debug/print/print.c.obj +Linking C executable kiibohd.elf +[ 94%] Built target kiibohd.elf +Scanning dependencies of target SizeAfter +[100%] Chip usage for mk20dx128vlf5 + SRAM: 32% 5384/16384 bytes + Flash: 18% 23296/126976 bytes +[100%] Built target SizeAfter +``` + +### NOTES: + +If you get the following error, you have not setup wincmake correctly: + +```bash +$ make +[ 5%] Generating KLL Layout +Scanning dependencies of target kiibohd.elf +[ 11%] Building C object CMakeFiles/kiibohd.elf.dir/main.c.o +../main.c:28:19: fatal error: macro.h: No such file or directory + #include <macro.h> + ^ +compilation terminated. +CMakeFiles/kiibohd.elf.dir/build.make:67: recipe for target 'CMakeFiles/kiibohd.elf.dir/main.c.o' failed +make[2]: *** [CMakeFiles/kiibohd.elf.dir/main.c.o] Error 1 +CMakeFiles/Makefile2:98: recipe for target 'CMakeFiles/kiibohd.elf.dir/all' failed +make[1]: *** [CMakeFiles/kiibohd.elf.dir/all] Error 2 +Makefile:75: recipe for target 'all' failed +make: *** [all] Error 2 +``` + +If you have already added the line to your `~/.bashrc` try restarting your +cygwin shell. + + +Windows Loading Firmware +------------------------ + +First place the keyboard into re-flash mode. This can be done either by +pressing the re-flash button on the PCB/Teensy. Or by entering the Kiibohd +Virtual Serial Interface and using the `reload` command. + +The `load` script that is created during the build can load the firmware over +USB. + +To load the newly built firmware: `./load` + +Be patient the couple of times, Windows is slow at installing drivers... + + +Mac OS X Building +----------------- + +From this directory. + +```bash +$ mkdir build +$ cd build +$ cmake .. +$ make +``` + +Example output: + +> TODO + + +Mac OS X Loading Firmware +------------------------- + +First place the keyboard into re-flash mode. This can be done either by +pressing the re-flash button on the PCB/Teensy. Or by entering the Kiibohd +Virtual Serial Port and using the `reload` command. + +The `load` script that is created during the build can load the firmware over +USB. + +To load the newly built firmware: `./load`. + + +Virtual Serial Port - CLI +------------------------- + +Rather than use a special program that can interpret Raw HID, this controller exposes a USB Serial CDC endpoint. +This allows for you to use a generic serial terminal to debug/control the keyboard firmware (e.g. Tera Term, minicom, screen) + + +### Linux + +I generally use screen. You will need sudo/root priviledges if you haven't +installed the `98-kiibohd.rules` file to `/etc/udev/rules.d`. + +``` +$ screen /dev/ttyACM0 +# (Might be ACM1, ACM2, etc.) +``` + +### Windows + +Make sure the Teensy Virtual Serial Port driver is installed. If possible use +screen (as part of Cygwin). Check which COM port the virtual serial port has +been assigned to: `Device Manager->Ports (COM & LPT)->Teensy USB Serial`. In +brackets it will say which COM port (e.g. COM3) + +putty works well when using DTR/DSR or RTS/CTS flow control. + +| Setting | Value | +| --------------- | ------------------------------------- | +| Connection type | Serial | +| Serial line | Your COM port, e.g. COM3 | +| Speed | doesn't matter, it's auto-negotiated | + +Under `Category->Connections->Serial`: `Flow control: DTR/DSR`. + +If stuff is hard to read (you have a dumb colour scheme): +`Category->Window->Colours->Use system color`. That seems to make text at +least readable + +> I use a custom colour scheme that makes each colour easy to see. +> -HaaTa. + +Unfortunately, screen for Cygwin seems to be broken for serial ports, but you +can try it... + +```bash +$ screen /dev/ttyS2 +# Might be a different file, ttyS0, ttyACM0, ttyUSB0, etc. +``` + +Gnu screen doesn't seem to echo all the characters (it works though). +I believe it's a problem with stty, but I don't know how to fix it... + +### Mac OS X + +I recommend screen (can be installed via Macports). + +```bash +$ screen /dev/tty.<usb something> +```
--- a/Scan/ADCTest/analog.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/ADCTest/analog.c Fri Jun 12 18:31:55 2015 -0700 @@ -57,7 +57,7 @@ uint32_t num; VREF_TRM = 0x60; - VREF_SC = 0xE1; // enable 1.2 volt ref + VREF_SC = 0xE1; // enable 1.2 volt ref if (analog_config_bits == 8) { ADC0_CFG1 = ADC_CFG1_24MHZ + ADC_CFG1_MODE(0);
--- a/Scan/ADCTest/scan_loop.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/ADCTest/scan_loop.c Fri Jun 12 18:31:55 2015 -0700 @@ -69,11 +69,11 @@ const CLIDictItem scanCLIDict[] = { #if defined(_mk20dx128_) || defined(_mk20dx256_) || defined(_mk20dx256vlh7_) // ARM { "adc", "Read the specified number of values from the ADC at the given pin: <pin> [# of reads]" - NL "\t\t See \033[35mLib/pin_map.teensy3\033[0m for ADC0 channel number.", cliFunc_adc }, + NL "\t\t See \033[35mLib/pin_map.teensy3\033[0m for ADC0 channel number.", cliFunc_adc }, { "adcInit", "Intialize/calibrate ADC: <ADC Resolution> <Vref> <Hardware averaging samples>" - NL "\t\tADC Resolution -> 8, 10, 12, 16 (bit)" - NL "\t\t Vref -> 0 (1.2 V), 1 (External)" - NL "\t\tHw Avg Samples -> 0 (disabled), 4, 8, 16, 32", cliFunc_adcInit }, + NL "\t\tADC Resolution -> 8, 10, 12, 16 (bit)" + NL "\t\t Vref -> 0 (1.2 V), 1 (External)" + NL "\t\tHw Avg Samples -> 0 (disabled), 4, 8, 16, 32", cliFunc_adcInit }, #endif #if defined(_mk20dx256_) || defined(_mk20dx256vlh7_) // DAC is only supported on Teensy 3.1 { "dac", "Set DAC output value, from 0 to 4095 (1/4096 Vref to Vref).", cliFunc_dac },
--- a/Scan/BudKeypad/matrix.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/BudKeypad/matrix.h Fri Jun 12 18:31:55 2015 -0700 @@ -1,15 +1,15 @@ /* Copyright (C) 2011 by Jacob Alexander - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE @@ -50,7 +50,7 @@ // Just layout the matrix by rows and columns // Usually you'll want to set the scanMode above to scanDual or scanCol_powrRow/scanRow_powrCol // The mode allows for optimization in the kind of scanning algorithms that are done -// +// // The key numbers are used to translate into the keymap table (array) (and always start from 1, not 0). // Thus if a row doesn't use all the key positions, you can denote it as 0, which will be ignored/skipped on each scan // See the keymap.h file for the various preconfigured arrays.
--- a/Scan/DPH/scan_loop.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/DPH/scan_loop.c Fri Jun 12 18:31:55 2015 -0700 @@ -609,7 +609,7 @@ PORTD &= ~D_MASK; PORTE &= ~E_MASK; - DDRB |= (1 << RECOVERY_SINK); // SINK pull + DDRB |= (1 << RECOVERY_SINK); // SINK pull PORTB |= (1 << RECOVERY_CONTROL); PORTB |= (1 << RECOVERY_SOURCE); // SOURCE high DDRB |= (1 << RECOVERY_SOURCE); @@ -619,7 +619,7 @@ PORTB &= ~(1 << RECOVERY_CONTROL); DDRB &= ~(1 << RECOVERY_SOURCE); PORTB &= ~(1 << RECOVERY_SOURCE); // SOURCE low - DDRB &= ~(1 << RECOVERY_SINK); // SINK high-imp + DDRB &= ~(1 << RECOVERY_SINK); // SINK high-imp } }
--- a/Scan/EpsonQX-10/scan_loop.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/EpsonQX-10/scan_loop.c Fri Jun 12 18:31:55 2015 -0700 @@ -149,7 +149,7 @@ // Setup the the USART interface for keyboard data input - + // Setup baud rate // 16 MHz / ( 16 * Baud ) = UBRR // Baud <- 1200 as per the spec (see datasheet archives), rounding to 1200.1 (as that's as accurate as the timer can be)
--- a/Scan/FACOM6684/scan_loop.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/FACOM6684/scan_loop.c Fri Jun 12 18:31:55 2015 -0700 @@ -103,7 +103,7 @@ inline void Scan_setup() { // Setup the the USART interface for keyboard data input - + // Setup baud rate // 16 MHz / ( 16 * Baud ) = UBRR // Baud: 4817 -> 16 MHz / ( 16 * 4817 ) = 207.5981 @@ -200,7 +200,7 @@ } } -// Send data +// Send data uint8_t Scan_sendData( uint8_t dataPayload ) { // Debug
--- a/Scan/HP150/scan_loop.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/HP150/scan_loop.c Fri Jun 12 18:31:55 2015 -0700 @@ -239,7 +239,7 @@ return 0; } -// Send data +// Send data uint8_t Scan_sendData( uint8_t dataPayload ) { return 0;
--- a/Scan/HeathZenith/matrix.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/HeathZenith/matrix.h Fri Jun 12 18:31:55 2015 -0700 @@ -1,15 +1,15 @@ /* Copyright (C) 2011 by Jacob Alexander - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--- a/Scan/IBMConvertible/matrix.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/IBMConvertible/matrix.h Fri Jun 12 18:31:55 2015 -0700 @@ -1,15 +1,15 @@ /* Copyright (C) 2012 by Jacob Alexander - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Scan/ISSILed/led_scan.c Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,706 @@ +/* Copyright (C) 2014-2015 by Jacob Alexander + * + * This file is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this file. If not, see <http://www.gnu.org/licenses/>. + */ + +// ----- Includes ----- + +// Compiler Includes +#include <Lib/ScanLib.h> + +// Project Includes +#include <cli.h> +#include <led.h> +#include <print.h> + +// Local Includes +#include "led_scan.h" + + + +// ----- Defines ----- + +#define I2C_TxBufferLength 300 +#define I2C_RxBufferLength 8 + +#define LED_BufferLength 144 + + +// ----- Structs ----- + +typedef struct I2C_Buffer { + uint16_t head; + uint16_t tail; + uint8_t sequencePos; + uint16_t size; + uint8_t *buffer; +} I2C_Buffer; + +typedef struct LED_Buffer { + uint8_t buffer[LED_BufferLength]; +} LED_Buffer; + + + +// ----- Function Declarations ----- + +// CLI Functions +void cliFunc_echo( char* args ); +void cliFunc_i2cRecv( char* args ); +void cliFunc_i2cSend( char* args ); +void cliFunc_ledTest( char* args ); +void cliFunc_ledZero( char* args ); + +uint8_t I2C_TxBufferPop(); +void I2C_BufferPush( uint8_t byte, I2C_Buffer *buffer ); +uint16_t I2C_BufferLen( I2C_Buffer *buffer ); +uint8_t I2C_Send( uint8_t *data, uint8_t sendLen, uint8_t recvLen ); + + + +// ----- Variables ----- + +// Scan Module command dictionary +CLIDict_Entry( i2cRecv, "Send I2C sequence of bytes and expect a reply of 1 byte on the last sequence." NL "\t\tUse |'s to split sequences with a stop." ); +CLIDict_Entry( i2cSend, "Send I2C sequence of bytes. Use |'s to split sequences with a stop." ); +CLIDict_Entry( ledTest, "Test out the led pages." ); +CLIDict_Entry( ledZero, "Zero out LED register pages (non-configuration)." ); + +CLIDict_Def( ledCLIDict, "ISSI LED Module Commands" ) = { + CLIDict_Item( i2cRecv ), + CLIDict_Item( i2cSend ), + CLIDict_Item( ledTest ), + CLIDict_Item( ledZero ), + { 0, 0, 0 } // Null entry for dictionary end +}; + + + +// Before sending the sequence, I2C_TxBuffer_CurLen is assigned and as each byte is sent, it is decremented +// Once I2C_TxBuffer_CurLen reaches zero, a STOP on the I2C bus is sent +volatile uint8_t I2C_TxBufferPtr[ I2C_TxBufferLength ]; +volatile uint8_t I2C_RxBufferPtr[ I2C_TxBufferLength ]; + +volatile I2C_Buffer I2C_TxBuffer = { 0, 0, 0, I2C_TxBufferLength, (uint8_t*)I2C_TxBufferPtr }; +volatile I2C_Buffer I2C_RxBuffer = { 0, 0, 0, I2C_RxBufferLength, (uint8_t*)I2C_RxBufferPtr }; + +LED_Buffer LED_pageBuffer; + +// A bit mask determining which LEDs are enabled in the ISSI chip +// 0x00 -> 0x11 +const uint8_t LED_ledEnableMask[] = { +0xE8, // I2C address +0x00, // Starting register address +0xFF, 0xFF, // C1-1 -> C1-16 +0xFF, 0xFF, // C2-1 -> C2-16 +0xFF, 0xFF, // C3-1 -> C3-16 +0xFF, 0xFF, // C4-1 -> C4-16 +0xFF, 0xFF, // C5-1 -> C5-16 +0xFF, 0xFF, // C6-1 -> C6-16 +0xFF, 0xFF, // C7-1 -> C7-16 +0xFF, 0xFF, // C8-1 -> C8-16 +0xFF, 0xFF, // C9-1 -> C9-16 +}; + +// XXX Pre-fill example of buffers +const uint8_t examplePage[] = { +0xE8, // I2C address +0x24, // Starting register address +0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, // C1-1 -> C1-16 +0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, // C2-1 -> C2-16 +0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, // C3-1 -> C3-16 +0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, // C4-1 -> C4-16 +0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, // C5-1 -> C5-16 +0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, // C6-1 -> C6-16 +0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, // C7-1 -> C7-16 +0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, // C8-1 -> C8-16 +0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, // C9-1 -> C9-16 +}; + + + +// ----- Interrupt Functions ----- + +void i2c0_isr() +{ + cli(); // Disable Interrupts + + uint8_t status = I2C0_S; // Read I2C Bus status + + // Master Mode Transmit + if ( I2C0_C1 & I2C_C1_TX ) + { + // Check current use of the I2C bus + // Currently sending data + if ( I2C_TxBuffer.sequencePos > 0 ) + { + // Make sure slave sent an ACK + if ( status & I2C_S_RXAK ) + { + // NACK Detected, disable interrupt + erro_print("I2C NAK detected..."); + I2C0_C1 = I2C_C1_IICEN; + + // Abort Tx Buffer + I2C_TxBuffer.head = 0; + I2C_TxBuffer.tail = 0; + I2C_TxBuffer.sequencePos = 0; + } + else + { + // Transmit byte + I2C0_D = I2C_TxBufferPop(); + } + } + // Receiving data + else if ( I2C_RxBuffer.sequencePos > 0 ) + { + // Master Receive, addr sent + if ( status & I2C_S_ARBL ) + { + // Arbitration Lost + erro_print("Arbitration lost..."); + // TODO Abort Rx + + I2C0_C1 = I2C_C1_IICEN; + I2C0_S = I2C_S_ARBL | I2C_S_IICIF; // Clear ARBL flag and interrupt + } + if ( status & I2C_S_RXAK ) + { + // Slave Address NACK Detected, disable interrupt + erro_print("Slave Address I2C NAK detected..."); + // TODO Abort Rx + + I2C0_C1 = I2C_C1_IICEN; + } + else + { + dbug_print("Attempting to read byte"); + I2C0_C1 = I2C_RxBuffer.sequencePos == 1 + ? I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST | I2C_C1_TXAK // Single byte read + : I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST; // Multi-byte read + } + } + else + { + /* + dbug_msg("STOP - "); + printHex( I2C_BufferLen( (I2C_Buffer*)&I2C_TxBuffer ) ); + print(NL); + */ + + // Delay around STOP to make sure it actually happens... + delayMicroseconds( 1 ); + I2C0_C1 = I2C_C1_IICEN; // Send STOP + delayMicroseconds( 7 ); + + // If there is another sequence, start sending + if ( I2C_BufferLen( (I2C_Buffer*)&I2C_TxBuffer ) < I2C_TxBuffer.size ) + { + // Clear status flags + I2C0_S = I2C_S_IICIF | I2C_S_ARBL; + + // Wait...till the master dies + while ( I2C0_S & I2C_S_BUSY ); + + // Enable I2C interrupt + I2C0_C1 = I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST | I2C_C1_TX; + + // Transmit byte + I2C0_D = I2C_TxBufferPop(); + } + } + } + // Master Mode Receive + else + { + // XXX Do we need to handle 2nd last byte? + //I2C0_C1 = I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST | I2C_C1_TXAK; // No STOP, Rx, NAK on recv + + // Last byte + if ( I2C_TxBuffer.sequencePos <= 1 ) + { + // Change to Tx mode + I2C0_C1 = I2C_C1_IICEN | I2C_C1_MST | I2C_C1_TX; + + // Grab last byte + I2C_BufferPush( I2C0_D, (I2C_Buffer*)&I2C_RxBuffer ); + + delayMicroseconds( 1 ); // Should be enough time before issuing the stop + I2C0_C1 = I2C_C1_IICEN; // Send STOP + } + else + { + // Retrieve data + I2C_BufferPush( I2C0_D, (I2C_Buffer*)&I2C_RxBuffer ); + } + } + + I2C0_S = I2C_S_IICIF; // Clear interrupt + + sei(); // Re-enable Interrupts +} + + + +// ----- Functions ----- + +inline void I2C_setup() +{ + // Enable I2C internal clock + SIM_SCGC4 |= SIM_SCGC4_I2C0; // Bus 0 + + // External pull-up resistor + PORTB_PCR0 = PORT_PCR_ODE | PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(2); + PORTB_PCR1 = PORT_PCR_ODE | PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(2); + + // SCL Frequency Divider + // 400kHz -> 120 (0x85) @ 48 MHz F_BUS + I2C0_F = 0x85; + I2C0_FLT = 4; + I2C0_C1 = I2C_C1_IICEN; + I2C0_C2 = I2C_C2_HDRS; // High drive select +//}, + + // Enable I2C Interrupt + NVIC_ENABLE_IRQ( IRQ_I2C0 ); +} + +void LED_zeroPages( uint8_t startPage, uint8_t numPages, uint8_t startReg, uint8_t endReg ) +{ + // Page Setup + uint8_t pageSetup[] = { 0xE8, 0xFD, 0x00 }; + + // Max length of a page + chip id + reg start + uint8_t fullPage[ 0xB4 + 2 ] = { 0 }; // Max size of page + fullPage[0] = 0xE8; // Set chip id + fullPage[1] = startReg; // Set start reg + + // Iterate through given pages, zero'ing out the given register regions + for ( uint8_t page = startPage; page < startPage + numPages; page++ ) + { + // Set page + pageSetup[2] = page; + + // Setup page + while ( I2C_Send( pageSetup, sizeof( pageSetup ), 0 ) == 0 ) + delay(1); + + // Zero out page + while ( I2C_Send( fullPage, endReg - startReg + 2, 0 ) == 0 ) + delay(1); + } +} + +void LED_sendPage( uint8_t *buffer, uint8_t len, uint8_t page ) +{ + // Page Setup + uint8_t pageSetup[] = { 0xE8, 0xFD, page }; + + // Setup page + while ( I2C_Send( pageSetup, sizeof( pageSetup ), 0 ) == 0 ) + delay(1); + + // Write page to I2C Tx Buffer + while ( I2C_Send( buffer, len, 0 ) == 0 ) + delay(1); + +} + +void LED_writeReg( uint8_t reg, uint8_t val, uint8_t page ) +{ + // Page Setup + uint8_t pageSetup[] = { 0xE8, 0xFD, page }; + + // Reg Write Setup + uint8_t writeData[] = { 0xE8, reg, val }; + + // Setup page + while ( I2C_Send( pageSetup, sizeof( pageSetup ), 0 ) == 0 ) + delay(1); + + while ( I2C_Send( writeData, sizeof( writeData ), 0 ) == 0 ) + delay(1); +} + +// Setup +inline void LED_setup() +{ + // Register Scan CLI dictionary + CLI_registerDictionary( ledCLIDict, ledCLIDictName ); + + // Initialize I2C + I2C_setup(); + + // Zero out Frame Registers + // This needs to be done before disabling the hardware shutdown (or the leds will do undefined things) + LED_zeroPages( 0x0B, 1, 0x00, 0x0C ); // Control Registers + + // Disable Hardware shutdown of ISSI chip (pull high) + GPIOD_PDDR |= (1<<1); + PORTD_PCR1 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1); + GPIOD_PSOR |= (1<<1); + + // Clear LED Pages + LED_zeroPages( 0x00, 8, 0x00, 0xB4 ); // LED Registers + + // Enable LEDs based upon mask + LED_sendPage( (uint8_t*)LED_ledEnableMask, sizeof( LED_ledEnableMask ), 0 ); + + // Disable Software shutdown of ISSI chip + LED_writeReg( 0x0A, 0x01, 0x0B ); +} + + +inline uint8_t I2C_BufferCopy( uint8_t *data, uint8_t sendLen, uint8_t recvLen, I2C_Buffer *buffer ) +{ + uint8_t reTurn = 0; + + // If sendLen is greater than buffer fail right away + if ( sendLen > buffer->size ) + return 0; + + // Calculate new tail to determine if buffer has enough space + // The first element specifies the expected number of bytes from the slave (+1) + // The second element in the new buffer is the length of the buffer sequence (+1) + uint16_t newTail = buffer->tail + sendLen + 2; + if ( newTail >= buffer->size ) + newTail -= buffer->size; + + if ( I2C_BufferLen( buffer ) < sendLen + 2 ) + return 0; + +/* + print("|"); + printHex( sendLen + 2 ); + print("|"); + printHex( *tail ); + print("@"); + printHex( newTail ); + print("@"); +*/ + + // If buffer is clean, return 1, otherwise 2 + reTurn = buffer->head == buffer->tail ? 1 : 2; + + // Add to buffer, already know there is enough room (simplifies adding logic) + uint8_t bufferHeaderPos = 0; + for ( uint16_t c = 0; c < sendLen; c++ ) + { + // Add data to buffer + switch ( bufferHeaderPos ) + { + case 0: + buffer->buffer[ buffer->tail ] = recvLen; + bufferHeaderPos++; + c--; + break; + + case 1: + buffer->buffer[ buffer->tail ] = sendLen; + bufferHeaderPos++; + c--; + break; + + default: + buffer->buffer[ buffer->tail ] = data[ c ]; + break; + } + + // Check for wrap-around case + if ( buffer->tail + 1 >= buffer->size ) + { + buffer->tail = 0; + } + // Normal case + else + { + buffer->tail++; + } + } + + return reTurn; +} + + +inline uint16_t I2C_BufferLen( I2C_Buffer *buffer ) +{ + // Tail >= Head + if ( buffer->tail >= buffer->head ) + return buffer->head + buffer->size - buffer->tail; + + // Head > Tail + return buffer->head - buffer->tail; +} + + +void I2C_BufferPush( uint8_t byte, I2C_Buffer *buffer ) +{ + // Make sure buffer isn't full + if ( buffer->tail + 1 == buffer->head || ( buffer->head > buffer->tail && buffer->tail + 1 - buffer->size == buffer->head ) ) + { + warn_msg("I2C_BufferPush failed, buffer full: "); + printHex( byte ); + print( NL ); + return; + } + + // Check for wrap-around case + if ( buffer->tail + 1 >= buffer->size ) + { + buffer->tail = 0; + } + // Normal case + else + { + buffer->tail++; + } + + // Add byte to buffer + buffer->buffer[ buffer->tail ] = byte; +} + + +uint8_t I2C_TxBufferPop() +{ + // Return 0xFF if no buffer left (do not rely on this) + if ( I2C_BufferLen( (I2C_Buffer*)&I2C_TxBuffer ) >= I2C_TxBuffer.size ) + { + erro_msg("No buffer to pop an entry from... "); + printHex( I2C_TxBuffer.head ); + print(" "); + printHex( I2C_TxBuffer.tail ); + print(" "); + printHex( I2C_TxBuffer.sequencePos ); + print(NL); + return 0xFF; + } + + // If there is currently no sequence being sent, the first entry in the RingBuffer is the length + if ( I2C_TxBuffer.sequencePos == 0 ) + { + I2C_TxBuffer.sequencePos = 0xFF; // So this doesn't become an infinite loop + I2C_RxBuffer.sequencePos = I2C_TxBufferPop(); + I2C_TxBuffer.sequencePos = I2C_TxBufferPop(); + } + + uint8_t data = I2C_TxBuffer.buffer[ I2C_TxBuffer.head ]; + + // Prune head + I2C_TxBuffer.head++; + + // Wrap-around case + if ( I2C_TxBuffer.head >= I2C_TxBuffer.size ) + I2C_TxBuffer.head = 0; + + // Decrement buffer sequence (until next stop will be sent) + I2C_TxBuffer.sequencePos--; + + /* + dbug_msg("Popping: "); + printHex( data ); + print(" "); + printHex( I2C_TxBuffer.head ); + print(" "); + printHex( I2C_TxBuffer.tail ); + print(" "); + printHex( I2C_TxBuffer.sequencePos ); + print(NL); + */ + return data; +} + + +uint8_t I2C_Send( uint8_t *data, uint8_t sendLen, uint8_t recvLen ) +{ + // Check head and tail pointers + // If full, return 0 + // If empty, start up I2C Master Tx + // If buffer is non-empty and non-full, just append to the buffer + switch ( I2C_BufferCopy( data, sendLen, recvLen, (I2C_Buffer*)&I2C_TxBuffer ) ) + { + // Not enough buffer space... + case 0: + /* + erro_msg("Not enough Tx buffer space... "); + printHex( I2C_TxBuffer.head ); + print(":"); + printHex( I2C_TxBuffer.tail ); + print("+"); + printHex( sendLen ); + print("|"); + printHex( I2C_TxBuffer.size ); + print( NL ); + */ + return 0; + + // Empty buffer, initialize I2C + case 1: + // Clear status flags + I2C0_S = I2C_S_IICIF | I2C_S_ARBL; + + // Check to see if we already have control of the bus + if ( I2C0_C1 & I2C_C1_MST ) + { + // Already the master (ah yeah), send a repeated start + I2C0_C1 = I2C_C1_IICEN | I2C_C1_MST | I2C_C1_RSTA | I2C_C1_TX; + } + // Otherwise, seize control + else + { + // Wait...till the master dies + while ( I2C0_S & I2C_S_BUSY ); + + // Now we're the master (ah yisss), get ready to send stuffs + I2C0_C1 = I2C_C1_IICEN | I2C_C1_MST | I2C_C1_TX; + } + + // Enable I2C interrupt + I2C0_C1 = I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST | I2C_C1_TX; + + // Depending on what type of transfer, the first byte is configured for R or W + I2C0_D = I2C_TxBufferPop(); + + return 1; + } + + // Dirty buffer, I2C already initialized + return 2; +} + + + +// LED State processing loop +inline uint8_t LED_scan() +{ + + // I2C Busy + // S & I2C_S_BUSY + //I2C_S_BUSY + + return 0; +} + + + +// ----- CLI Command Functions ----- + +void cliFunc_i2cSend( char* args ) +{ + char* curArgs; + char* arg1Ptr; + char* arg2Ptr = args; + + // Buffer used after interpretting the args, will be sent to I2C functions + // NOTE: Limited to 8 bytes currently (can be increased if necessary + #define i2cSend_BuffLenMax 8 + uint8_t buffer[ i2cSend_BuffLenMax ]; + uint8_t bufferLen = 0; + + // No \r\n by default after the command is entered + print( NL ); + info_msg("Sending: "); + + // Parse args until a \0 is found + while ( bufferLen < i2cSend_BuffLenMax ) + { + curArgs = arg2Ptr; // Use the previous 2nd arg pointer to separate the next arg from the list + CLI_argumentIsolation( curArgs, &arg1Ptr, &arg2Ptr ); + + // Stop processing args if no more are found + if ( *arg1Ptr == '\0' ) + break; + + // If | is found, end sequence and start new one + if ( *arg1Ptr == '|' ) + { + print("| "); + I2C_Send( buffer, bufferLen, 0 ); + bufferLen = 0; + continue; + } + + // Interpret the argument + buffer[ bufferLen++ ] = (uint8_t)numToInt( arg1Ptr ); + + // Print out the arg + dPrint( arg1Ptr ); + print(" "); + } + + print( NL ); + + I2C_Send( buffer, bufferLen, 0 ); +} + +void cliFunc_i2cRecv( char* args ) +{ + char* curArgs; + char* arg1Ptr; + char* arg2Ptr = args; + + // Buffer used after interpretting the args, will be sent to I2C functions + // NOTE: Limited to 8 bytes currently (can be increased if necessary + #define i2cSend_BuffLenMax 8 + uint8_t buffer[ i2cSend_BuffLenMax ]; + uint8_t bufferLen = 0; + + // No \r\n by default after the command is entered + print( NL ); + info_msg("Sending: "); + + // Parse args until a \0 is found + while ( bufferLen < i2cSend_BuffLenMax ) + { + curArgs = arg2Ptr; // Use the previous 2nd arg pointer to separate the next arg from the list + CLI_argumentIsolation( curArgs, &arg1Ptr, &arg2Ptr ); + + // Stop processing args if no more are found + if ( *arg1Ptr == '\0' ) + break; + + // If | is found, end sequence and start new one + if ( *arg1Ptr == '|' ) + { + print("| "); + I2C_Send( buffer, bufferLen, 0 ); + bufferLen = 0; + continue; + } + + // Interpret the argument + buffer[ bufferLen++ ] = (uint8_t)numToInt( arg1Ptr ); + + // Print out the arg + dPrint( arg1Ptr ); + print(" "); + } + + print( NL ); + + I2C_Send( buffer, bufferLen, 1 ); // Only 1 byte is ever read at a time with the ISSI chip +} + +void cliFunc_ledTest( char* args ) +{ + print( NL ); // No \r\n by default after the command is entered + LED_sendPage( (uint8_t*)examplePage, sizeof( examplePage ), 0 ); +} + +void cliFunc_ledZero( char* args ) +{ + print( NL ); // No \r\n by default after the command is entered + LED_zeroPages( 0x00, 8, 0x24, 0xB4 ); // Only PWMs +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Scan/ISSILed/led_scan.h Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,34 @@ +/* Copyright (C) 2014-2015 by Jacob Alexander + * + * This file is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this file. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __LED_SCAN_H +#define __LED_SCAN_H + +// ----- Includes ----- + +// Compiler Includes +#include <stdint.h> + + + +// ----- Functions ----- + +void LED_setup(); +uint8_t LED_scan(); + + +#endif // __LED_SCAN_H +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Scan/ISSILed/setup.cmake Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,30 @@ +###| CMake Kiibohd Controller Scan Module |### +# +# Written by Jacob Alexander in 2014-2015 for the Kiibohd Controller +# +# Released into the Public Domain +# +### + + +### +# Sub-module flag, cannot be included stand-alone +# +set ( SubModule 1 ) + + +### +# Module C files +# +set ( Module_SRCS + led_scan.c +) + + +### +# Compiler Family Compatibility +# +set ( ModuleCompatibility + arm +) +
--- a/Scan/MD1/pinout Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/MD1/pinout Fri Jun 12 18:31:55 2015 -0700 @@ -49,6 +49,19 @@ PTA1 - RX0 PTA2 - TX0 +* Tag Connect + +1 - Vdd +5 +2 - PTA3 / SWD_IO +3 - Vss / Gnd +4 - PTA0 / SWD_CLK +5 - +5V +6 - PTA2 / TRACE_SWO +7 - N/C +8 - PTA1 / JTAG_TDI +9 - N/C +10 - Reset_b + ------ |Unused|
--- a/Scan/MicroSwitch8304/scan_loop.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/MicroSwitch8304/scan_loop.c Fri Jun 12 18:31:55 2015 -0700 @@ -180,7 +180,7 @@ sei(); // Re-enable Interrupts } -// Send data +// Send data // // Keyboard Input Guide for Micro Switch 8304 // 0xBX is for LED F1,F2,Over Type,Lock
--- a/Scan/SonyNEWS/scan_loop.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/SonyNEWS/scan_loop.c Fri Jun 12 18:31:55 2015 -0700 @@ -92,7 +92,7 @@ // Configured as a Pull-up Input - This pin "can" be read as well, it will go to GND when the "Power On" switch is pressed, and will read ~5V otherwise // XXX Currently not used by the controller POWR_DDR &= ~(1 << POWR_POS); - POWR_PORT |= (1 << POWR_POS); + POWR_PORT |= (1 << POWR_POS); // Reset the keyboard before scanning, we might be in a wierd state scan_resetKeyboard();
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Scan/UARTConnect/capabilities.kll Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,31 @@ +Name = UARTConnectCapabilities; +Version = 0.1; +Author = "HaaTa (Jacob Alexander) 2015"; +KLL = 0.3a; + +# Modified Date +Date = 2015-03-15; + +# UART Buffer Size +# Number of bytes to reserve for each side of UARTConnect +# For true NKRO support must be at least: <# of Keys> x 3 + 5 +UARTConnectBufSize => UARTConnectBufSize_define; +UARTConnectBufSize = 128; # MDErgo1 requires at least a 119 byte buffer + +# UART Speed +# *NOTE* This must be changed on every device in the chain or else UARTConnect will not work +# The faster the speed, the lower the latency, but higher chance for an error +UARTConnectBaud => UARTConnectBaud_define; +UARTConnectBaudFine => UARTConnectBaudFine_define; +# Generally, leave BaudFine at zero unless trying to tune the link to an external UART +# You'll want to look at the specific chip datasheet for the exact equation +# +# Example of 115200 Baud using a 48 MHz clock (mk20dx128vlf5) +# 48 MHz / ( 16 * Baud ) = BDH/L +# Baud: 115200 -> 48 MHz / ( 16 * 115200 ) = 26.0416667 +# Thus baud setting = 26 +# NOTE: If finer baud adjustment is needed see UARTx_C4 -> BRFA in the datasheet +# Baud fine setting = 0x02 +UARTConnectBaud = 26; +UARTConnectBaudFine = 0x02; +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Scan/UARTConnect/connect_scan.c Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,908 @@ +/* Copyright (C) 2014-2015 by Jacob Alexander + * + * This file is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this file. If not, see <http://www.gnu.org/licenses/>. + */ + +// ----- Includes ----- + +// Compiler Includes +#include <Lib/ScanLib.h> + +// Project Includes +#include <cli.h> +#include <led.h> +#include <print.h> +#include <macro.h> + +// Local Includes +#include "connect_scan.h" + + + +// ----- Macros ----- + +// Macro for adding to each uart Tx ring buffer +#define uart_addTxBuffer( uartNum ) \ +case uartNum: \ + while ( uart##uartNum##_buffer_items + count > uart_buffer_size ) \ + { \ + warn_msg("Too much data to send on UART0, waiting..."); \ + delay( 1 ); \ + } \ + for ( uint8_t c = 0; c < count; c++ ) \ + { \ + printHex( buffer[ c ] ); \ + print( " +" #uartNum NL ); \ + uart##uartNum##_buffer[ uart##uartNum##_buffer_tail++ ] = buffer[ c ]; \ + uart##uartNum##_buffer_items++; \ + if ( uart##uartNum##_buffer_tail >= uart_buffer_size ) \ + uart##uartNum##_buffer_tail = 0; \ + if ( uart##uartNum##_buffer_head == uart##uartNum##_buffer_tail ) \ + uart##uartNum##_buffer_head++; \ + if ( uart##uartNum##_buffer_head >= uart_buffer_size ) \ + uart##uartNum##_buffer_head = 0; \ + } \ + break + +// Macro for popping from Tx ring buffer +#define uart_fillTxFifo( uartNum ) \ +{ \ + uint8_t fifoSize = ( ( UART##uartNum##_PFIFO & UART_PFIFO_TXFIFOSIZE ) >> 2 ); \ + if ( fifoSize == 0 ) \ + fifoSize = 1; \ + while ( UART##uartNum##_TCFIFO < fifoSize ) \ + { \ + if ( uart##uartNum##_buffer_items == 0 ) \ + break; \ + UART##uartNum##_D = uart##uartNum##_buffer[ uart##uartNum##_buffer_head++ ]; \ + uart##uartNum##_buffer_items--; \ + if ( uart##uartNum##_buffer_head >= uart_buffer_size ) \ + uart##uartNum##_buffer_head = 0; \ + } \ +} + +// Macro for processing UART Rx +#define uart_processRx( uartNum ) \ +{ \ + if ( !( UART##uartNum##_S1 & UART_S1_RDRF ) ) \ + return; \ + uint8_t available = UART##uartNum##_RCFIFO; \ + if ( available == 0 ) \ + { \ + available = UART##uartNum##_D; \ + UART##uartNum##_CFIFO = UART_CFIFO_RXFLUSH; \ + return; \ + } \ + while ( available-- > 0 ) \ + { \ + uint8_t byteRead = UART##uartNum##_D; \ + printHex( byteRead ); \ + print( "(" ); \ + printInt8( available ); \ + print( ") <-" ); \ + switch ( uart##uartNum##_rx_status ) \ + { \ + case UARTStatus_Wait: \ + print(" SYN "); \ + uart##uartNum##_rx_status = byteRead == 0x16 ? UARTStatus_SYN : UARTStatus_Wait; \ + break; \ + case UARTStatus_SYN: \ + print(" SOH "); \ + uart##uartNum##_rx_status = byteRead == 0x01 ? UARTStatus_SOH : UARTStatus_Wait; \ + break; \ + case UARTStatus_SOH: \ + { \ + print(" CMD "); \ + uint8_t byte = byteRead; \ + if ( byte <= Animation ) \ + { \ + uart##uartNum##_rx_status = UARTStatus_Command; \ + uart##uartNum##_rx_command = byte; \ + uart##uartNum##_rx_bytes_waiting = 0xFFFF; \ + } \ + else \ + { \ + uart##uartNum##_rx_status = UARTStatus_Wait; \ + } \ + switch ( uart##uartNum##_rx_command ) \ + { \ + case IdRequest: \ + Connect_receive_IdRequest( 0, (uint16_t*)&uart##uartNum##_rx_bytes_waiting, uartNum ); \ + uart##uartNum##_rx_status = UARTStatus_Wait; \ + break; \ + default: \ + print("###"); \ + break; \ + } \ + break; \ + } \ + case UARTStatus_Command: \ + { \ + print(" CMD "); \ + uint8_t (*rcvFunc)(uint8_t, uint16_t(*), uint8_t) = (uint8_t(*)(uint8_t, uint16_t(*), uint8_t))(Connect_receiveFunctions[ uart##uartNum##_rx_command ]); \ + if ( rcvFunc( byteRead, (uint16_t*)&uart##uartNum##_rx_bytes_waiting, uartNum ) ) \ + uart##uartNum##_rx_status = UARTStatus_Wait; \ + break; \ + } \ + default: \ + erro_msg("Invalid UARTStatus..."); \ + uart##uartNum##_rx_status = UARTStatus_Wait; \ + available++; \ + continue; \ + } \ + print( NL ); \ + } \ +} + +// Macros for locking/unlock Tx buffers +#define uart_lockTx( uartNum ) \ +{ \ + while ( uart##uartNum##_tx_status == UARTStatus_Wait ); \ + uart##uartNum##_tx_status = UARTStatus_Wait; \ +} + +#define uart_unlockTx( uartNum ) \ +{ \ + uart##uartNum##_tx_status = UARTStatus_Ready; \ +} + + + +// ----- Function Declarations ----- + +// CLI Functions +void cliFunc_connectCmd ( char *args ); +void cliFunc_connectIdl ( char *args ); +void cliFunc_connectMst ( char *args ); +void cliFunc_connectRst ( char *args ); +void cliFunc_connectSts ( char *args ); + + + +// ----- Variables ----- + +// Connect Module command dictionary +CLIDict_Entry( connectCmd, "Sends a command via UART Connect, first arg is which uart, next arg is the command, rest are the arguments." ); +CLIDict_Entry( connectIdl, "Sends N number of Idle commands, 2 is the default value, and should be sufficient in most cases." ); +CLIDict_Entry( connectMst, "Sets the device as master. Use argument of s to set as slave." ); +CLIDict_Entry( connectRst, "Resets both Rx and Tx connect buffers and state variables." ); +CLIDict_Entry( connectSts, "UARTConnect status." ); +CLIDict_Def( uartConnectCLIDict, "UARTConnect Module Commands" ) = { + CLIDict_Item( connectCmd ), + CLIDict_Item( connectIdl ), + CLIDict_Item( connectMst ), + CLIDict_Item( connectRst ), + CLIDict_Item( connectSts ), + { 0, 0, 0 } // Null entry for dictionary end +}; + + +// -- Connect Device Id Variables -- +uint8_t Connect_id = 255; // Invalid, unset +uint8_t Connect_master = 0; + + +// -- Rx Status Variables -- + +volatile UARTStatus uart0_rx_status; +volatile UARTStatus uart1_rx_status; +volatile uint16_t uart0_rx_bytes_waiting; +volatile uint16_t uart1_rx_bytes_waiting; +volatile Command uart0_rx_command; +volatile Command uart1_rx_command; + + +// -- Tx Status Variables -- + +volatile UARTStatus uart0_tx_status; +volatile UARTStatus uart1_tx_status; + + +// -- Ring Buffer Variables -- + +#define uart_buffer_size UARTConnectBufSize_define +volatile uint8_t uart0_buffer_head; +volatile uint8_t uart0_buffer_tail; +volatile uint8_t uart0_buffer_items; +volatile uint8_t uart0_buffer[uart_buffer_size]; +volatile uint8_t uart1_buffer_head; +volatile uint8_t uart1_buffer_tail; +volatile uint8_t uart1_buffer_items; +volatile uint8_t uart1_buffer[uart_buffer_size]; + +volatile uint8_t uarts_configured = 0; + + +// -- Ring Buffer Convenience Functions -- + +void Connect_addBytes( uint8_t *buffer, uint8_t count, uint8_t uart ) +{ + // Too big to fit into buffer + if ( count > uart_buffer_size ) + { + erro_msg("Too big of a command to fit into the buffer..."); + return; + } + + // Choose the uart + switch ( uart ) + { + uart_addTxBuffer( 0 ); + uart_addTxBuffer( 1 ); + default: + erro_msg("Invalid UART to send from..."); + break; + } +} + + +// -- Connect send functions -- + +// patternLen defines how many bytes should the incrementing pattern have +void Connect_send_CableCheck( uint8_t patternLen ) +{ + // Wait until the Tx buffers are ready, then lock them + uart_lockTx( 0 ); + uart_lockTx( 1 ); + + // Prepare header + uint8_t header[] = { 0x16, 0x01, CableCheck, patternLen }; + + // Send header + Connect_addBytes( header, sizeof( header ), 1 ); // Master + Connect_addBytes( header, sizeof( header ), 0 ); // Slave + + // Send 0xD2 (11010010) for each argument + uint8_t value = 0xD2; + for ( uint8_t c = 0; c < patternLen; c++ ) + { + Connect_addBytes( &value, 1, 1 ); // Master + Connect_addBytes( &value, 1, 0 ); // Slave + } + + // Release Tx buffers + uart_unlockTx( 0 ); + uart_unlockTx( 1 ); +} + +void Connect_send_IdRequest() +{ + // Lock master bound Tx + uart_lockTx( 1 ); + + // Prepare header + uint8_t header[] = { 0x16, 0x01, IdRequest }; + + // Send header + Connect_addBytes( header, sizeof( header ), 1 ); // Master + + // Unlock Tx + uart_unlockTx( 1 ); +} + +// id is the value the next slave should enumerate as +void Connect_send_IdEnumeration( uint8_t id ) +{ + // Lock slave bound Tx + uart_lockTx( 0 ); + + // Prepare header + uint8_t header[] = { 0x16, 0x01, IdEnumeration, id }; + + // Send header + Connect_addBytes( header, sizeof( header ), 0 ); // Slave + + // Unlock Tx + uart_unlockTx( 0 ); +} + +// id is the currently assigned id to the slave +void Connect_send_IdReport( uint8_t id ) +{ + // Lock master bound Tx + uart_lockTx( 1 ); + + // Prepare header + uint8_t header[] = { 0x16, 0x01, IdReport, id }; + + // Send header + Connect_addBytes( header, sizeof( header ), 1 ); // Master + + // Unlock Tx + uart_unlockTx( 1 ); +} + +// id is the currently assigned id to the slave +// scanCodeStateList is an array of [scancode, state]'s (8 bit values) +// numScanCodes is the number of scan codes to parse from array +void Connect_send_ScanCode( uint8_t id, TriggerGuide *scanCodeStateList, uint8_t numScanCodes ) +{ + // Lock master bound Tx + uart_lockTx( 1 ); + + // Prepare header + uint8_t header[] = { 0x16, 0x01, ScanCode, id, numScanCodes }; + + // Send header + Connect_addBytes( header, sizeof( header ), 1 ); // Master + + // Send each of the scan codes + Connect_addBytes( (uint8_t*)scanCodeStateList, numScanCodes * TriggerGuideSize, 1 ); // Master + + // Unlock Tx + uart_unlockTx( 1 ); +} + +// id is the currently assigned id to the slave +// paramList is an array of [param, value]'s (8 bit values) +// numParams is the number of params to parse from the array +void Connect_send_Animation( uint8_t id, uint8_t *paramList, uint8_t numParams ) +{ + // Lock slave bound Tx + uart_lockTx( 0 ); + + // Prepare header + uint8_t header[] = { 0x16, 0x01, Animation, id, numParams }; + + // Send header + Connect_addBytes( header, sizeof( header ), 0 ); // Slave + + // Send each of the scan codes + Connect_addBytes( paramList, numParams, 0 ); // Slave + + // Unlock Tx + uart_unlockTx( 0 ); +} + +void Connect_send_Idle( uint8_t num ) +{ + // Wait until the Tx buffers are ready, then lock them + uart_lockTx( 0 ); + uart_lockTx( 1 ); + + // Send n number of idles to reset link status (if in a bad state) + uint8_t value = 0x16; + for ( uint8_t c = 0; c < num; c++ ) + { + Connect_addBytes( &value, 1, 1 ); // Master + Connect_addBytes( &value, 1, 0 ); // Slave + } + + // Release Tx buffers + uart_unlockTx( 0 ); + uart_unlockTx( 1 ); +} + + +// -- Connect receive functions -- + +// - Cable Check variables - +uint32_t Connect_cableFaultsMaster = 0; +uint32_t Connect_cableFaultsSlave = 0; +uint8_t Connect_cableOkMaster = 0; +uint8_t Connect_cableOkSlave = 0; + +uint8_t Connect_receive_CableCheck( uint8_t byte, uint16_t *pending_bytes, uint8_t to_master ) +{ + // Check if this is the first byte + if ( *pending_bytes == 0xFFFF ) + { + dbug_msg("PENDING SET -> "); + printHex( byte ); + print(" "); + *pending_bytes = byte; + printHex( *pending_bytes ); + print( NL ); + } + // Verify byte + else + { + (*pending_bytes)--; + + // The argument bytes are always 0xD2 (11010010) + if ( byte != 0xD2 ) + { + warn_print("Cable Fault!"); + + // Check which side of the chain + if ( to_master ) + { + Connect_cableFaultsMaster++; + Connect_cableOkMaster = 0; + print(" Master "); + } + else + { + Connect_cableFaultsSlave++; + Connect_cableOkSlave = 0; + print(" Slave "); + } + printHex( byte ); + print( NL ); + + // Signal that the command should wait for a SYN again + return 1; + } + } + + // If cable check was successful, set cable ok + if ( *pending_bytes == 0 ) + { + if ( to_master ) + { + Connect_cableOkMaster = 1; + } + else + { + Connect_cableOkSlave = 1; + } + } + dbug_msg("CABLECHECK RECEIVE - "); + printHex( byte ); + print(" "); + printHex( *pending_bytes ); + print(NL); + + // Check whether the cable check has finished + return *pending_bytes == 0 ? 1 : 0; +} + +uint8_t Connect_receive_IdRequest( uint8_t byte, uint16_t *pending_bytes, uint8_t to_master ) +{ + dbug_print("IdRequest"); + // Check the directionality + if ( !to_master ) + { + erro_print("Invalid IdRequest direction..."); + } + + // Check if master, begin IdEnumeration + if ( Connect_master ) + { + // The first device is always id 1 + // Id 0 is reserved for the master + Connect_send_IdEnumeration( 1 ); + } + // Propagate IdRequest + else + { + Connect_send_IdRequest(); + } + + return 1; +} + +uint8_t Connect_receive_IdEnumeration( uint8_t id, uint16_t *pending_bytes, uint8_t to_master ) +{ + dbug_print("IdEnumeration"); + // Check the directionality + if ( to_master ) + { + erro_print("Invalid IdEnumeration direction..."); + } + + // Set the device id + Connect_id = id; + + // Send reponse back to master + Connect_send_IdReport( id ); + + // Propogate next Id if the connection is ok + if ( Connect_cableOkSlave ) + { + Connect_send_IdEnumeration( id + 1 ); + } + + return 1; +} + +uint8_t Connect_receive_IdReport( uint8_t id, uint16_t *pending_bytes, uint8_t to_master ) +{ + dbug_print("IdReport"); + // Check the directionality + if ( !to_master ) + { + erro_print("Invalid IdRequest direction..."); + } + + // Track Id response if master + if ( Connect_master ) + { + // TODO, setup id's + info_msg("Id Reported: "); + printHex( id ); + print( NL ); + return 1; + } + // Propagate id if yet another slave + else + { + Connect_send_IdReport( id ); + } + + return 1; +} + +// - Scan Code Variables - +TriggerGuide Connect_receive_ScanCodeBuffer; +uint8_t Connect_receive_ScanCodeBufferPos; +uint8_t Connect_receive_ScanCodeDeviceId; + +uint8_t Connect_receive_ScanCode( uint8_t byte, uint16_t *pending_bytes, uint8_t to_master ) +{ + dbug_print("ScanCode"); + // Check the directionality + if ( !to_master ) + { + erro_print("Invalid ScanCode direction..."); + } + + // Master node, trigger scan codes + if ( Connect_master ) switch ( (*pending_bytes)-- ) + { + case 0xFFFF: // Device Id + Connect_receive_ScanCodeDeviceId = byte; + break; + + case 0xFFFE: // Number of TriggerGuides in bytes (byte * 3) + *pending_bytes = byte * 3; + Connect_receive_ScanCodeBufferPos = 0; + break; + + default: + // Set the specific TriggerGuide entry + ((uint8_t*)&Connect_receive_ScanCodeBuffer)[ Connect_receive_ScanCodeBufferPos++ ] = byte; + + // Reset the BufferPos if higher than 3 + // And send the TriggerGuide to the Macro Module + if ( Connect_receive_ScanCodeBufferPos > 3 ) + { + Connect_receive_ScanCodeBufferPos = 0; + Macro_triggerState( &Connect_receive_ScanCodeBuffer, 1 ); + } + + break; + } + // Propagate ScanCode packet + else switch ( (*pending_bytes)-- ) + { + case 0xFFFF: // Device Id + { + Connect_receive_ScanCodeDeviceId = byte; + + // Lock the master Tx buffer + uart_lockTx( 1 ); + + // Send header + Id byte + uint8_t header[] = { 0x16, 0x01, ScanCode, byte }; + Connect_addBytes( header, sizeof( header ), 1 ); // Master + break; + } + case 0xFFFE: // Number of TriggerGuides in bytes (byte * 3) + *pending_bytes = byte * 3; + Connect_receive_ScanCodeBufferPos = 0; + + // Pass through byte + Connect_addBytes( &byte, 1, 1 ); // Master + break; + + default: + // Pass through byte + Connect_addBytes( &byte, 1, 1 ); // Master + + // Unlock Tx Buffer after sending last byte + if ( *pending_bytes == 0 ) + uart_unlockTx( 1 ); + break; + } + + // Check whether the scan codes have finished sending + return *pending_bytes == 0 ? 1 : 0; +} + +uint8_t Connect_receive_Animation( uint8_t byte, uint16_t *pending_bytes, uint8_t to_master ) +{ + dbug_print("Animation"); + return 1; +} + + +// Baud Rate +// NOTE: If finer baud adjustment is needed see UARTx_C4 -> BRFA in the datasheet +uint16_t Connect_baud = UARTConnectBaud_define; // Max setting of 8191 +uint16_t Connect_baudFine = UARTConnectBaudFine_define; + +// Connect receive function lookup +void *Connect_receiveFunctions[] = { + Connect_receive_CableCheck, + Connect_receive_IdRequest, + Connect_receive_IdEnumeration, + Connect_receive_IdReport, + Connect_receive_ScanCode, + Connect_receive_Animation, +}; + + + +// ----- Interrupt Functions ----- + +// Master / UART0 ISR +void uart0_status_isr() +{ + // Process Rx buffer + uart_processRx( 0 ); +} + +// Slave / UART1 ISR +void uart1_status_isr() +{ + // Process Rx buffer + uart_processRx( 1 ); +} + + + +// ----- Functions ----- + +// Resets the state of the UART buffers and state variables +void Connect_reset() +{ + // Rx Status Variables + uart0_rx_status = UARTStatus_Wait; + uart1_rx_status = UARTStatus_Wait; + uart0_rx_bytes_waiting = 0; + uart1_rx_bytes_waiting = 0; + + // Tx Status Variables + uart0_tx_status = UARTStatus_Ready; + uart1_tx_status = UARTStatus_Ready; + + // Ring Buffer Variables + uart0_buffer_head = 0; + uart0_buffer_tail = 0; + uart0_buffer_items = 0; + uart1_buffer_head = 0; + uart1_buffer_tail = 0; + uart1_buffer_items = 0; +} + + +// Setup connection to other side +// - Only supports a single slave and master +// - If USB has been initiallized at this point, this side is the master +// - If both sides assert master, flash error leds +void Connect_setup( uint8_t master ) +{ + // Indication that UARTs are not ready + uarts_configured = 0; + + // Register Connect CLI dictionary + CLI_registerDictionary( uartConnectCLIDict, uartConnectCLIDictName ); + + Connect_master = master; + + // Master / UART0 setup + // Slave / UART1 setup + // Setup the the UART interface for keyboard data input + SIM_SCGC4 |= SIM_SCGC4_UART0; // Disable clock gating + SIM_SCGC4 |= SIM_SCGC4_UART1; // Disable clock gating + + // Pin Setup for UART0 / UART1 + // XXX TODO Set to actual (Teensy 3.1s don't have the correct pins available) + PORTB_PCR16 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); // RX Pin + PORTB_PCR17 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); // TX Pin + PORTC_PCR3 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); // RX Pin + PORTC_PCR4 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); // TX Pin + //PORTA_PCR1 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); // RX Pin + //PORTA_PCR2 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(2); // TX Pin + //PORTE_PCR0 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); // RX Pin + //PORTE_PCR1 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); // TX Pin + + // Baud Rate setting + UART0_BDH = (uint8_t)(Connect_baud >> 8); + UART0_BDL = (uint8_t)Connect_baud; + UART0_C4 = Connect_baudFine; + UART1_BDH = (uint8_t)(Connect_baud >> 8); + UART1_BDL = (uint8_t)Connect_baud; + UART1_C4 = Connect_baudFine; + + // 8 bit, Even Parity, Idle Character bit after stop + // NOTE: For 8 bit with Parity you must enable 9 bit transmission (pg. 1065) + // You only need to use UART0_D for 8 bit reading/writing though + // UART_C1_M UART_C1_PE UART_C1_PT UART_C1_ILT + UART0_C1 = UART_C1_M | UART_C1_PE | UART_C1_ILT; + UART1_C1 = UART_C1_M | UART_C1_PE | UART_C1_ILT; + + // Number of bytes in FIFO before TX Interrupt + // TODO Set 0 + UART0_TWFIFO = 1; + UART1_TWFIFO = 1; + + // Number of bytes in FIFO before RX Interrupt + UART0_RWFIFO = 1; + UART1_RWFIFO = 1; + + // Enable TX and RX FIFOs + UART0_PFIFO = UART_PFIFO_TXFE | UART_PFIFO_RXFE; + UART1_PFIFO = UART_PFIFO_TXFE | UART_PFIFO_RXFE; + + // Reciever Inversion Disabled, LSBF + // UART_S2_RXINV UART_S2_MSBF + UART0_S2 |= 0x00; + UART1_S2 |= 0x00; + + // Transmit Inversion Disabled + // UART_C3_TXINV + UART0_C3 |= 0x00; + UART1_C3 |= 0x00; + + // TX Enabled, RX Enabled, RX Interrupt Enabled + // UART_C2_TE UART_C2_RE UART_C2_RIE + UART0_C2 = UART_C2_TE | UART_C2_RE | UART_C2_RIE; + UART1_C2 = UART_C2_TE | UART_C2_RE | UART_C2_RIE; + + // Add interrupts to the vector table + NVIC_ENABLE_IRQ( IRQ_UART0_STATUS ); + NVIC_ENABLE_IRQ( IRQ_UART1_STATUS ); + + // UARTs are now ready to go + uarts_configured = 1; + + // Reset the state of the UART variables + Connect_reset(); +} + + +// Scan for updates in the master/slave +// - Interrupts will deal with most input functions +// - Used to send queries +// - SyncEvent is sent immediately once the current command is sent +// - SyncEvent is also blocking until sent +void Connect_scan() +{ + // Check if Tx Buffers are empty and the Tx Ring buffers have data to send + // This happens if there was previously nothing to send + if ( uart0_buffer_items > 0 && UART0_TCFIFO == 0 ) + uart_fillTxFifo( 0 ); + if ( uart1_buffer_items > 0 && UART1_TCFIFO == 0 ) + uart_fillTxFifo( 1 ); +} + + + +// ----- CLI Command Functions ----- + +void cliFunc_connectCmd( char* args ) +{ + // Parse number from argument + // NOTE: Only first argument is used + char* arg1Ptr; + char* arg2Ptr; + CLI_argumentIsolation( args, &arg1Ptr, &arg2Ptr ); + + print( NL ); + + switch ( numToInt( &arg1Ptr[0] ) ) + { + case CableCheck: + Connect_send_CableCheck( 2 ); + break; + + case IdRequest: + Connect_send_IdRequest(); + break; + + case IdEnumeration: + Connect_send_IdEnumeration( 5 ); + break; + + case IdReport: + Connect_send_IdReport( 8 ); + break; + + case ScanCode: + { + TriggerGuide scanCodes[] = { { 0x00, 0x01, 0x05 }, { 0x00, 0x03, 0x16 } }; + Connect_send_ScanCode( 10, scanCodes, 2 ); + break; + } + case Animation: + default: + break; + } +} + +void cliFunc_connectIdl( char* args ) +{ + // Parse number from argument + // NOTE: Only first argument is used + char* arg1Ptr; + char* arg2Ptr; + CLI_argumentIsolation( args, &arg1Ptr, &arg2Ptr ); + + print( NL ); + info_msg("Sending Sync Idles..."); + + uint8_t count = numToInt( &arg1Ptr[0] ); + // Default to 2 idles + if ( count == 0 ) + count = 2; + + Connect_send_Idle( count ); +} + +void cliFunc_connectMst( char* args ) +{ + // Parse number from argument + // NOTE: Only first argument is used + char* arg1Ptr; + char* arg2Ptr; + CLI_argumentIsolation( args, &arg1Ptr, &arg2Ptr ); + + print( NL ); + + switch ( arg1Ptr[0] ) + { + case 's': + case 'S': + info_msg("Setting device as slave."); + Connect_master = 0; + Connect_id = 0xFF; + break; + + case 'm': + case 'M': + default: + info_msg("Setting device as master."); + Connect_master = 1; + Connect_id = 0; + break; + } +} + +void cliFunc_connectRst( char* args ) +{ + print( NL ); + info_msg("Resetting UARTConnect state..."); + Connect_reset(); + + // TODO - Argument for re-sync +} + +void cliFunc_connectSts( char* args ) +{ + print( NL ); + info_msg("UARTConnect Status"); + print( NL "Device Type:\t" ); + print( Connect_master ? "Master" : "Slave" ); + print( NL "Device Id:\t" ); + printHex( Connect_id ); + print( NL "Master <=" NL "\tStatus:\t"); + printHex( Connect_cableOkMaster ); + print( NL "\tFaults:\t"); + printHex( Connect_cableFaultsMaster ); + print( NL "\tRx:\t"); + printHex( uart1_rx_status ); + print( NL "\tTx:\t"); + printHex( uart1_tx_status ); + print( NL "Slave <=" NL "\tStatus:\t"); + printHex( Connect_cableOkSlave ); + print( NL "\tFaults:\t"); + printHex( Connect_cableFaultsSlave ); + print( NL "\tRx:\t"); + printHex( uart0_rx_status ); + print( NL "\tTx:\t"); + printHex( uart0_tx_status ); +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Scan/UARTConnect/connect_scan.h Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,122 @@ +/* Copyright (C) 2014-2015 by Jacob Alexander + * + * This file is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this file. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __CONNECT_SCAN_H +#define __CONNECT_SCAN_H + +// ----- Includes ----- + +// Project Includes +#include <kll.h> + + + +// ----- Enums ----- + +// Functions +typedef enum Command { + CableCheck = 0, // Comm check + IdRequest = 1, // Slave initialization (request id from master) + IdEnumeration = 2, // Slave initialization (begin enumeration from master) + IdReport = 3, // Slave initialization complete, report id to master + ScanCode = 4, // ScanCode event status change + Animation = 5, // Master trigger animation event (same command is sent back to master when ready) +} Command; + +// UART Rx/Tx Status +typedef enum UARTStatus { + UARTStatus_Wait = 0, // Waiting Rx: for SYN Tx: for current command copy to finish + UARTStatus_SYN = 1, // Rx: SYN Received, waiting for SOH + UARTStatus_SOH = 2, // Rx: SOH Received, waiting for Command + UARTStatus_Command = 3, // Rx: Command Received, waiting for data + UARTStatus_Ready = 4, // Tx: Ready to receive commands +} UARTStatus; + + + +// ----- Structs ----- + +// UART Connect Commands + +// Cable Check Command +// Called on each UART every few seconds to make sure there is a connection +// Also used to make sure there aren't any serious problems with the cable with data corruption +// This command must pass before sending any other commands on the particular UART +// Each argument is always 0xD2 (11010010) +typedef struct CableCheckCommand { + Command command; + uint8_t numArgs; + uint8_t firstArg[0]; +} CableCheckCommand; + +// Id Request Command +// Issued by the slave device (non-master) whenever it is powered up +// Do not issue any commands until given an Id +// (Except for Cable Check and IdRequestCommand) +typedef struct IdRequestCommand { + Command command; +} IdRequestCommand; + +// Id Enumeration Command +// Issued by the master whenever an Id Request is received +// XXX Future work may include an "external capabilities" list in this command +typedef struct IdEnumerationCommand { + Command command; + uint8_t id; +} IdEnumerationCommand; + +// Id Report Command +// Issued by each slave to the master when assigned an Id +// XXX Future work will include an "external capabilities" list in this command +typedef struct IdReportCommand { + Command command; + uint8_t id; +} IdReportCommand; + +// Scan Code Command +// Sent from the slave to the master whenever there is a scan code state change +typedef struct ScanCodeCommand { + Command command; + uint8_t id; + uint8_t numScanCodes; + TriggerGuide firstScanCode[0]; +} ScanCodeCommand; + +// Animation Command +// Initiated by the master whenever an animation id should modify it's state +// Then after the leaf slave node receives the command, send it back to the master +// On the way back, each device can begin the animation adjustment +// +// The master->leaf command should indicate to each device that it should finish sending the +// current slave->master data and wait for the leaf->master command +// This allows for a tighter synchronization of animation events +typedef struct AnimationCommand { + Command command; + uint8_t animationId; + uint8_t numParams; + uint8_t firstParam[0]; +} AnimationCommand; + + + +// ----- Functions ----- + +void Connect_setup( uint8_t master ); +void Connect_scan(); + + +#endif // __CONNECT_SCAN_H +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Scan/UARTConnect/setup.cmake Fri Jun 12 18:31:55 2015 -0700 @@ -0,0 +1,30 @@ +###| CMake Kiibohd Controller Scan Module |### +# +# Written by Jacob Alexander in 2014-2015 for the Kiibohd Controller +# +# Released into the Public Domain +# +### + + +### +# Sub-module flag, cannot be included stand-alone +# +set ( SubModule 1 ) + + +### +# Module C files +# +set ( Module_SRCS + connect_scan.c +) + + +### +# Compiler Family Compatibility +# +set ( ModuleCompatibility + arm +) +
--- a/Scan/matrix/matrix_scan.c Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/matrix/matrix_scan.c Fri Jun 12 18:31:55 2015 -0700 @@ -39,7 +39,7 @@ // ----- Macros ----- // -- pinSetup Macros -- -#define REG_SET(reg) reg |= (1 << ( matrix[row*(MAX_ROW_SIZE+1)+col] % 10 ) ) // Modulo 10 for the define offset for each pin set 12 or 32 -> shift of 2 +#define REG_SET(reg) reg |= (1 << ( matrix[row*(MAX_ROW_SIZE+1)+col] % 10 ) ) // Modulo 10 for the define offset for each pin set 12 or 32 -> shift of 2 #define REG_UNSET(reg) reg &= ~(1 << ( matrix[row*(MAX_ROW_SIZE+1)+col] % 10 ) ) #define PIN_SET(pin,scan,direction) \ @@ -57,7 +57,7 @@ case scanDual: \ REG_SET(port##pin); break; \ case scanCol_powrRow: REG_UNSET(ddr##pin); REG_UNSET(DDR##pin); \ - REG_SET(port##pin); REG_SET(PORT##pin); break; \ + REG_SET(port##pin); REG_SET(PORT##pin); break; \ case powrRow: break; \ case powrCol: REG_SET(ddr##pin); REG_SET(DDR##pin); \ REG_SET(port##pin); REG_SET(PORT##pin); break; \ @@ -72,9 +72,9 @@ case scanDual: \ REG_SET(port##pin); break; \ case scanCol_powrRow: REG_SET(ddr##pin); REG_SET(DDR##pin); \ - REG_UNSET(port##pin); REG_UNSET(PORT##pin); break; \ + REG_UNSET(port##pin); REG_UNSET(PORT##pin); break; \ case powrRow: REG_SET(ddr##pin); REG_SET(DDR##pin); \ - REG_SET(port##pin); REG_SET(PORT##pin); break; \ + REG_SET(port##pin); REG_SET(PORT##pin); break; \ case powrCol: break; \ } \ break @@ -261,7 +261,7 @@ if ( showDebug == 0 ) // Only show once { matrix_debugPins(); - } + } } // Scans the given matrix determined by the scanMode method @@ -380,7 +380,7 @@ _delay_us( 1 ); col = 1; row = 1; - for ( ; col < (MAX_ROW_SIZE+1); col++ ) for ( ; row < (MAX_COL_SIZE+1); row++ ) + for ( ; col < (MAX_ROW_SIZE+1); col++ ) for ( ; row < (MAX_COL_SIZE+1); row++ ) { // Scan over the pins for each of the rows, and using the pin alias to determine which pin to set // (e.g. / 10 is for the pin name (A,B,C,etc.) and % 10 is for the position of the pin (A1,A2,etc.)) @@ -404,4 +404,4 @@ } #endif } - +
--- a/Scan/matrix/scan_loop.h Sun Mar 08 22:35:55 2015 -0700 +++ b/Scan/matrix/scan_loop.h Fri Jun 12 18:31:55 2015 -0700 @@ -46,7 +46,7 @@ // NOTE: Highest Bit: Valid keypress (0x80 is valid keypress) // Other Bits: Pressed state sample counter extern uint8_t KeyIndex_Array [KEYBOARD_KEYS + 1]; - static const uint8_t KeyIndex_Size = KEYBOARD_KEYS; + static const uint8_t KeyIndex_Size = KEYBOARD_KEYS; extern volatile uint8_t KeyIndex_Buffer[KEYBOARD_BUFFER]; extern volatile uint8_t KeyIndex_BufferUsed;