Mercurial > archived > louis > epitech > mq > rathaxes
annotate e1000_initialize_transmission.patch @ 83:27f0e70df342
Wip on the transmission, tx init done, and tx hooked from Ethernet send
author | Louis Opter <louis@lse.epitech.net> |
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date | Sun, 08 Jul 2012 10:00:25 +0200 |
parents | 71f76c0f235f |
children |
rev | line source |
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81
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Push the rx init, start a patch for the tx init
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1 # HG changeset patch |
83
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2 # Parent e2e48ad161482555c5e87550e76cf15ef7fdbd3e |
81
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3 rathaxes: initialize transmission on the e1000 sample: |
78f2f1918398
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4 |
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5 - This is documented in details in the sections 14.5 and 3.3 of the |
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6 Intel Gigabit Controller Software Developer manual. |
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7 |
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8 diff --git a/rathaxes/samples/e1000/e1000.blt b/rathaxes/samples/e1000/e1000.blt |
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9 --- a/rathaxes/samples/e1000/e1000.blt |
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10 +++ b/rathaxes/samples/e1000/e1000.blt |
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11 @@ -34,6 +34,59 @@ |
82 | 12 } |
13 | |
83
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14 /* |
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15 + * This is a generic tx descriptor for the e1000. When you use TCP |
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16 + * Segmentation Offload (TSO) the hardware actually uses two types of |
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17 + * tx descriptors in its tx ring: |
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18 + * - context descriptors: this descriptor doesn't actually point to data to |
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19 + * send but initialize the offloading engine for the data descriptor that |
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20 + * follow; |
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21 + * - data descriptors: this descriptor points to data from the skbuffs. |
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22 + */ |
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23 + template type e1000::TxDescriptor() |
82 | 24 + { |
83
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25 + chunk LKM::includes() |
82 | 26 + { |
83
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27 + static const ${e1000::TxDescriptor} force_rtx_e1000_tx_descriptor_decl; |
82 | 28 + } |
29 + | |
30 + chunk ::decl() | |
31 + { | |
32 + typedef struct rtx_e1000_tx_descriptor | |
33 + { | |
83
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34 + unsigned long int /* __le64 */ buff_addr; |
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35 + union |
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36 + { |
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37 + unsigned int /* __le32 */ data; |
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38 + struct |
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39 + { |
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40 + unsigned short /* __le16 */ length; |
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41 + unsigned char csum_offset; /* CSO */ |
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42 + unsigned char cmd; |
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43 + } fields; |
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44 + } lower; |
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45 + union |
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46 + { |
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47 + unsigned int /* __le32 */ data; |
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48 + struct |
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49 + { |
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50 + unsigned char status; |
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51 + unsigned char csum_start; /* CSS */ |
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52 + unsigned short /* __le16 */ special; |
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53 + } fields; |
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54 + } upper; |
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55 + } *rtx_e1000_tx_descriptor_p; |
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56 + } |
82 | 57 + |
83
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58 + chunk ::init() |
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59 + { |
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60 + } |
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61 + |
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62 + map |
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63 + { |
82 | 64 + } |
65 + } | |
66 + | |
83
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67 + /* |
82 | 68 * Ring of e1000::RxDescriptors and their corresponding skbuffs. |
69 * | |
83
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70 * - size: total size of the ring in bytes. |
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71 @@ -73,6 +126,43 @@ |
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72 } |
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73 } |
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74 |
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75 + /* |
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76 + * Ring of e1000::TxDescriptors, this is a bit similar to the Rx ring except |
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77 + * that we don't really have to manage the skbuffs themselves (they are |
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78 + * given to use by the kernel). |
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79 + * |
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80 + * - size: total size of the ring in bytes. |
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81 + * - base: address of the ring (we can't use the typedef here until we get |
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82 + * CNorm unstrict); |
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83 + * - dma_base: (physical) address of the ring where the device can access |
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84 + * the different descriptors. |
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85 + */ |
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86 + template type e1000::TxRing() |
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87 + { |
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88 + chunk LKM::includes() |
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89 + { |
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90 + static const ${e1000::TxRing} force_rtx_e1000_tx_ring_decl; |
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91 + } |
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92 + |
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93 + chunk ::decl() |
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94 + { |
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95 + struct rtx_e1000_tx_ring |
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96 + { |
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97 + unsigned int size; |
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98 + struct rtx_e1000_tx_descriptor *base; |
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99 + void* /* dma_addr_t */ dma_base; |
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100 + }; |
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101 + } |
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102 + |
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103 + chunk ::init() |
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104 + { |
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105 + } |
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106 + |
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107 + map |
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108 + { |
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109 + } |
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110 + } |
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111 + |
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112 template type e1000::Context() |
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113 { |
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114 chunk LKM::includes() |
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115 @@ -99,6 +189,7 @@ |
82 | 116 |
117 /* we can't use the Rathaxes type here (#8) */ | |
118 struct rtx_e1000_rx_ring rx_ring; | |
119 + struct rtx_e1000_tx_ring tx_ring; | |
120 } *rtx_e1000_ctx_p; | |
121 } | |
122 | |
83
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123 @@ -139,6 +230,7 @@ |
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124 E1000_FCT = 0x00030, /* Flow Control Type */ |
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125 E1000_RCTL = 0x00100, /* Receive Control */ |
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126 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value */ |
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127 + E1000_TCTL = 0x00400, /* Transmit Control */ |
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128 E1000_CRCERRS = 0x04000, /* CRC Error Count (base address of the statistic register spaces) */ |
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129 E1000_RAL = 0x05400, /* Receive Address Low */ |
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130 E1000_RAH = 0x05404, /* Receive Address High */ |
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131 @@ -148,6 +240,11 @@ |
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132 E1000_RDLEN = 0x02808, /* Receive Descriptor Length */ |
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133 E1000_RDH = 0x02810, /* Receive Descriptor Head */ |
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134 E1000_RDT = 0x02818, /* Receive Descriptor Tail */ |
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135 + E1000_TDBAL = 0x03800, /* Transmit Descriptor Base Address (Low 32 bits) */ |
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136 + E1000_TDBAH = 0x03804, /* Transmit Descriptor Base Address (High 33 bits) */ |
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137 + E1000_TDLEN = 0x03808, /* Transmit Descriptor Length */ |
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138 + E1000_TDH = 0x03810, /* Transmit Descriptor Head */ |
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139 + E1000_TDT = 0x03818, /* Transmit Descriptor Tail */ |
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140 }; |
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141 } |
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142 |
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143 @@ -226,6 +323,8 @@ |
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144 E1000_RCTL_BSIZE_4096 = (E1000_RCTL_BSEX | (1 << 16) | (1 << 17)), |
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145 E1000_RCTL_BSIZE_8192 = (E1000_RCTL_BSEX | (1 << 17)), |
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146 E1000_RCTL_BSIZE_16384 = (E1000_RCTL_BSEX | (1 << 16)), |
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147 + E1000_TCTL_EN = (1 << 1), /* Transmitter Enable */ |
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148 + E1000_TCTL_PSP = (1 << 3), /* Pad Short Packet */ |
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149 }; |
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150 } |
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151 |
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152 @@ -728,11 +827,64 @@ |
81
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153 } |
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154 |
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155 /* |
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156 + * Transmission initialization (section 14.5): |
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157 + * |
82 | 158 + * 1. Allocate the transmit descriptors ring and map it to make it |
81
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159 + * accessible by the device; |
82 | 160 + * 2. Write the start address of the ring in TDBAL/TDBAH and set |
161 + * TDLEN to the size of the ring; | |
162 + * 3. Set the TDH/TDT indexes to the beginning and end of the ring; | |
163 + * 4. Set TCTL.PSP to pad short packets and TCTL.EN to enable the | |
164 + * transmitter. | |
81
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165 + */ |
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166 + |
83
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167 + /* |
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168 + * XXX: at this point we must be careful to not fuck up with i, or |
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169 + * we are going go have surprises in `err_skbuffs_alloc`. Maybe it's |
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170 + * time to separate the rx and tx initialization in two functions. |
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171 + */ |
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172 + |
82 | 173 + /* 1. Allocate the tx ring */ |
83
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174 + hw_ctx->tx_ring.size = ${config.tx_ring_size} * sizeof(*hw_ctx->tx_ring.base); |
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175 + hw_ctx->tx_ring.size = ALIGN(hw_ctx->tx_ring.size, 4096); |
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176 + hw_ctx->tx_ring.base = dma_alloc_coherent( |
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177 + &${ctx}->pci_dev->dev, |
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178 + hw_ctx->tx_ring.size, |
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179 + (dma_addr_t *)&hw_ctx->tx_ring.dma_base, |
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180 + GFP_KERNEL); |
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181 + if (!hw_ctx->rx_ring.base) |
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182 + { |
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183 + ${Log::info("cannot allocate the descriptors for the tx ring")}; |
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184 + goto err_tx_ring_alloc; |
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185 + } |
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186 + |
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187 + { |
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188 + ${Log::info("setup_device: tx descriptors allocated")}; |
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189 + } |
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190 + |
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191 + /* 2. Save the emplacement and the size of the ring in TDBA/TDLEN */ |
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192 + rtx_e1000_register_write32(hw_ctx, E1000_TDBAL, (dma_addr_t)hw_ctx->tx_ring.dma_base & 0xffffffff); |
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193 + rtx_e1000_register_write32(hw_ctx, E1000_TDBAH, (dma_addr_t)hw_ctx->tx_ring.dma_base >> 32); |
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194 + rtx_e1000_register_write32(hw_ctx, E1000_TDLEN, hw_ctx->tx_ring.size); |
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195 + |
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196 + /* 3. Setup TDH/TDT to zero: the queue is empty */ |
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197 + rtx_e1000_register_write32(hw_ctx, E1000_TDH, 0); |
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198 + rtx_e1000_register_write32(hw_ctx, E1000_TDT, 0); |
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199 + |
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200 + /* 4. Set TCTL.PSP and enable the transmitter */ |
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201 + rtx_e1000_register_set32(hw_ctx, E1000_TCTL, E1000_TCTL_PSP|E1000_TCTL_PSP); |
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202 + |
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203 + { |
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204 + ${Log::info("transmit registers configured and transmitter enabled")}; |
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205 + } |
82 | 206 + |
81
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207 + /* |
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208 * XXX: We can't return here since we are not in a function but in |
78f2f1918398
Push the rx init, start a patch for the tx init
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209 * a chunk of code (injected in a function). |
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Push the rx init, start a patch for the tx init
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210 */ |
83
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211 goto ok; |
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212 |
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213 + err_tx_ring_alloc: |
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214 /* |
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215 * Likewise, always the same problem with error handling, we don't |
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216 * know where we are at in the "parent context": |
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217 @@ -788,6 +940,15 @@ |
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218 ${Log::info("free_rx_tx: rx ring free'ed")}; |
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219 } |
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220 |
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221 + /* |
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222 + * Free the tx ring: |
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223 + * - Free the descriptors array. |
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224 + */ |
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225 + dma_free_coherent(&${ctx}->pci_dev->dev, hw_ctx->tx_ring.size, |
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226 + hw_ctx->tx_ring.base, (dma_addr_t)hw_ctx->tx_ring.dma_base); |
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227 + { |
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228 + ${Log::info("free_rx_tx: tx ring free'ed")}; |
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229 + } |
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230 } |
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231 } |
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232 |
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233 diff --git a/rathaxes/samples/e1000/e1000.rti b/rathaxes/samples/e1000/e1000.rti |
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234 --- a/rathaxes/samples/e1000/e1000.rti |
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235 +++ b/rathaxes/samples/e1000/e1000.rti |
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236 @@ -2,7 +2,9 @@ |
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237 { |
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238 provided type e1000::Context; |
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239 provided type e1000::RxDescriptor; |
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240 + provided type e1000::TxDescriptor; |
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241 provided type e1000::RxRing; |
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242 + provided type e1000::TxRing; |
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243 |
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244 /* |
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245 * These two types should actually be registers definitions in the frontend: |
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246 diff --git a/rathaxes/samples/e1000/lkm.rtx b/rathaxes/samples/e1000/lkm.rtx |
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247 --- a/rathaxes/samples/e1000/lkm.rtx |
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248 +++ b/rathaxes/samples/e1000/lkm.rtx |
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249 @@ -73,6 +73,7 @@ |
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250 Ethernet::ifname = "rtx%d"; |
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251 |
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252 e1000::rx_ring_size = 256; /* Number of incoming packets we can buffer */ |
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253 + e1000::tx_ring_size = 256; /* Mumber of buffers we can have in the tx queue */ |
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254 /* |
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255 * The e1000 supports seven receive buffer sizes: 256, 512, 1024, 2048, |
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256 * 4096, 8192 and 16384 bytes: |