Mercurial > archived > louis > epitech > mq > rathaxes

comparison e1000_initialize_reception.patch @ 76:51bea596df7f

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Start a patch for the Rx init
author Louis Opter <louis@lse.epitech.net>
date Sun, 04 Mar 2012 15:27:34 +0100
parents
children 892b3bc7e43b
comparison
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75:c076a41a753c 76:51bea596df7f
1 # HG changeset patch
2 # Parent 40e5b7402e64e301b898fa4da1056a5348522fbb
3 rathaxes: initialize reception on the e1000 sample:
4
5 - This is documented in details in the sections 14.4 and 3.2 of the
6 Intel Gigabit Controller Software Developer manual;
7 - "Address filtering" is set up, address filters just tell the hardware
8 which packets they should accept (unicast/multicast/vlan/promisc), we
9 simply configure the hardware to accept packet for its own mac
10 address (receive address);
11 - It involves setting up a ring of receive descriptors (their format is
12 documented in section 3.2.3) and an internal data structure to keep
13 track of the ring;
14 - Each descriptor of the ring correspond to an skbuff (skbuff are
15 allocated individually).
16
17 diff --git a/rathaxes/samples/e1000/e1000.blt b/rathaxes/samples/e1000/e1000.blt
18 --- a/rathaxes/samples/e1000/e1000.blt
19 +++ b/rathaxes/samples/e1000/e1000.blt
20 @@ -36,6 +36,25 @@
21 }
22 }
23
24 + template type e1000::RingRx()
25 + {
26 + chunk LKM::includes()
27 + {
28 + }
29 +
30 + chunk ::decl()
31 + {
32 + }
33 +
34 + chunk ::init()
35 + {
36 + }
37 +
38 + map
39 + {
40 + }
41 + }
42 +
43 template type e1000::Register()
44 {
45 chunk LKM::includes()
46 @@ -64,6 +83,9 @@
47 E1000_FCT = 0x00030, /* Flow Control Type */
48 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value */
49 E1000_CRCERRS = 0x04000, /* CRC Error Count (base address of the statistic register spaces) */
50 + E1000_RAL = 0x05400, /* Receive Address Low */
51 + E1000_RAH = 0x05404, /* Receive Address High */
52 + E1000_MTA = 0x05200, /* Multicast Table Array */
53 };
54 }
55
56 @@ -132,7 +154,8 @@
57 E1000_INTR_RXDMT0 = 0x00000010, /* rx desc min. threshold (0) */
58 E1000_INTR_RXO = 0x00000040, /* rx overrun */
59 E1000_INTR_RXT0 = 0x00000080, /* rx timer intr (ring 0) */
60 - E1000_INTR_MDAC = 0x00000200 /* MDIO access complete */
61 + E1000_INTR_MDAC = 0x00000200, /* MDIO access complete */
62 + E1000_RAH_AV = (1 << 31), /* Set the MAC Address as Valid */
63 };
64 }
65
66 @@ -491,9 +514,32 @@
67 rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCAL, 0);
68 rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCT, 0);
69 rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCTTV, 0);
70 - int i = 0;
71 + int i = 0; /* CNorm workaround, the init part of for isn't generated */
72 for (i = 0; i != 64; ++i)
73 rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_CRCERRS + i * 4, 0);
74 +
75 + /*
76 + * Receive initialization
77 + *
78 + * - Program the receive address, in RAL/RAH;
79 + * - Initialize the Multicast Table Array;
80 + * - Program the interrupt mask register (done in
81 + * e1000::activate_device_interruption);
82 + *
83 + * (We should use uint{32,16}_t but CNorm doesn't know them yet)
84 + */
85 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_RAL,
86 + *(unsigned int *)(${ctx}->net_dev->dev_addr));
87 + /*
88 + * The 16 upper bits of RAH also store the AS bits (which should be
89 + * 0) and the AV bit (should be 1 to set the address as valid).
90 + */
91 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_RAH,
92 + *(unsigned short *)(&${ctx}->net_dev->dev_addr[4]));
93 + rtx_e1000_register_set32(&${ctx}->hw_ctx, E1000_RAH, E1000_RAH_AV);
94 + i = 0; /* CNorm workaround, the init part of for isn't generated */
95 + for (i = 0; i != 128; ++i)
96 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_MTA + i * 4, 0);
97 }
98 }
99
100 diff --git a/rathaxes/samples/e1000/e1000.rti b/rathaxes/samples/e1000/e1000.rti
101 --- a/rathaxes/samples/e1000/e1000.rti
102 +++ b/rathaxes/samples/e1000/e1000.rti
103 @@ -1,6 +1,8 @@
104 interface e1000 : Socket, Ethernet, PCI, LKM
105 {
106 provided type e1000::Context;
107 + provided type e1000::RingRx;
108 +
109 /*
110 * These two types should actually be registers definitions in the frontend:
111 */