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annotate e1000_initialize_reception.patch @ 76:51bea596df7f

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Start a patch for the Rx init
author Louis Opter <louis@lse.epitech.net>
date Sun, 04 Mar 2012 15:27:34 +0100
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children 892b3bc7e43b
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1 # HG changeset patch
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2 # Parent 40e5b7402e64e301b898fa4da1056a5348522fbb
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3 rathaxes: initialize reception on the e1000 sample:
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4
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5 - This is documented in details in the sections 14.4 and 3.2 of the
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6 Intel Gigabit Controller Software Developer manual;
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7 - "Address filtering" is set up, address filters just tell the hardware
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8 which packets they should accept (unicast/multicast/vlan/promisc), we
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9 simply configure the hardware to accept packet for its own mac
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10 address (receive address);
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11 - It involves setting up a ring of receive descriptors (their format is
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12 documented in section 3.2.3) and an internal data structure to keep
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13 track of the ring;
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14 - Each descriptor of the ring correspond to an skbuff (skbuff are
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15 allocated individually).
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16
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17 diff --git a/rathaxes/samples/e1000/e1000.blt b/rathaxes/samples/e1000/e1000.blt
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18 --- a/rathaxes/samples/e1000/e1000.blt
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19 +++ b/rathaxes/samples/e1000/e1000.blt
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20 @@ -36,6 +36,25 @@
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21 }
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22 }
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23
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24 + template type e1000::RingRx()
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25 + {
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26 + chunk LKM::includes()
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27 + {
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28 + }
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29 +
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30 + chunk ::decl()
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31 + {
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32 + }
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33 +
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34 + chunk ::init()
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35 + {
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36 + }
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37 +
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38 + map
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39 + {
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40 + }
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41 + }
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42 +
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43 template type e1000::Register()
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44 {
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45 chunk LKM::includes()
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46 @@ -64,6 +83,9 @@
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47 E1000_FCT = 0x00030, /* Flow Control Type */
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48 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value */
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49 E1000_CRCERRS = 0x04000, /* CRC Error Count (base address of the statistic register spaces) */
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50 + E1000_RAL = 0x05400, /* Receive Address Low */
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51 + E1000_RAH = 0x05404, /* Receive Address High */
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52 + E1000_MTA = 0x05200, /* Multicast Table Array */
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53 };
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54 }
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55
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56 @@ -132,7 +154,8 @@
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57 E1000_INTR_RXDMT0 = 0x00000010, /* rx desc min. threshold (0) */
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58 E1000_INTR_RXO = 0x00000040, /* rx overrun */
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59 E1000_INTR_RXT0 = 0x00000080, /* rx timer intr (ring 0) */
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60 - E1000_INTR_MDAC = 0x00000200 /* MDIO access complete */
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61 + E1000_INTR_MDAC = 0x00000200, /* MDIO access complete */
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62 + E1000_RAH_AV = (1 << 31), /* Set the MAC Address as Valid */
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63 };
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64 }
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65
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66 @@ -491,9 +514,32 @@
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67 rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCAL, 0);
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68 rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCT, 0);
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69 rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCTTV, 0);
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70 - int i = 0;
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71 + int i = 0; /* CNorm workaround, the init part of for isn't generated */
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72 for (i = 0; i != 64; ++i)
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73 rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_CRCERRS + i * 4, 0);
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74 +
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75 + /*
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76 + * Receive initialization
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77 + *
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78 + * - Program the receive address, in RAL/RAH;
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79 + * - Initialize the Multicast Table Array;
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80 + * - Program the interrupt mask register (done in
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81 + * e1000::activate_device_interruption);
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82 + *
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83 + * (We should use uint{32,16}_t but CNorm doesn't know them yet)
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84 + */
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85 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_RAL,
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86 + *(unsigned int *)(${ctx}->net_dev->dev_addr));
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87 + /*
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88 + * The 16 upper bits of RAH also store the AS bits (which should be
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89 + * 0) and the AV bit (should be 1 to set the address as valid).
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90 + */
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91 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_RAH,
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92 + *(unsigned short *)(&${ctx}->net_dev->dev_addr[4]));
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93 + rtx_e1000_register_set32(&${ctx}->hw_ctx, E1000_RAH, E1000_RAH_AV);
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94 + i = 0; /* CNorm workaround, the init part of for isn't generated */
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95 + for (i = 0; i != 128; ++i)
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96 + rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_MTA + i * 4, 0);
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97 }
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98 }
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99
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100 diff --git a/rathaxes/samples/e1000/e1000.rti b/rathaxes/samples/e1000/e1000.rti
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101 --- a/rathaxes/samples/e1000/e1000.rti
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102 +++ b/rathaxes/samples/e1000/e1000.rti
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103 @@ -1,6 +1,8 @@
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104 interface e1000 : Socket, Ethernet, PCI, LKM
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105 {
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106 provided type e1000::Context;
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107 + provided type e1000::RingRx;
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108 +
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109 /*
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110 * These two types should actually be registers definitions in the frontend:
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111 */