Mercurial > archived > louis > epitech > mq > rathaxes
annotate e1000_initialize_reception.patch @ 78:501bf9cf65dc
wip on e1000 add some fixes for the generation and check that it works on tip
author | Louis Opter <louis@lse.epitech.net> |
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date | Sun, 04 Mar 2012 18:55:20 +0100 |
parents | 892b3bc7e43b |
children | f07f6c6d6cd4 |
rev | line source |
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1 # HG changeset patch |
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2 # Parent 0d14f4eef173e65c3430393966e5f7e3bef7a8b2 |
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3 rathaxes: initialize reception on the e1000 sample: |
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4 |
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5 - This is documented in details in the sections 14.4 and 3.2 of the |
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6 Intel Gigabit Controller Software Developer manual; |
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7 - "Address filtering" is set up, address filters just tell the hardware |
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8 which packets they should accept (unicast/multicast/vlan/promisc), we |
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9 simply configure the hardware to accept packet for its own mac |
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10 address (receive address); |
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11 - It involves setting up a ring of receive descriptors (their format is |
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12 documented in section 3.2.3) and an internal data structure to keep |
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13 track of the ring; |
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14 - Each descriptor of the ring correspond to an skbuff (skbuff are |
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15 allocated individually). |
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16 |
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17 diff --git a/rathaxes/samples/e1000/e1000.blt b/rathaxes/samples/e1000/e1000.blt |
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18 --- a/rathaxes/samples/e1000/e1000.blt |
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19 +++ b/rathaxes/samples/e1000/e1000.blt |
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20 @@ -21,9 +21,12 @@ |
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21 */ |
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22 typedef struct rtx_e1000_ctx |
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23 { |
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24 - int bars; |
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25 - unsigned char /* __iomem */ *ioaddr; |
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26 - int irq; |
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27 + int bars; |
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28 + unsigned char /* __iomem */ *ioaddr; |
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29 + int irq; |
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30 + |
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31 + /* we can't use the Rathaxes type here (#8) */ |
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32 + struct rtx_e1000_rx_ring rx_ring; |
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33 } *rtx_e1000_ctx_p; |
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34 } |
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35 |
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36 @@ -36,6 +39,82 @@ |
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37 } |
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38 } |
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39 |
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40 + template type e1000::RxDescriptor() |
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41 + { |
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42 + chunk LKM::includes() |
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43 + { |
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44 + typedef int ${e1000::RxDescriptor}; |
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45 + |
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46 + #include <linux/types.h> |
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47 + } |
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48 + |
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49 + chunk ::decl() |
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50 + { |
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51 + typedef struct rtx_e1000_rx_descriptor |
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52 + { |
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53 + /* actual types are in comments */ |
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54 + unsigned long int /* __le64 */ buff_addr; |
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55 + unsigned short /* __le16 */ length; |
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56 + unsigned short /* __le16 */ csum; |
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57 + unsigned char status; |
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58 + unsigned char errors; |
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59 + unsigned short /* __le16 */ special; |
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60 + } *rtx_e1000_rx_descriptor_p; |
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61 + } |
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62 + |
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63 + chunk ::init() |
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64 + { |
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65 + } |
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66 + |
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67 + map |
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68 + { |
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69 + } |
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70 + } |
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71 + |
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72 + template type e1000::RxRing() |
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73 + { |
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74 + chunk LKM::includes() |
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75 + { |
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76 + typedef int ${e1000::RxRing}; |
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77 + } |
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78 + |
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79 + chunk ::decl() |
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80 + { |
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81 + /* |
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82 + * - size: total size of the ring in bytes. |
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83 + * - base: address of the ring; |
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84 + * - dma_base: (physical) address of the ring where the device |
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85 + * can access it; |
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86 + * - skbuffs: array of the skbuffs associated with |
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87 + * each descriptor; |
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88 + * - dma_skbuffs: (physical) address of each skbuff |
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89 + * where the device can write the received |
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90 + * packets; |
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91 + */ |
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92 + struct rtx_e1000_rx_ring |
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93 + { |
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94 + unsigned int size; |
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95 + /* |
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96 + * we can't use the typedef here because will not understand it |
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97 + * in __std__ mode |
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98 + */ |
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99 + struct rtx_e1000_rx_descriptor *base; |
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100 + void *dma_base; |
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101 + |
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102 + struct sk_buff *skbuffs[256 /* ${config.rx_ring_size} */]; |
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103 + void *dma_skbuffs[256 /* ${config.rx_ring_size} */]; |
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104 + }; |
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105 + } |
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106 + |
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107 + chunk ::init() |
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108 + { |
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109 + } |
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110 + |
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111 + map |
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112 + { |
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113 + } |
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114 + } |
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115 + |
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116 template type e1000::Register() |
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117 { |
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118 chunk LKM::includes() |
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119 @@ -64,6 +143,9 @@ |
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120 E1000_FCT = 0x00030, /* Flow Control Type */ |
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121 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value */ |
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122 E1000_CRCERRS = 0x04000, /* CRC Error Count (base address of the statistic register spaces) */ |
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123 + E1000_RAL = 0x05400, /* Receive Address Low */ |
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124 + E1000_RAH = 0x05404, /* Receive Address High */ |
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125 + E1000_MTA = 0x05200, /* Multicast Table Array */ |
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126 }; |
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127 } |
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128 |
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129 @@ -132,7 +214,8 @@ |
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130 E1000_INTR_RXDMT0 = 0x00000010, /* rx desc min. threshold (0) */ |
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131 E1000_INTR_RXO = 0x00000040, /* rx overrun */ |
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132 E1000_INTR_RXT0 = 0x00000080, /* rx timer intr (ring 0) */ |
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133 - E1000_INTR_MDAC = 0x00000200 /* MDIO access complete */ |
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134 + E1000_INTR_MDAC = 0x00000200, /* MDIO access complete */ |
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135 + E1000_RAH_AV = (1 << 31), /* Set the MAC Address as Valid */ |
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136 }; |
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137 } |
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138 |
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139 @@ -458,14 +541,24 @@ |
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140 chunk ::CALL() |
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141 { |
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142 /* |
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143 - * This is documented in the Intel Gigabit Ethernet Controller |
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144 - * Software Developper manual. |
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145 + * This part is documented in the Intel Gigabit Ethernet Controller |
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146 + * Software Developper manual. (You can find it in the doc/hardware |
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147 + * directory). |
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148 * |
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149 * Since this part is actually completely device specific it should |
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150 * not be written here. (but in the front-end). |
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151 */ |
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152 |
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153 /* |
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154 + * shortcut hw_ctx... maybe we should directly take an |
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155 + * e1000::Context? (but we would need to make it point back to |
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156 + * the struct net_device) |
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157 + */ |
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158 + typedef int ${e1000::Context}; |
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159 + ${e1000::Context} hw_ctx; |
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160 + hw_ctx = &${ctx}->hw_ctx; |
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161 + |
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162 + /* |
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163 * "General Configuration" (section 14.3): |
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164 * |
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165 * - CTRL.ASDE/CTRL.SLU: Let the PHY handle the speed detection & |
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166 @@ -478,22 +571,111 @@ |
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167 * - Finally, initialize all the statistic registers from |
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168 * E1000_CRCERRS to E1000_TSCTFC. |
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169 */ |
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170 - rtx_e1000_register_set32(&${ctx}->hw_ctx, E1000_CTRL, |
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171 + |
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172 + rtx_e1000_register_set32(hw_ctx, E1000_CTRL, |
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173 E1000_CMD_ASDE | |
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174 E1000_CMD_SLU); |
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175 - rtx_e1000_register_unset32(&${ctx}->hw_ctx, E1000_CTRL, |
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176 + rtx_e1000_register_unset32(hw_ctx, E1000_CTRL, |
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177 E1000_CMD_LRST | |
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178 E1000_CMD_FRCSPD | |
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179 E1000_CMD_PHY_RST | |
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180 E1000_CMD_ILOS | |
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181 E1000_CMD_VME); |
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182 - rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCAH, 0); |
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183 - rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCAL, 0); |
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184 - rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCT, 0); |
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185 - rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_FCTTV, 0); |
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186 - int i = 0; |
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187 + rtx_e1000_register_write32(hw_ctx, E1000_FCAH, 0); |
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188 + rtx_e1000_register_write32(hw_ctx, E1000_FCAL, 0); |
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189 + rtx_e1000_register_write32(hw_ctx, E1000_FCT, 0); |
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190 + rtx_e1000_register_write32(hw_ctx, E1000_FCTTV, 0); |
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191 + int i = 0; /* CNorm workaround, the init part of for isn't generated */ |
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192 for (i = 0; i != 64; ++i) |
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193 - rtx_e1000_register_write32(&${ctx}->hw_ctx, E1000_CRCERRS + i * 4, 0); |
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194 + rtx_e1000_register_write32(hw_ctx, E1000_CRCERRS + i * 4, 0); |
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195 + |
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196 + /* |
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197 + * Receive initialization |
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198 + * |
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199 + * - Program the receive address, in RAL/RAH; |
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200 + * - Initialize the Multicast Table Array; |
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201 + * - Program the interrupt mask register (done in |
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202 + * e1000::activate_device_interruption); |
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203 + * - Allocate the receive descriptor ring and map it to make it |
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204 + * accessible by the device. |
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205 + */ |
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206 + |
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207 + /* (We should use uint{32,16}_t but CNorm doesn't know them yet) */ |
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208 + rtx_e1000_register_write32(hw_ctx, E1000_RAL, |
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209 + *(unsigned int *)(${ctx}->net_dev->dev_addr)); |
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210 + /* |
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211 + * The 16 upper bits of RAH also store the AS bits (which should be |
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212 + * 0) and the AV bit (should be 1 to set the address as valid). |
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213 + */ |
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214 + rtx_e1000_register_write32(hw_ctx, E1000_RAH, |
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215 + *(unsigned short *)(&${ctx}->net_dev->dev_addr[4])); |
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216 + rtx_e1000_register_set32(hw_ctx, E1000_RAH, E1000_RAH_AV); |
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217 + |
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218 + i = 0; /* CNorm workaround, the init part of for isn't generated */ |
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219 + for (i = 0; i != 128; ++i) |
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220 + rtx_e1000_register_write32(hw_ctx, E1000_MTA + i * 4, 0); |
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221 + |
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222 + hw_ctx->rx_ring.size = ${config.rx_ring_size} * sizeof(*hw_ctx->rx_ring.base); |
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223 + hw_ctx->rx_ring.size = ALIGN(hw_ctx->rx_ring.size, 4096); |
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224 + hw_ctx->rx_ring.base = dma_alloc_coherent(&${ctx}->pci_dev->dev, |
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225 + hw_ctx->rx_ring.size, &hw_ctx->rx_ring.dma_base, GFP_KERNEL); |
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226 + if (!hw->ctx->rx_ring.base) |
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227 + { |
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228 + ${Log::info("cannot allocate the descriptors for the Rx ring")}; |
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229 + goto err_rx_ring_alloc; |
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Wip on the RX init in the e1000 sample
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230 + } |
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|
231 + |
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|
232 + i = 0; |
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Wip on the RX init in the e1000 sample
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233 + for (i = 0; i != ${config.rx_ring_size}; ++i) |
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234 + { |
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Wip on the RX init in the e1000 sample
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|
235 + hw_ctx->rx_ring.skbuffs[i] = netdev_allock_skb(${ctx}->net_device, |
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Wip on the RX init in the e1000 sample
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|
236 + ${config.rx_buffer_len}); |
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|
237 + if (!hw_ctx->rx_ring.skbuffs[i]) |
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|
238 + { |
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|
239 + ${Log::info("cannot allocate a skbuff for the Rx ring")}; |
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240 + goto err_skbuffs_alloc; |
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Wip on the RX init in the e1000 sample
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241 + } |
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242 + hw_ctx->rx_ring.dma_skbuffs[i] = dma_map_single(&${ctx}->pci_dev->dev, |
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|
243 + hw_ctx->rx_ring.skbuffs[i]->data, |
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|
244 + ${config.rx_buffer_len}, |
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|
245 + DMA_FROM_DEVICE); |
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|
246 + if (dma_mapping_error(&${ctx}->pci_dev->dev, |
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|
247 + hw_ctx->rx_ring.dma_skbuffs[i])) |
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248 + { |
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249 + ${Log::info("cannot dma-map a skbuff for the Rx ring")}; |
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250 + goto err_skbuffs_map; |
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|
251 + } |
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252 + hw_ctx->rx_ring.base[i].buff_addr = cpu_to_le64(hw_ctx->rx_ring.dma_skbuffs[i]); |
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253 + } |
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254 + |
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255 + /* |
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256 + * Always the same problem with error handling, we don't know where |
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257 + * we are at in the "parent context": |
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258 + */ |
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|
259 + |
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|
260 + err_skbuffs_alloc: |
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261 + while (i--) |
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262 + { |
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263 + dma_unmap_single(&${ctx}->pci_dev->dev, |
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|
264 + hw_ctx->rx_ring.dma_skbuffs[i], |
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|
265 + ${config.rx_buffer_len}, |
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266 + DMA_FROM_DEVICE); |
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|
267 + err_skbuffs_map: |
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268 + dev_kfree_skb(hw_ctx->rx_ring.skbuffs[i]); |
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269 + } |
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270 + |
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271 + dma_free_coherent(&${ctx}->pci_dev->dev, hw_ctx->rx_ring.size, |
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272 + hw_ctx->rx_ring.base, hw_ctx->rx_ring.dma_base); |
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273 + err_rx_ring_alloc: |
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274 + return -ENOMEM; |
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275 + } |
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276 + } |
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277 + |
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278 + template sequence e1000::free_rx_tx(Ethernet::Device ctx) |
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279 + { |
78
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280 + chunk ::CALL() |
77
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281 + { |
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|
282 + |
76
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|
283 } |
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|
284 } |
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Start a patch for the Rx init
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|
285 |
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286 diff --git a/rathaxes/samples/e1000/e1000.rti b/rathaxes/samples/e1000/e1000.rti |
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287 --- a/rathaxes/samples/e1000/e1000.rti |
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288 +++ b/rathaxes/samples/e1000/e1000.rti |
77
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289 @@ -1,6 +1,9 @@ |
76
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290 interface e1000 : Socket, Ethernet, PCI, LKM |
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Start a patch for the Rx init
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|
291 { |
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292 provided type e1000::Context; |
77
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293 + provided type e1000::RxDescriptor; |
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Wip on the RX init in the e1000 sample
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|
294 + provided type e1000::RxRing; |
76
51bea596df7f
Start a patch for the Rx init
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|
295 + |
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Start a patch for the Rx init
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|
296 /* |
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297 * These two types should actually be registers definitions in the frontend: |
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Start a patch for the Rx init
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|
298 */ |
78
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299 @@ -55,6 +58,11 @@ |
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|
300 provided chunk ::CALL(); |
77
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|
301 } |
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|
302 |
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|
303 + provided sequence e1000::free_rx_tx(Ethernet::Device dev) |
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|
304 + { |
78
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wip on e1000 add some fixes for the generation and check that it works on tip
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|
305 + provided chunk ::CALL(); |
77
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|
306 + } |
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|
307 + |
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|
308 provided sequence e1000::handle_interrupt(Ethernet::Device) |
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|
309 { |
78
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|
310 provided chunk ::CALL(); |
77
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311 diff --git a/rathaxes/samples/e1000/ethernet.blt b/rathaxes/samples/e1000/ethernet.blt |
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|
312 --- a/rathaxes/samples/e1000/ethernet.blt |
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|
313 +++ b/rathaxes/samples/e1000/ethernet.blt |
78
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|
314 @@ -105,7 +105,7 @@ |
77
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|
315 { |
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changeset
|
316 static int rtx_ethernet_close(struct net_device *dev) |
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|
317 { |
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|
318 - struct rtx_ethernet_dev* rtx_ether_dev = netdev_priv(dev); |
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|
319 + struct rtx_ethernet_dev* rtx_ether_dev = netdev_priv(dev); |
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|
320 struct rtx_e1000_ctx* ctx = &rtx_ether_dev->hw_ctx; |
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|
321 |
78
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|
322 ${cast local.rtx_ether_dev as Ethernet::Device}; |
77
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|
323 diff --git a/rathaxes/samples/e1000/lkm.rtx b/rathaxes/samples/e1000/lkm.rtx |
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|
324 --- a/rathaxes/samples/e1000/lkm.rtx |
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|
325 +++ b/rathaxes/samples/e1000/lkm.rtx |
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|
326 @@ -24,7 +24,17 @@ |
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|
327 Ethernet::close(Ethernet::Device dev) |
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|
328 { |
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|
329 Log::info("closing the device"); |
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|
330 + |
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|
331 + /* |
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|
332 + * Note: some calls to release resources must be done when IRQs are |
892b3bc7e43b
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|
333 + * enabled (dma_free_coherent() for example). So we have to cleanup our |
892b3bc7e43b
Wip on the RX init in the e1000 sample
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|
334 + * stuff before free_interrupt_handler(). |
892b3bc7e43b
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|
335 + */ |
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|
336 + e1000::free_rx_tx(dev); |
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|
337 + Log::info("free'ed up skbuffs"); |
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|
338 + |
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changeset
|
339 e1000::free_interrupt_handler(dev); |
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340 + Log::info("interrupt handler free'ed"); |
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341 } |
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342 |
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343 Ethernet::interrupt_handler(Ethernet::Device dev) |
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344 @@ -61,4 +71,11 @@ |
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345 PCI::set_master = true; |
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346 |
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347 Ethernet::ifname = "rtx%d"; |
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348 + |
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349 + e1000::rx_ring_size = 256; /* Number of incoming packets we can buffer */ |
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350 + /* |
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351 + * The e1000 supports seven receive buffer sizes: 256, 512, 1024, 2048, |
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352 + * 4096, 8192 and 16384 bytes: |
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353 + */ |
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354 + e1000::rx_buffer_len = 2048; |
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355 } |