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Merge branch 'master' of https://github.com/smasher816/controller into smasher816-master
author Jacob Alexander <haata@kiibohd.com>
date Sun, 15 Mar 2015 18:27:35 -0700
parents ecd2ae35d25c ab4515606277
children 9e31d92caf12
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307:ecd2ae35d25c 311:48e69c499057
59 59
60 60
61 // ----- Registers ----- 61 // ----- Registers -----
62 62
63 // chapter 11: Port control and interrupts (PORT) 63 // chapter 11: Port control and interrupts (PORT)
64 #define PORT_PCR_ISF (uint32_t)0x01000000 // Interrupt Status Flag 64 #define PORT_PCR_ISF (uint32_t)0x01000000 // Interrupt Status Flag
65 #define PORT_PCR_IRQC(n) (uint32_t)(((n) & 15) << 16) // Interrupt Configuration 65 #define PORT_PCR_IRQC(n) (uint32_t)(((n) & 15) << 16) // Interrupt Configuration
66 #define PORT_PCR_IRQC_MASK (uint32_t)0x000F0000 66 #define PORT_PCR_IRQC_MASK (uint32_t)0x000F0000
67 #define PORT_PCR_LK (uint32_t)0x00008000 // Lock Register 67 #define PORT_PCR_LK (uint32_t)0x00008000 // Lock Register
68 #define PORT_PCR_MUX(n) (uint32_t)(((n) & 7) << 8) // Pin Mux Control 68 #define PORT_PCR_MUX(n) (uint32_t)(((n) & 7) << 8) // Pin Mux Control
69 #define PORT_PCR_MUX_MASK (uint32_t)0x00000700 69 #define PORT_PCR_MUX_MASK (uint32_t)0x00000700
70 #define PORT_PCR_DSE (uint32_t)0x00000040 // Drive Strength Enable 70 #define PORT_PCR_DSE (uint32_t)0x00000040 // Drive Strength Enable
71 #define PORT_PCR_ODE (uint32_t)0x00000020 // Open Drain Enable 71 #define PORT_PCR_ODE (uint32_t)0x00000020 // Open Drain Enable
72 #define PORT_PCR_PFE (uint32_t)0x00000010 // Passive Filter Enable 72 #define PORT_PCR_PFE (uint32_t)0x00000010 // Passive Filter Enable
73 #define PORT_PCR_SRE (uint32_t)0x00000004 // Slew Rate Enable 73 #define PORT_PCR_SRE (uint32_t)0x00000004 // Slew Rate Enable
74 #define PORT_PCR_PE (uint32_t)0x00000002 // Pull Enable 74 #define PORT_PCR_PE (uint32_t)0x00000002 // Pull Enable
75 #define PORT_PCR_PS (uint32_t)0x00000001 // Pull Select 75 #define PORT_PCR_PS (uint32_t)0x00000001 // Pull Select
76 #define PORTA_PCR0 *(volatile uint32_t *)0x40049000 // Pin Control Register n 76 #define PORTA_PCR0 *(volatile uint32_t *)0x40049000 // Pin Control Register n
77 #define PORTA_PCR1 *(volatile uint32_t *)0x40049004 // Pin Control Register n 77 #define PORTA_PCR1 *(volatile uint32_t *)0x40049004 // Pin Control Register n
78 #define PORTA_PCR2 *(volatile uint32_t *)0x40049008 // Pin Control Register n 78 #define PORTA_PCR2 *(volatile uint32_t *)0x40049008 // Pin Control Register n
79 #define PORTA_PCR3 *(volatile uint32_t *)0x4004900C // Pin Control Register n 79 #define PORTA_PCR3 *(volatile uint32_t *)0x4004900C // Pin Control Register n
80 #define PORTA_PCR4 *(volatile uint32_t *)0x40049010 // Pin Control Register n 80 #define PORTA_PCR4 *(volatile uint32_t *)0x40049010 // Pin Control Register n
251 251
252 // Chapter 12: System Integration Module (SIM) 252 // Chapter 12: System Integration Module (SIM)
253 #define SIM_SOPT1 *(volatile uint32_t *)0x40047000 // System Options Register 1 253 #define SIM_SOPT1 *(volatile uint32_t *)0x40047000 // System Options Register 1
254 #define SIM_SOPT1CFG *(volatile uint32_t *)0x40047004 // SOPT1 Configuration Register 254 #define SIM_SOPT1CFG *(volatile uint32_t *)0x40047004 // SOPT1 Configuration Register
255 #define SIM_SOPT2 *(volatile uint32_t *)0x40048004 // System Options Register 2 255 #define SIM_SOPT2 *(volatile uint32_t *)0x40048004 // System Options Register 2
256 #define SIM_SOPT2_USBSRC (uint32_t)0x00040000 // 0=USB_CLKIN, 1=FFL/PLL 256 #define SIM_SOPT2_USBSRC (uint32_t)0x00040000 // 0=USB_CLKIN, 1=FFL/PLL
257 #define SIM_SOPT2_PLLFLLSEL (uint32_t)0x00010000 // 0=FLL, 1=PLL 257 #define SIM_SOPT2_PLLFLLSEL (uint32_t)0x00010000 // 0=FLL, 1=PLL
258 #define SIM_SOPT2_TRACECLKSEL (uint32_t)0x00001000 // 0=MCGOUTCLK, 1=CPU 258 #define SIM_SOPT2_TRACECLKSEL (uint32_t)0x00001000 // 0=MCGOUTCLK, 1=CPU
259 #define SIM_SOPT2_PTD7PAD (uint32_t)0x00000800 // 0=normal, 1=double drive PTD7 259 #define SIM_SOPT2_PTD7PAD (uint32_t)0x00000800 // 0=normal, 1=double drive PTD7
260 #define SIM_SOPT2_CLKOUTSEL(n) (uint32_t)(((n) & 7) << 5) // Selects the clock to output on the CLKOUT pin. 260 #define SIM_SOPT2_CLKOUTSEL(n) (uint32_t)(((n) & 7) << 5) // Selects the clock to output on the CLKOUT pin.
261 #define SIM_SOPT2_RTCCLKOUTSEL (uint32_t)0x00000010 // RTC clock out select 261 #define SIM_SOPT2_RTCCLKOUTSEL (uint32_t)0x00000010 // RTC clock out select
262 #define SIM_SOPT4 *(volatile uint32_t *)0x4004800C // System Options Register 4 262 #define SIM_SOPT4 *(volatile uint32_t *)0x4004800C // System Options Register 4
263 #define SIM_SOPT5 *(volatile uint32_t *)0x40048010 // System Options Register 5 263 #define SIM_SOPT5 *(volatile uint32_t *)0x40048010 // System Options Register 5
264 #define SIM_SOPT7 *(volatile uint32_t *)0x40048018 // System Options Register 7 264 #define SIM_SOPT7 *(volatile uint32_t *)0x40048018 // System Options Register 7
265 #define SIM_SDID *(const uint32_t *)0x40048024 // System Device Identification Register 265 #define SIM_SDID *(const uint32_t *)0x40048024 // System Device Identification Register
266 #define SIM_SCGC2 *(volatile uint32_t *)0x4004802C // System Clock Gating Control Register 2 266 #define SIM_SCGC2 *(volatile uint32_t *)0x4004802C // System Clock Gating Control Register 2
267 #define SIM_SCGC2_DAC0 (uint32_t)0x00001000 // DAC0 Clock Gate Control 267 #define SIM_SCGC2_DAC0 (uint32_t)0x00001000 // DAC0 Clock Gate Control
268 #define SIM_SCGC3 *(volatile uint32_t *)0x40048030 // System Clock Gating Control Register 3 268 #define SIM_SCGC3 *(volatile uint32_t *)0x40048030 // System Clock Gating Control Register 3
269 #define SIM_SCGC3_ADC1 (uint32_t)0x08000000 // ADC1 Clock Gate Control 269 #define SIM_SCGC3_ADC1 (uint32_t)0x08000000 // ADC1 Clock Gate Control
270 #define SIM_SCGC3_FTM2 (uint32_t)0x01000000 // FTM2 Clock Gate Control 270 #define SIM_SCGC3_FTM2 (uint32_t)0x01000000 // FTM2 Clock Gate Control
271 #define SIM_SCGC4 *(volatile uint32_t *)0x40048034 // System Clock Gating Control Register 4 271 #define SIM_SCGC4 *(volatile uint32_t *)0x40048034 // System Clock Gating Control Register 4
272 #define SIM_SCGC4_VREF (uint32_t)0x00100000 // VREF Clock Gate Control 272 #define SIM_SCGC4_VREF (uint32_t)0x00100000 // VREF Clock Gate Control
273 #define SIM_SCGC4_CMP (uint32_t)0x00080000 // Comparator Clock Gate Control 273 #define SIM_SCGC4_CMP (uint32_t)0x00080000 // Comparator Clock Gate Control
274 #define SIM_SCGC4_USBOTG (uint32_t)0x00040000 // USB Clock Gate Control 274 #define SIM_SCGC4_USBOTG (uint32_t)0x00040000 // USB Clock Gate Control
275 #define SIM_SCGC4_UART2 (uint32_t)0x00001000 // UART2 Clock Gate Control 275 #define SIM_SCGC4_UART2 (uint32_t)0x00001000 // UART2 Clock Gate Control
276 #define SIM_SCGC4_UART1 (uint32_t)0x00000800 // UART1 Clock Gate Control 276 #define SIM_SCGC4_UART1 (uint32_t)0x00000800 // UART1 Clock Gate Control
277 #define SIM_SCGC4_UART0 (uint32_t)0x00000400 // UART0 Clock Gate Control 277 #define SIM_SCGC4_UART0 (uint32_t)0x00000400 // UART0 Clock Gate Control
278 #define SIM_SCGC4_I2C1 (uint32_t)0x00000080 // I2C1 Clock Gate Control 278 #define SIM_SCGC4_I2C1 (uint32_t)0x00000080 // I2C1 Clock Gate Control
279 #define SIM_SCGC4_I2C0 (uint32_t)0x00000040 // I2C0 Clock Gate Control 279 #define SIM_SCGC4_I2C0 (uint32_t)0x00000040 // I2C0 Clock Gate Control
280 #define SIM_SCGC4_CMT (uint32_t)0x00000004 // CMT Clock Gate Control 280 #define SIM_SCGC4_CMT (uint32_t)0x00000004 // CMT Clock Gate Control
281 #define SIM_SCGC4_EWM (uint32_t)0x00000002 // EWM Clock Gate Control 281 #define SIM_SCGC4_EWM (uint32_t)0x00000002 // EWM Clock Gate Control
282 #define SIM_SCGC5 *(volatile uint32_t *)0x40048038 // System Clock Gating Control Register 5 282 #define SIM_SCGC5 *(volatile uint32_t *)0x40048038 // System Clock Gating Control Register 5
283 #define SIM_SCGC5_PORTE (uint32_t)0x00002000 // Port E Clock Gate Control 283 #define SIM_SCGC5_PORTE (uint32_t)0x00002000 // Port E Clock Gate Control
284 #define SIM_SCGC5_PORTD (uint32_t)0x00001000 // Port D Clock Gate Control 284 #define SIM_SCGC5_PORTD (uint32_t)0x00001000 // Port D Clock Gate Control
285 #define SIM_SCGC5_PORTC (uint32_t)0x00000800 // Port C Clock Gate Control 285 #define SIM_SCGC5_PORTC (uint32_t)0x00000800 // Port C Clock Gate Control
286 #define SIM_SCGC5_PORTB (uint32_t)0x00000400 // Port B Clock Gate Control 286 #define SIM_SCGC5_PORTB (uint32_t)0x00000400 // Port B Clock Gate Control
287 #define SIM_SCGC5_PORTA (uint32_t)0x00000200 // Port A Clock Gate Control 287 #define SIM_SCGC5_PORTA (uint32_t)0x00000200 // Port A Clock Gate Control
288 #define SIM_SCGC5_TSI (uint32_t)0x00000020 // Touch Sense Input TSI Clock Gate Control 288 #define SIM_SCGC5_TSI (uint32_t)0x00000020 // Touch Sense Input TSI Clock Gate Control
289 #define SIM_SCGC5_LPTIMER (uint32_t)0x00000001 // Low Power Timer Access Control 289 #define SIM_SCGC5_LPTIMER (uint32_t)0x00000001 // Low Power Timer Access Control
290 #define SIM_SCGC6 *(volatile uint32_t *)0x4004803C // System Clock Gating Control Register 6 290 #define SIM_SCGC6 *(volatile uint32_t *)0x4004803C // System Clock Gating Control Register 6
291 #define SIM_SCGC6_RTC (uint32_t)0x20000000 // RTC Access 291 #define SIM_SCGC6_RTC (uint32_t)0x20000000 // RTC Access
292 #define SIM_SCGC6_ADC0 (uint32_t)0x08000000 // ADC0 Clock Gate Control 292 #define SIM_SCGC6_ADC0 (uint32_t)0x08000000 // ADC0 Clock Gate Control
293 #define SIM_SCGC6_FTM1 (uint32_t)0x02000000 // FTM1 Clock Gate Control 293 #define SIM_SCGC6_FTM1 (uint32_t)0x02000000 // FTM1 Clock Gate Control
294 #define SIM_SCGC6_FTM0 (uint32_t)0x01000000 // FTM0 Clock Gate Control 294 #define SIM_SCGC6_FTM0 (uint32_t)0x01000000 // FTM0 Clock Gate Control
295 #define SIM_SCGC6_PIT (uint32_t)0x00800000 // PIT Clock Gate Control 295 #define SIM_SCGC6_PIT (uint32_t)0x00800000 // PIT Clock Gate Control
296 #define SIM_SCGC6_PDB (uint32_t)0x00400000 // PDB Clock Gate Control 296 #define SIM_SCGC6_PDB (uint32_t)0x00400000 // PDB Clock Gate Control
297 #define SIM_SCGC6_USBDCD (uint32_t)0x00200000 // USB DCD Clock Gate Control 297 #define SIM_SCGC6_USBDCD (uint32_t)0x00200000 // USB DCD Clock Gate Control
298 #define SIM_SCGC6_CRC (uint32_t)0x00040000 // CRC Clock Gate Control 298 #define SIM_SCGC6_CRC (uint32_t)0x00040000 // CRC Clock Gate Control
299 #define SIM_SCGC6_I2S (uint32_t)0x00008000 // I2S Clock Gate Control 299 #define SIM_SCGC6_I2S (uint32_t)0x00008000 // I2S Clock Gate Control
300 #define SIM_SCGC6_SPI1 (uint32_t)0x00002000 // SPI1 Clock Gate Control 300 #define SIM_SCGC6_SPI1 (uint32_t)0x00002000 // SPI1 Clock Gate Control
301 #define SIM_SCGC6_SPI0 (uint32_t)0x00001000 // SPI0 Clock Gate Control 301 #define SIM_SCGC6_SPI0 (uint32_t)0x00001000 // SPI0 Clock Gate Control
302 #define SIM_SCGC6_FLEXCAN0 (uint32_t)0x00000010 // FlexCAN0 Clock Gate Control 302 #define SIM_SCGC6_FLEXCAN0 (uint32_t)0x00000010 // FlexCAN0 Clock Gate Control
303 #define SIM_SCGC6_DMAMUX (uint32_t)0x00000002 // DMA Mux Clock Gate Control 303 #define SIM_SCGC6_DMAMUX (uint32_t)0x00000002 // DMA Mux Clock Gate Control
304 #define SIM_SCGC6_FTFL (uint32_t)0x00000001 // Flash Memory Clock Gate Control 304 #define SIM_SCGC6_FTFL (uint32_t)0x00000001 // Flash Memory Clock Gate Control
305 #define SIM_SCGC7 *(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7 305 #define SIM_SCGC7 *(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7
306 #define SIM_SCGC7_DMA (uint32_t)0x00000002 // DMA Clock Gate Control 306 #define SIM_SCGC7_DMA (uint32_t)0x00000002 // DMA Clock Gate Control
307 #define SIM_CLKDIV1 *(volatile uint32_t *)0x40048044 // System Clock Divider Register 1 307 #define SIM_CLKDIV1 *(volatile uint32_t *)0x40048044 // System Clock Divider Register 1
308 #define SIM_CLKDIV1_OUTDIV1(n) (uint32_t)(((n) & 0x0F) << 28) // divide value for the core/system clock 308 #define SIM_CLKDIV1_OUTDIV1(n) (uint32_t)(((n) & 0x0F) << 28) // divide value for the core/system clock
309 #define SIM_CLKDIV1_OUTDIV2(n) (uint32_t)(((n) & 0x0F) << 24) // divide value for the peripheral clock 309 #define SIM_CLKDIV1_OUTDIV2(n) (uint32_t)(((n) & 0x0F) << 24) // divide value for the peripheral clock
310 #define SIM_CLKDIV1_OUTDIV4(n) (uint32_t)(((n) & 0x0F) << 16) // divide value for the flash clock 310 #define SIM_CLKDIV1_OUTDIV4(n) (uint32_t)(((n) & 0x0F) << 16) // divide value for the flash clock
311 #define SIM_CLKDIV2 *(volatile uint32_t *)0x40048048 // System Clock Divider Register 2 311 #define SIM_CLKDIV2 *(volatile uint32_t *)0x40048048 // System Clock Divider Register 2
312 #define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) 312 #define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1)
313 #define SIM_CLKDIV2_USBFRAC (uint32_t)0x01 313 #define SIM_CLKDIV2_USBFRAC (uint32_t)0x01
314 #define SIM_FCFG1 *(const uint32_t *)0x4004804C // Flash Configuration Register 1 314 #define SIM_FCFG1 *(const uint32_t *)0x4004804C // Flash Configuration Register 1
315 #define SIM_FCFG2 *(const uint32_t *)0x40048050 // Flash Configuration Register 2 315 #define SIM_FCFG2 *(const uint32_t *)0x40048050 // Flash Configuration Register 2
316 #define SIM_UIDH *(const uint32_t *)0x40048054 // Unique Identification Register High 316 #define SIM_UIDH *(const uint32_t *)0x40048054 // Unique Identification Register High
317 #define SIM_UIDMH *(const uint32_t *)0x40048058 // Unique Identification Register Mid-High 317 #define SIM_UIDMH *(const uint32_t *)0x40048058 // Unique Identification Register Mid-High
318 #define SIM_UIDML *(const uint32_t *)0x4004805C // Unique Identification Register Mid Low 318 #define SIM_UIDML *(const uint32_t *)0x4004805C // Unique Identification Register Mid Low
324 #define RCM_RPFC *(volatile uint8_t *)0x4007F004 // Reset Pin Filter Control Register 324 #define RCM_RPFC *(volatile uint8_t *)0x4007F004 // Reset Pin Filter Control Register
325 #define RCM_RPFW *(volatile uint8_t *)0x4007F005 // Reset Pin Filter Width Register 325 #define RCM_RPFW *(volatile uint8_t *)0x4007F005 // Reset Pin Filter Width Register
326 #define RCM_MR *(volatile uint8_t *)0x4007F007 // Mode Register 326 #define RCM_MR *(volatile uint8_t *)0x4007F007 // Mode Register
327 327
328 // Chapter 14: System Mode Controller 328 // Chapter 14: System Mode Controller
329 #define SMC_PMPROT *(volatile uint8_t *)0x4007E000 // Power Mode Protection Register 329 #define SMC_PMPROT *(volatile uint8_t *)0x4007E000 // Power Mode Protection Register
330 #define SMC_PMPROT_AVLP (uint8_t)0x20 // Allow very low power modes 330 #define SMC_PMPROT_AVLP (uint8_t)0x20 // Allow very low power modes
331 #define SMC_PMPROT_ALLS (uint8_t)0x08 // Allow low leakage stop mode 331 #define SMC_PMPROT_ALLS (uint8_t)0x08 // Allow low leakage stop mode
332 #define SMC_PMPROT_AVLLS (uint8_t)0x02 // Allow very low leakage stop mode 332 #define SMC_PMPROT_AVLLS (uint8_t)0x02 // Allow very low leakage stop mode
333 #define SMC_PMCTRL *(volatile uint8_t *)0x4007E001 // Power Mode Control Register 333 #define SMC_PMCTRL *(volatile uint8_t *)0x4007E001 // Power Mode Control Register
334 #define SMC_PMCTRL_LPWUI (uint8_t)0x80 // Low Power Wake Up on Interrupt 334 #define SMC_PMCTRL_LPWUI (uint8_t)0x80 // Low Power Wake Up on Interrupt
335 #define SMC_PMCTRL_RUNM(n) (uint8_t)(((n) & 0x03) << 5) // Run Mode Control 335 #define SMC_PMCTRL_RUNM(n) (uint8_t)(((n) & 0x03) << 5) // Run Mode Control
336 #define SMC_PMCTRL_STOPA (uint8_t)0x08 // Stop Aborted 336 #define SMC_PMCTRL_STOPA (uint8_t)0x08 // Stop Aborted
337 #define SMC_PMCTRL_STOPM(n) (uint8_t)((n) & 0x07) // Stop Mode Control 337 #define SMC_PMCTRL_STOPM(n) (uint8_t)((n) & 0x07) // Stop Mode Control
338 #define SMC_VLLSCTRL *(volatile uint8_t *)0x4007E002 // VLLS Control Register 338 #define SMC_VLLSCTRL *(volatile uint8_t *)0x4007E002 // VLLS Control Register
339 #define SMC_VLLSCTRL_PORPO (uint8_t)0x20 // POR Power Option 339 #define SMC_VLLSCTRL_PORPO (uint8_t)0x20 // POR Power Option
340 #define SMC_VLLSCTRL_VLLSM(n) (uint8_t)((n) & 0x07) // VLLS Mode Control 340 #define SMC_VLLSCTRL_VLLSM(n) (uint8_t)((n) & 0x07) // VLLS Mode Control
341 #define SMC_PMSTAT *(volatile uint8_t *)0x4007E003 // Power Mode Status Register 341 #define SMC_PMSTAT *(volatile uint8_t *)0x4007E003 // Power Mode Status Register
342 #define SMC_PMSTAT_RUN (uint8_t)0x01 // Current power mode is RUN 342 #define SMC_PMSTAT_RUN (uint8_t)0x01 // Current power mode is RUN
343 #define SMC_PMSTAT_STOP (uint8_t)0x02 // Current power mode is STOP 343 #define SMC_PMSTAT_STOP (uint8_t)0x02 // Current power mode is STOP
344 #define SMC_PMSTAT_VLPR (uint8_t)0x04 // Current power mode is VLPR 344 #define SMC_PMSTAT_VLPR (uint8_t)0x04 // Current power mode is VLPR
345 #define SMC_PMSTAT_VLPW (uint8_t)0x08 // Current power mode is VLPW 345 #define SMC_PMSTAT_VLPW (uint8_t)0x08 // Current power mode is VLPW
346 #define SMC_PMSTAT_VLPS (uint8_t)0x10 // Current power mode is VLPS 346 #define SMC_PMSTAT_VLPS (uint8_t)0x10 // Current power mode is VLPS
347 #define SMC_PMSTAT_LLS (uint8_t)0x20 // Current power mode is LLS 347 #define SMC_PMSTAT_LLS (uint8_t)0x20 // Current power mode is LLS
348 #define SMC_PMSTAT_VLLS (uint8_t)0x40 // Current power mode is VLLS 348 #define SMC_PMSTAT_VLLS (uint8_t)0x40 // Current power mode is VLLS
349 349
350 // Chapter 15: Power Management Controller 350 // Chapter 15: Power Management Controller
351 #define PMC_LVDSC1 *(volatile uint8_t *)0x4007D000 // Low Voltage Detect Status And Control 1 register 351 #define PMC_LVDSC1 *(volatile uint8_t *)0x4007D000 // Low Voltage Detect Status And Control 1 register
352 #define PMC_LVDSC1_LVDF (uint8_t)0x80 // Low-Voltage Detect Flag 352 #define PMC_LVDSC1_LVDF (uint8_t)0x80 // Low-Voltage Detect Flag
353 #define PMC_LVDSC1_LVDACK (uint8_t)0x40 // Low-Voltage Detect Acknowledge 353 #define PMC_LVDSC1_LVDACK (uint8_t)0x40 // Low-Voltage Detect Acknowledge
354 #define PMC_LVDSC1_LVDIE (uint8_t)0x20 // Low-Voltage Detect Interrupt Enable 354 #define PMC_LVDSC1_LVDIE (uint8_t)0x20 // Low-Voltage Detect Interrupt Enable
355 #define PMC_LVDSC1_LVDRE (uint8_t)0x10 // Low-Voltage Detect Reset Enable 355 #define PMC_LVDSC1_LVDRE (uint8_t)0x10 // Low-Voltage Detect Reset Enable
356 #define PMC_LVDSC1_LVDV(n) (uint8_t)((n) & 0x03) // Low-Voltage Detect Voltage Select 356 #define PMC_LVDSC1_LVDV(n) (uint8_t)((n) & 0x03) // Low-Voltage Detect Voltage Select
357 #define PMC_LVDSC2 *(volatile uint8_t *)0x4007D001 // Low Voltage Detect Status And Control 2 register 357 #define PMC_LVDSC2 *(volatile uint8_t *)0x4007D001 // Low Voltage Detect Status And Control 2 register
358 #define PMC_LVDSC2_LVWF (uint8_t)0x80 // Low-Voltage Warning Flag 358 #define PMC_LVDSC2_LVWF (uint8_t)0x80 // Low-Voltage Warning Flag
359 #define PMC_LVDSC2_LVWACK (uint8_t)0x40 // Low-Voltage Warning Acknowledge 359 #define PMC_LVDSC2_LVWACK (uint8_t)0x40 // Low-Voltage Warning Acknowledge
360 #define PMC_LVDSC2_LVWIE (uint8_t)0x20 // Low-Voltage Warning Interrupt Enable 360 #define PMC_LVDSC2_LVWIE (uint8_t)0x20 // Low-Voltage Warning Interrupt Enable
361 #define PMC_LVDSC2_LVWV(n) (uint8_t)((n) & 0x03) // Low-Voltage Warning Voltage Select 361 #define PMC_LVDSC2_LVWV(n) (uint8_t)((n) & 0x03) // Low-Voltage Warning Voltage Select
362 #define PMC_REGSC *(volatile uint8_t *)0x4007D002 // Regulator Status And Control register 362 #define PMC_REGSC *(volatile uint8_t *)0x4007D002 // Regulator Status And Control register
363 #define PMC_REGSC_BGEN (uint8_t)0x10 // Bandgap Enable In VLPx Operation 363 #define PMC_REGSC_BGEN (uint8_t)0x10 // Bandgap Enable In VLPx Operation
364 #define PMC_REGSC_ACKISO (uint8_t)0x08 // Acknowledge Isolation 364 #define PMC_REGSC_ACKISO (uint8_t)0x08 // Acknowledge Isolation
365 #define PMC_REGSC_REGONS (uint8_t)0x04 // Regulator In Run Regulation Status 365 #define PMC_REGSC_REGONS (uint8_t)0x04 // Regulator In Run Regulation Status
366 #define PMC_REGSC_BGBE (uint8_t)0x01 // Bandgap Buffer Enable 366 #define PMC_REGSC_BGBE (uint8_t)0x01 // Bandgap Buffer Enable
367 367
368 // Chapter 16: Low-Leakage Wakeup Unit (LLWU) 368 // Chapter 16: Low-Leakage Wakeup Unit (LLWU)
369 #define LLWU_PE1 *(volatile uint8_t *)0x4007C000 // LLWU Pin Enable 1 register 369 #define LLWU_PE1 *(volatile uint8_t *)0x4007C000 // LLWU Pin Enable 1 register
370 #define LLWU_PE2 *(volatile uint8_t *)0x4007C001 // LLWU Pin Enable 2 register 370 #define LLWU_PE2 *(volatile uint8_t *)0x4007C001 // LLWU Pin Enable 2 register
371 #define LLWU_PE3 *(volatile uint8_t *)0x4007C002 // LLWU Pin Enable 3 register 371 #define LLWU_PE3 *(volatile uint8_t *)0x4007C002 // LLWU Pin Enable 3 register
377 #define LLWU_FILT1 *(volatile uint8_t *)0x4007C008 // LLWU Pin Filter 1 register 377 #define LLWU_FILT1 *(volatile uint8_t *)0x4007C008 // LLWU Pin Filter 1 register
378 #define LLWU_FILT2 *(volatile uint8_t *)0x4007C009 // LLWU Pin Filter 2 register 378 #define LLWU_FILT2 *(volatile uint8_t *)0x4007C009 // LLWU Pin Filter 2 register
379 #define LLWU_RST *(volatile uint8_t *)0x4007C00A // LLWU Reset Enable register 379 #define LLWU_RST *(volatile uint8_t *)0x4007C00A // LLWU Reset Enable register
380 380
381 // Chapter 17: Miscellaneous Control Module (MCM) 381 // Chapter 17: Miscellaneous Control Module (MCM)
382 #define MCM_PLASC *(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration 382 #define MCM_PLASC *(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration
383 #define MCM_PLAMC *(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration 383 #define MCM_PLAMC *(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration
384 #define MCM_PLACR *(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register (MK20DX128) 384 #define MCM_PLACR *(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register (MK20DX128)
385 #define MCM_PLACR_ARG (uint32_t)0x00000200 // Arbitration select, 0=fixed, 1=round-robin 385 #define MCM_PLACR_ARG (uint32_t)0x00000200 // Arbitration select, 0=fixed, 1=round-robin
386 #define MCM_CR *(volatile uint32_t *)0xE008000C // RAM arbitration control register (MK20DX256) 386 #define MCM_CR *(volatile uint32_t *)0xE008000C // RAM arbitration control register (MK20DX256)
387 #define MCM_CR_SRAMLWP (uint32_t)0x40000000 // SRAM_L write protect 387 #define MCM_CR_SRAMLWP (uint32_t)0x40000000 // SRAM_L write protect
388 #define MCM_CR_SRAMLAP(n) (uint32_t)(((n) & 0x03) << 28) // SRAM_L priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA 388 #define MCM_CR_SRAMLAP(n) (uint32_t)(((n) & 0x03) << 28) // SRAM_L priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
389 #define MCM_CR_SRAMUWP (uint32_t)0x04000000 // SRAM_U write protect 389 #define MCM_CR_SRAMUWP (uint32_t)0x04000000 // SRAM_U write protect
390 #define MCM_CR_SRAMUAP(n) (uint32_t)(((n) & 0x03) << 24) // SRAM_U priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA 390 #define MCM_CR_SRAMUAP(n) (uint32_t)(((n) & 0x03) << 24) // SRAM_U priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
391 391
392 // Crossbar Switch (AXBS) - only programmable on MK20DX256 392 // Crossbar Switch (AXBS) - only programmable on MK20DX256
393 #define AXBS_PRS0 *(volatile uint32_t *)0x40004000 // Priority Registers Slave 0 393 #define AXBS_PRS0 *(volatile uint32_t *)0x40004000 // Priority Registers Slave 0
394 #define AXBS_CRS0 *(volatile uint32_t *)0x40004010 // Control Register 0 394 #define AXBS_CRS0 *(volatile uint32_t *)0x40004010 // Control Register 0
395 #define AXBS_PRS1 *(volatile uint32_t *)0x40004100 // Priority Registers Slave 1 395 #define AXBS_PRS1 *(volatile uint32_t *)0x40004100 // Priority Registers Slave 1
396 #define AXBS_CRS1 *(volatile uint32_t *)0x40004110 // Control Register 1 396 #define AXBS_CRS1 *(volatile uint32_t *)0x40004110 // Control Register 1
397 #define AXBS_PRS2 *(volatile uint32_t *)0x40004200 // Priority Registers Slave 2 397 #define AXBS_PRS2 *(volatile uint32_t *)0x40004200 // Priority Registers Slave 2
398 #define AXBS_CRS2 *(volatile uint32_t *)0x40004210 // Control Register 2 398 #define AXBS_CRS2 *(volatile uint32_t *)0x40004210 // Control Register 2
399 #define AXBS_PRS3 *(volatile uint32_t *)0x40004300 // Priority Registers Slave 3 399 #define AXBS_PRS3 *(volatile uint32_t *)0x40004300 // Priority Registers Slave 3
400 #define AXBS_CRS3 *(volatile uint32_t *)0x40004310 // Control Register 3 400 #define AXBS_CRS3 *(volatile uint32_t *)0x40004310 // Control Register 3
401 #define AXBS_PRS4 *(volatile uint32_t *)0x40004400 // Priority Registers Slave 4 401 #define AXBS_PRS4 *(volatile uint32_t *)0x40004400 // Priority Registers Slave 4
402 #define AXBS_CRS4 *(volatile uint32_t *)0x40004410 // Control Register 4 402 #define AXBS_CRS4 *(volatile uint32_t *)0x40004410 // Control Register 4
403 #define AXBS_PRS5 *(volatile uint32_t *)0x40004500 // Priority Registers Slave 5 403 #define AXBS_PRS5 *(volatile uint32_t *)0x40004500 // Priority Registers Slave 5
404 #define AXBS_CRS5 *(volatile uint32_t *)0x40004510 // Control Register 5 404 #define AXBS_CRS5 *(volatile uint32_t *)0x40004510 // Control Register 5
405 #define AXBS_PRS6 *(volatile uint32_t *)0x40004600 // Priority Registers Slave 6 405 #define AXBS_PRS6 *(volatile uint32_t *)0x40004600 // Priority Registers Slave 6
406 #define AXBS_CRS6 *(volatile uint32_t *)0x40004610 // Control Register 6 406 #define AXBS_CRS6 *(volatile uint32_t *)0x40004610 // Control Register 6
407 #define AXBS_PRS7 *(volatile uint32_t *)0x40004700 // Priority Registers Slave 7 407 #define AXBS_PRS7 *(volatile uint32_t *)0x40004700 // Priority Registers Slave 7
408 #define AXBS_CRS7 *(volatile uint32_t *)0x40004710 // Control Register 7 408 #define AXBS_CRS7 *(volatile uint32_t *)0x40004710 // Control Register 7
409 #define AXBS_MGPCR0 *(volatile uint32_t *)0x40004800 // Master 0 General Purpose Control Register 409 #define AXBS_MGPCR0 *(volatile uint32_t *)0x40004800 // Master 0 General Purpose Control Register
410 #define AXBS_MGPCR1 *(volatile uint32_t *)0x40004900 // Master 1 General Purpose Control Register 410 #define AXBS_MGPCR1 *(volatile uint32_t *)0x40004900 // Master 1 General Purpose Control Register
411 #define AXBS_MGPCR2 *(volatile uint32_t *)0x40004A00 // Master 2 General Purpose Control Register 411 #define AXBS_MGPCR2 *(volatile uint32_t *)0x40004A00 // Master 2 General Purpose Control Register
412 #define AXBS_MGPCR3 *(volatile uint32_t *)0x40004B00 // Master 3 General Purpose Control Register 412 #define AXBS_MGPCR3 *(volatile uint32_t *)0x40004B00 // Master 3 General Purpose Control Register
413 #define AXBS_MGPCR4 *(volatile uint32_t *)0x40004C00 // Master 4 General Purpose Control Register 413 #define AXBS_MGPCR4 *(volatile uint32_t *)0x40004C00 // Master 4 General Purpose Control Register
414 #define AXBS_MGPCR5 *(volatile uint32_t *)0x40004D00 // Master 5 General Purpose Control Register 414 #define AXBS_MGPCR5 *(volatile uint32_t *)0x40004D00 // Master 5 General Purpose Control Register
415 #define AXBS_MGPCR6 *(volatile uint32_t *)0x40004E00 // Master 6 General Purpose Control Register 415 #define AXBS_MGPCR6 *(volatile uint32_t *)0x40004E00 // Master 6 General Purpose Control Register
416 #define AXBS_MGPCR7 *(volatile uint32_t *)0x40004F00 // Master 7 General Purpose Control Register 416 #define AXBS_MGPCR7 *(volatile uint32_t *)0x40004F00 // Master 7 General Purpose Control Register
417 #define AXBS_CRS_READONLY (uint32_t)0x80000000 417 #define AXBS_CRS_READONLY (uint32_t)0x80000000
418 #define AXBS_CRS_HALTLOWPRIORITY (uint32_t)0x40000000 418 #define AXBS_CRS_HALTLOWPRIORITY (uint32_t)0x40000000
419 #define AXBS_CRS_ARB_FIXED (uint32_t)0x00000000 419 #define AXBS_CRS_ARB_FIXED (uint32_t)0x00000000
420 #define AXBS_CRS_ARB_ROUNDROBIN (uint32_t)0x00010000 420 #define AXBS_CRS_ARB_ROUNDROBIN (uint32_t)0x00010000
421 #define AXBS_CRS_PARK_FIXED (uint32_t)0x00000000 421 #define AXBS_CRS_PARK_FIXED (uint32_t)0x00000000
422 #define AXBS_CRS_PARK_PREVIOUS (uint32_t)0x00000010 422 #define AXBS_CRS_PARK_PREVIOUS (uint32_t)0x00000010
423 #define AXBS_CRS_PARK_NONE (uint32_t)0x00000020 423 #define AXBS_CRS_PARK_NONE (uint32_t)0x00000020
424 #define AXBS_CRS_PARK(n) (uint32_t)(((n) & 7) << 0) 424 #define AXBS_CRS_PARK(n) (uint32_t)(((n) & 7) << 0)
425 425
426 426
427 427
428 // Chapter 20: Direct Memory Access Multiplexer (DMAMUX) 428 // Chapter 20: Direct Memory Access Multiplexer (DMAMUX)
429 #define DMAMUX0_CHCFG0 *(volatile uint8_t *)0x40021000 // Channel Configuration register 429 #define DMAMUX0_CHCFG0 *(volatile uint8_t *)0x40021000 // Channel Configuration register
430 #define DMAMUX0_CHCFG1 *(volatile uint8_t *)0x40021001 // Channel Configuration register 430 #define DMAMUX0_CHCFG1 *(volatile uint8_t *)0x40021001 // Channel Configuration register
431 #define DMAMUX0_CHCFG2 *(volatile uint8_t *)0x40021002 // Channel Configuration register 431 #define DMAMUX0_CHCFG2 *(volatile uint8_t *)0x40021002 // Channel Configuration register
432 #define DMAMUX0_CHCFG3 *(volatile uint8_t *)0x40021003 // Channel Configuration register 432 #define DMAMUX0_CHCFG3 *(volatile uint8_t *)0x40021003 // Channel Configuration register
433 #define DMAMUX0_CHCFG4 *(volatile uint8_t *)0x40021004 // Channel Configuration register 433 #define DMAMUX0_CHCFG4 *(volatile uint8_t *)0x40021004 // Channel Configuration register
434 #define DMAMUX0_CHCFG5 *(volatile uint8_t *)0x40021005 // Channel Configuration register 434 #define DMAMUX0_CHCFG5 *(volatile uint8_t *)0x40021005 // Channel Configuration register
435 #define DMAMUX0_CHCFG6 *(volatile uint8_t *)0x40021006 // Channel Configuration register 435 #define DMAMUX0_CHCFG6 *(volatile uint8_t *)0x40021006 // Channel Configuration register
436 #define DMAMUX0_CHCFG7 *(volatile uint8_t *)0x40021007 // Channel Configuration register 436 #define DMAMUX0_CHCFG7 *(volatile uint8_t *)0x40021007 // Channel Configuration register
437 #define DMAMUX0_CHCFG8 *(volatile uint8_t *)0x40021008 // Channel Configuration register 437 #define DMAMUX0_CHCFG8 *(volatile uint8_t *)0x40021008 // Channel Configuration register
438 #define DMAMUX0_CHCFG9 *(volatile uint8_t *)0x40021009 // Channel Configuration register 438 #define DMAMUX0_CHCFG9 *(volatile uint8_t *)0x40021009 // Channel Configuration register
439 #define DMAMUX0_CHCFG10 *(volatile uint8_t *)0x4002100A // Channel Configuration register 439 #define DMAMUX0_CHCFG10 *(volatile uint8_t *)0x4002100A // Channel Configuration register
440 #define DMAMUX0_CHCFG11 *(volatile uint8_t *)0x4002100B // Channel Configuration register 440 #define DMAMUX0_CHCFG11 *(volatile uint8_t *)0x4002100B // Channel Configuration register
441 #define DMAMUX0_CHCFG12 *(volatile uint8_t *)0x4002100C // Channel Configuration register 441 #define DMAMUX0_CHCFG12 *(volatile uint8_t *)0x4002100C // Channel Configuration register
442 #define DMAMUX0_CHCFG13 *(volatile uint8_t *)0x4002100D // Channel Configuration register 442 #define DMAMUX0_CHCFG13 *(volatile uint8_t *)0x4002100D // Channel Configuration register
443 #define DMAMUX0_CHCFG14 *(volatile uint8_t *)0x4002100E // Channel Configuration register 443 #define DMAMUX0_CHCFG14 *(volatile uint8_t *)0x4002100E // Channel Configuration register
444 #define DMAMUX0_CHCFG15 *(volatile uint8_t *)0x4002100F // Channel Configuration register 444 #define DMAMUX0_CHCFG15 *(volatile uint8_t *)0x4002100F // Channel Configuration register
445 #define DMAMUX_DISABLE 0 445 #define DMAMUX_DISABLE 0
446 #define DMAMUX_TRIG 64 446 #define DMAMUX_TRIG 64
447 #define DMAMUX_ENABLE 128 447 #define DMAMUX_ENABLE 128
448 #define DMAMUX_SOURCE_UART0_RX 2 448 #define DMAMUX_SOURCE_UART0_RX 2
449 #define DMAMUX_SOURCE_UART0_TX 3 449 #define DMAMUX_SOURCE_UART0_TX 3
450 #define DMAMUX_SOURCE_UART1_RX 4 450 #define DMAMUX_SOURCE_UART1_RX 4
451 #define DMAMUX_SOURCE_UART1_TX 5 451 #define DMAMUX_SOURCE_UART1_TX 5
452 #define DMAMUX_SOURCE_UART2_RX 6 452 #define DMAMUX_SOURCE_UART2_RX 6
453 #define DMAMUX_SOURCE_UART2_TX 7 453 #define DMAMUX_SOURCE_UART2_TX 7
454 #define DMAMUX_SOURCE_I2S0_RX 14 454 #define DMAMUX_SOURCE_I2S0_RX 14
455 #define DMAMUX_SOURCE_I2S0_TX 15 455 #define DMAMUX_SOURCE_I2S0_TX 15
456 #define DMAMUX_SOURCE_SPI0_RX 16 456 #define DMAMUX_SOURCE_SPI0_RX 16
457 #define DMAMUX_SOURCE_SPI0_TX 17 457 #define DMAMUX_SOURCE_SPI0_TX 17
458 #define DMAMUX_SOURCE_I2C0 22 458 #define DMAMUX_SOURCE_I2C0 22
459 #define DMAMUX_SOURCE_I2C1 23 459 #define DMAMUX_SOURCE_I2C1 23
460 #define DMAMUX_SOURCE_FTM0_CH0 24 460 #define DMAMUX_SOURCE_FTM0_CH0 24
461 #define DMAMUX_SOURCE_FTM0_CH1 25 461 #define DMAMUX_SOURCE_FTM0_CH1 25
462 #define DMAMUX_SOURCE_FTM0_CH2 26 462 #define DMAMUX_SOURCE_FTM0_CH2 26
463 #define DMAMUX_SOURCE_FTM0_CH3 27 463 #define DMAMUX_SOURCE_FTM0_CH3 27
464 #define DMAMUX_SOURCE_FTM0_CH4 28 464 #define DMAMUX_SOURCE_FTM0_CH4 28
465 #define DMAMUX_SOURCE_FTM0_CH5 29 465 #define DMAMUX_SOURCE_FTM0_CH5 29
466 #define DMAMUX_SOURCE_FTM0_CH6 30 466 #define DMAMUX_SOURCE_FTM0_CH6 30
467 #define DMAMUX_SOURCE_FTM0_CH7 31 467 #define DMAMUX_SOURCE_FTM0_CH7 31
468 #define DMAMUX_SOURCE_FTM1_CH0 32 468 #define DMAMUX_SOURCE_FTM1_CH0 32
469 #define DMAMUX_SOURCE_FTM1_CH1 33 469 #define DMAMUX_SOURCE_FTM1_CH1 33
470 #define DMAMUX_SOURCE_FTM2_CH0 34 470 #define DMAMUX_SOURCE_FTM2_CH0 34
471 #define DMAMUX_SOURCE_FTM2_CH1 35 471 #define DMAMUX_SOURCE_FTM2_CH1 35
472 #define DMAMUX_SOURCE_ADC0 40 472 #define DMAMUX_SOURCE_ADC0 40
473 #define DMAMUX_SOURCE_ADC1 41 473 #define DMAMUX_SOURCE_ADC1 41
474 #define DMAMUX_SOURCE_CMP0 42 474 #define DMAMUX_SOURCE_CMP0 42
475 #define DMAMUX_SOURCE_CMP1 43 475 #define DMAMUX_SOURCE_CMP1 43
476 #define DMAMUX_SOURCE_CMP2 44 476 #define DMAMUX_SOURCE_CMP2 44
477 #define DMAMUX_SOURCE_DAC0 45 477 #define DMAMUX_SOURCE_DAC0 45
478 #define DMAMUX_SOURCE_CMT 47 478 #define DMAMUX_SOURCE_CMT 47
479 #define DMAMUX_SOURCE_PDB 48 479 #define DMAMUX_SOURCE_PDB 48
480 #define DMAMUX_SOURCE_PORTA 49 480 #define DMAMUX_SOURCE_PORTA 49
481 #define DMAMUX_SOURCE_PORTB 50 481 #define DMAMUX_SOURCE_PORTB 50
482 #define DMAMUX_SOURCE_PORTC 51 482 #define DMAMUX_SOURCE_PORTC 51
483 #define DMAMUX_SOURCE_PORTD 52 483 #define DMAMUX_SOURCE_PORTD 52
484 #define DMAMUX_SOURCE_PORTE 53 484 #define DMAMUX_SOURCE_PORTE 53
485 #define DMAMUX_SOURCE_ALWAYS0 54 485 #define DMAMUX_SOURCE_ALWAYS0 54
486 #define DMAMUX_SOURCE_ALWAYS1 55 486 #define DMAMUX_SOURCE_ALWAYS1 55
487 #define DMAMUX_SOURCE_ALWAYS2 56 487 #define DMAMUX_SOURCE_ALWAYS2 56
488 #define DMAMUX_SOURCE_ALWAYS3 57 488 #define DMAMUX_SOURCE_ALWAYS3 57
489 #define DMAMUX_SOURCE_ALWAYS4 58 489 #define DMAMUX_SOURCE_ALWAYS4 58
490 #define DMAMUX_SOURCE_ALWAYS5 59 490 #define DMAMUX_SOURCE_ALWAYS5 59
491 #define DMAMUX_SOURCE_ALWAYS6 60 491 #define DMAMUX_SOURCE_ALWAYS6 60
492 #define DMAMUX_SOURCE_ALWAYS7 61 492 #define DMAMUX_SOURCE_ALWAYS7 61
493 #define DMAMUX_SOURCE_ALWAYS8 62 493 #define DMAMUX_SOURCE_ALWAYS8 62
494 #define DMAMUX_SOURCE_ALWAYS9 63 494 #define DMAMUX_SOURCE_ALWAYS9 63
495 495
496 // Chapter 21: Direct Memory Access Controller (eDMA) 496 // Chapter 21: Direct Memory Access Controller (eDMA)
497 #define DMA_CR *(volatile uint32_t *)0x40008000 // Control Register 497 #define DMA_CR *(volatile uint32_t *)0x40008000 // Control Register
498 #define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer 498 #define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer
499 #define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer 499 #define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer
500 #define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping 500 #define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping
501 #define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode 501 #define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode
502 #define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations 502 #define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations
503 #define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error 503 #define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error
504 #define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration 504 #define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration
505 #define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug 505 #define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug
506 #define DMA_ES *(volatile uint32_t *)0x40008004 // Error Status Register 506 #define DMA_ES *(volatile uint32_t *)0x40008004 // Error Status Register
507 #define DMA_ERQ *(volatile uint32_t *)0x4000800C // Enable Request Register 507 #define DMA_ERQ *(volatile uint32_t *)0x4000800C // Enable Request Register
508 #define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0 508 #define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0
509 #define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1 509 #define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1
510 #define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2 510 #define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2
511 #define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3 511 #define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3
512 #define DMA_EEI *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register 512 #define DMA_EEI *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register
513 #define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0 513 #define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0
514 #define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1 514 #define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1
515 #define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2 515 #define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2
516 #define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3 516 #define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3
517 #define DMA_CEEI *(volatile uint8_t *)0x40008018 // Clear Enable Error Interrupt Register 517 #define DMA_CEEI *(volatile uint8_t *)0x40008018 // Clear Enable Error Interrupt Register
518 #define DMA_CEEI_CEEI(n) ((uint8_t)(n & 3)<<0) // Clear Enable Error Interrupt 518 #define DMA_CEEI_CEEI(n) ((uint8_t)(n & 3)<<0) // Clear Enable Error Interrupt
519 #define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts 519 #define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts
520 #define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP 520 #define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP
521 #define DMA_SEEI *(volatile uint8_t *)0x40008019 // Set Enable Error Interrupt Register 521 #define DMA_SEEI *(volatile uint8_t *)0x40008019 // Set Enable Error Interrupt Register
522 #define DMA_SEEI_SEEI(n) ((uint8_t)(n & 3)<<0) // Set Enable Error Interrupt 522 #define DMA_SEEI_SEEI(n) ((uint8_t)(n & 3)<<0) // Set Enable Error Interrupt
523 #define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts 523 #define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts
524 #define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP 524 #define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP
525 #define DMA_CERQ *(volatile uint8_t *)0x4000801A // Clear Enable Request Register 525 #define DMA_CERQ *(volatile uint8_t *)0x4000801A // Clear Enable Request Register
526 #define DMA_CERQ_CERQ(n) ((uint8_t)(n & 3)<<0) // Clear Enable Request 526 #define DMA_CERQ_CERQ(n) ((uint8_t)(n & 3)<<0) // Clear Enable Request
527 #define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests 527 #define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests
528 #define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP 528 #define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP
529 #define DMA_SERQ *(volatile uint8_t *)0x4000801B // Set Enable Request Register 529 #define DMA_SERQ *(volatile uint8_t *)0x4000801B // Set Enable Request Register
530 #define DMA_SERQ_SERQ(n) ((uint8_t)(n & 3)<<0) // Set Enable Request 530 #define DMA_SERQ_SERQ(n) ((uint8_t)(n & 3)<<0) // Set Enable Request
531 #define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests 531 #define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests
532 #define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP 532 #define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP
533 #define DMA_CDNE *(volatile uint8_t *)0x4000801C // Clear DONE Status Bit Register 533 #define DMA_CDNE *(volatile uint8_t *)0x4000801C // Clear DONE Status Bit Register
534 #define DMA_CDNE_CDNE(n) ((uint8_t)(n & 3)<<0) // Clear Done Bit 534 #define DMA_CDNE_CDNE(n) ((uint8_t)(n & 3)<<0) // Clear Done Bit
535 #define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits 535 #define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits
536 #define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP 536 #define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP
537 #define DMA_SSRT *(volatile uint8_t *)0x4000801D // Set START Bit Register 537 #define DMA_SSRT *(volatile uint8_t *)0x4000801D // Set START Bit Register
538 #define DMA_SSRT_SSRT(n) ((uint8_t)(n & 3)<<0) // Set Start Bit 538 #define DMA_SSRT_SSRT(n) ((uint8_t)(n & 3)<<0) // Set Start Bit
539 #define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits 539 #define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits
540 #define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP 540 #define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP
541 #define DMA_CERR *(volatile uint8_t *)0x4000801E // Clear Error Register 541 #define DMA_CERR *(volatile uint8_t *)0x4000801E // Clear Error Register
542 #define DMA_CERR_CERR(n) ((uint8_t)(n & 3)<<0) // Clear Error Indicator 542 #define DMA_CERR_CERR(n) ((uint8_t)(n & 3)<<0) // Clear Error Indicator
543 #define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators 543 #define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators
544 #define DMA_CERR_NOP ((uint8_t)1<<7) // NOP 544 #define DMA_CERR_NOP ((uint8_t)1<<7) // NOP
545 #define DMA_CINT *(volatile uint8_t *)0x4000801F // Clear Interrupt Request Register 545 #define DMA_CINT *(volatile uint8_t *)0x4000801F // Clear Interrupt Request Register
546 #define DMA_CINT_CINT(n) ((uint8_t)(n & 3)<<0) // Clear Interrupt Request 546 #define DMA_CINT_CINT(n) ((uint8_t)(n & 3)<<0) // Clear Interrupt Request
547 #define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests 547 #define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests
548 #define DMA_CINT_NOP ((uint8_t)1<<7) // NOP 548 #define DMA_CINT_NOP ((uint8_t)1<<7) // NOP
549 #define DMA_INT *(volatile uint32_t *)0x40008024 // Interrupt Request Register 549 #define DMA_INT *(volatile uint32_t *)0x40008024 // Interrupt Request Register
550 #define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0 550 #define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0
551 #define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1 551 #define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1
552 #define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2 552 #define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2
553 #define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3 553 #define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3
554 #define DMA_ERR *(volatile uint32_t *)0x4000802C // Error Register 554 #define DMA_ERR *(volatile uint32_t *)0x4000802C // Error Register
555 #define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0 555 #define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0
556 #define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1 556 #define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1
557 #define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2 557 #define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2
558 #define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3 558 #define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3
559 #define DMA_HRS *(volatile uint32_t *)0x40008034 // Hardware Request Status Register 559 #define DMA_HRS *(volatile uint32_t *)0x40008034 // Hardware Request Status Register
560 #define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0 560 #define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0
561 #define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1 561 #define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1
562 #define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2 562 #define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2
563 #define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3 563 #define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3
564 #define DMA_DCHPRI3 *(volatile uint8_t *)0x40008100 // Channel n Priority Register 564 #define DMA_DCHPRI3 *(volatile uint8_t *)0x40008100 // Channel n Priority Register
565 #define DMA_DCHPRI2 *(volatile uint8_t *)0x40008101 // Channel n Priority Register 565 #define DMA_DCHPRI2 *(volatile uint8_t *)0x40008101 // Channel n Priority Register
566 #define DMA_DCHPRI1 *(volatile uint8_t *)0x40008102 // Channel n Priority Register 566 #define DMA_DCHPRI1 *(volatile uint8_t *)0x40008102 // Channel n Priority Register
567 #define DMA_DCHPRI0 *(volatile uint8_t *)0x40008103 // Channel n Priority Register 567 #define DMA_DCHPRI0 *(volatile uint8_t *)0x40008103 // Channel n Priority Register
568 #define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 3)<<0) // Channel Arbitration Priority 568 #define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 3)<<0) // Channel Arbitration Priority
569 #define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability 569 #define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability
570 #define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption 570 #define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption
571 571
572 572
573 #define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11) 573 #define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11)
574 #define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8) 574 #define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8)
575 #define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3) 575 #define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3)
576 #define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0) 576 #define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0)
577 #define DMA_TCD_ATTR_SIZE_8BIT 0 577 #define DMA_TCD_ATTR_SIZE_8BIT 0
578 #define DMA_TCD_ATTR_SIZE_16BIT 1 578 #define DMA_TCD_ATTR_SIZE_16BIT 1
579 #define DMA_TCD_ATTR_SIZE_32BIT 2 579 #define DMA_TCD_ATTR_SIZE_32BIT 2
580 #define DMA_TCD_ATTR_SIZE_16BYTE 4 580 #define DMA_TCD_ATTR_SIZE_16BYTE 4
581 #define DMA_TCD_ATTR_SIZE_32BYTE 5 581 #define DMA_TCD_ATTR_SIZE_32BYTE 5
582 #define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14) 582 #define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14)
583 #define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0x3) << 8) 583 #define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0x3) << 8)
584 #define DMA_TCD_CSR_DONE 0x0080 584 #define DMA_TCD_CSR_DONE 0x0080
585 #define DMA_TCD_CSR_ACTIVE 0x0040 585 #define DMA_TCD_CSR_ACTIVE 0x0040
586 #define DMA_TCD_CSR_MAJORELINK 0x0020 586 #define DMA_TCD_CSR_MAJORELINK 0x0020
587 #define DMA_TCD_CSR_ESG 0x0010 587 #define DMA_TCD_CSR_ESG 0x0010
588 #define DMA_TCD_CSR_DREQ 0x0008 588 #define DMA_TCD_CSR_DREQ 0x0008
589 #define DMA_TCD_CSR_INTHALF 0x0004 589 #define DMA_TCD_CSR_INTHALF 0x0004
590 #define DMA_TCD_CSR_INTMAJOR 0x0002 590 #define DMA_TCD_CSR_INTMAJOR 0x0002
591 #define DMA_TCD_CSR_START 0x0001 591 #define DMA_TCD_CSR_START 0x0001
592 #define DMA_TCD_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask 592 #define DMA_TCD_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask
593 #define DMA_TCD_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete 593 #define DMA_TCD_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
594 #define DMA_TCD_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask 594 #define DMA_TCD_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask
595 #define DMA_TCD_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete 595 #define DMA_TCD_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
596 #define DMA_TCD_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable 596 #define DMA_TCD_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable
597 #define DMA_TCD_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable 597 #define DMA_TCD_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable
598 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)(n)) // NBytes transfer count when minor loop disabled 598 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)(n)) // NBytes transfer count when minor loop disabled
599 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)(n & 0x1F)) // NBytes transfer count when minor loop enabled 599 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)(n & 0x1F)) // NBytes transfer count when minor loop enabled
600 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset 600 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset
601 601
602 #define DMA_TCD0_SADDR *(volatile const void * volatile *)0x40009000 // TCD Source Address 602 #define DMA_TCD0_SADDR *(volatile const void * volatile *)0x40009000 // TCD Source Address
603 #define DMA_TCD0_SOFF *(volatile int16_t *)0x40009004 // TCD Signed Source Address Offset 603 #define DMA_TCD0_SOFF *(volatile int16_t *)0x40009004 // TCD Signed Source Address Offset
604 #define DMA_TCD0_ATTR *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes 604 #define DMA_TCD0_ATTR *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes
605 #define DMA_TCD0_NBYTES_MLNO *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled) 605 #define DMA_TCD0_NBYTES_MLNO *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled)
606 #define DMA_TCD0_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) 606 #define DMA_TCD0_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
607 #define DMA_TCD0_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) 607 #define DMA_TCD0_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
608 #define DMA_TCD0_SLAST *(volatile int32_t *)0x4000900C // TCD Last Source Address Adjustment 608 #define DMA_TCD0_SLAST *(volatile int32_t *)0x4000900C // TCD Last Source Address Adjustment
609 #define DMA_TCD0_DADDR *(volatile void * volatile *)0x40009010 // TCD Destination Address 609 #define DMA_TCD0_DADDR *(volatile void * volatile *)0x40009010 // TCD Destination Address
610 #define DMA_TCD0_DOFF *(volatile int16_t *)0x40009014 // TCD Signed Destination Address Offset 610 #define DMA_TCD0_DOFF *(volatile int16_t *)0x40009014 // TCD Signed Destination Address Offset
611 #define DMA_TCD0_CITER_ELINKYES *(volatile uint16_t *)0x40009016 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled 611 #define DMA_TCD0_CITER_ELINKYES *(volatile uint16_t *)0x40009016 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
612 #define DMA_TCD0_CITER_ELINKNO *(volatile uint16_t *)0x40009016 // ?? 612 #define DMA_TCD0_CITER_ELINKNO *(volatile uint16_t *)0x40009016 // ??
613 #define DMA_TCD0_DLASTSGA *(volatile int32_t *)0x40009018 // TCD Last Destination Address Adjustment/Scatter Gather Address 613 #define DMA_TCD0_DLASTSGA *(volatile int32_t *)0x40009018 // TCD Last Destination Address Adjustment/Scatter Gather Address
614 #define DMA_TCD0_CSR *(volatile uint16_t *)0x4000901C // TCD Control and Status 614 #define DMA_TCD0_CSR *(volatile uint16_t *)0x4000901C // TCD Control and Status
615 #define DMA_TCD0_BITER_ELINKYES *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled 615 #define DMA_TCD0_BITER_ELINKYES *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
616 #define DMA_TCD0_BITER_ELINKNO *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled 616 #define DMA_TCD0_BITER_ELINKNO *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
617 617
618 #define DMA_TCD1_SADDR *(volatile const void * volatile *)0x40009020 // TCD Source Address 618 #define DMA_TCD1_SADDR *(volatile const void * volatile *)0x40009020 // TCD Source Address
619 #define DMA_TCD1_SOFF *(volatile int16_t *)0x40009024 // TCD Signed Source Address Offset 619 #define DMA_TCD1_SOFF *(volatile int16_t *)0x40009024 // TCD Signed Source Address Offset
620 #define DMA_TCD1_ATTR *(volatile uint16_t *)0x40009026 // TCD Transfer Attributes 620 #define DMA_TCD1_ATTR *(volatile uint16_t *)0x40009026 // TCD Transfer Attributes
621 #define DMA_TCD1_NBYTES_MLNO *(volatile uint32_t *)0x40009028 // TCD Minor Byte Count, Minor Loop Disabled 621 #define DMA_TCD1_NBYTES_MLNO *(volatile uint32_t *)0x40009028 // TCD Minor Byte Count, Minor Loop Disabled
622 #define DMA_TCD1_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled 622 #define DMA_TCD1_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
623 #define DMA_TCD1_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled 623 #define DMA_TCD1_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
624 #define DMA_TCD1_SLAST *(volatile int32_t *)0x4000902C // TCD Last Source Address Adjustment 624 #define DMA_TCD1_SLAST *(volatile int32_t *)0x4000902C // TCD Last Source Address Adjustment
625 #define DMA_TCD1_DADDR *(volatile void * volatile *)0x40009030 // TCD Destination Address 625 #define DMA_TCD1_DADDR *(volatile void * volatile *)0x40009030 // TCD Destination Address
626 #define DMA_TCD1_DOFF *(volatile int16_t *)0x40009034 // TCD Signed Destination Address Offset 626 #define DMA_TCD1_DOFF *(volatile int16_t *)0x40009034 // TCD Signed Destination Address Offset
627 #define DMA_TCD1_CITER_ELINKYES *(volatile uint16_t *)0x40009036 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled 627 #define DMA_TCD1_CITER_ELINKYES *(volatile uint16_t *)0x40009036 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
628 #define DMA_TCD1_CITER_ELINKNO *(volatile uint16_t *)0x40009036 // ?? 628 #define DMA_TCD1_CITER_ELINKNO *(volatile uint16_t *)0x40009036 // ??
629 #define DMA_TCD1_DLASTSGA *(volatile int32_t *)0x40009038 // TCD Last Destination Address Adjustment/Scatter Gather Address 629 #define DMA_TCD1_DLASTSGA *(volatile int32_t *)0x40009038 // TCD Last Destination Address Adjustment/Scatter Gather Address
630 #define DMA_TCD1_CSR *(volatile uint16_t *)0x4000903C // TCD Control and Status 630 #define DMA_TCD1_CSR *(volatile uint16_t *)0x4000903C // TCD Control and Status
631 #define DMA_TCD1_BITER_ELINKYES *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled 631 #define DMA_TCD1_BITER_ELINKYES *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled
632 #define DMA_TCD1_BITER_ELINKNO *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled 632 #define DMA_TCD1_BITER_ELINKNO *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
633 633
634 #define DMA_TCD2_SADDR *(volatile const void * volatile *)0x40009040 // TCD Source Address 634 #define DMA_TCD2_SADDR *(volatile const void * volatile *)0x40009040 // TCD Source Address
635 #define DMA_TCD2_SOFF *(volatile int16_t *)0x40009044 // TCD Signed Source Address Offset 635 #define DMA_TCD2_SOFF *(volatile int16_t *)0x40009044 // TCD Signed Source Address Offset
636 #define DMA_TCD2_ATTR *(volatile uint16_t *)0x40009046 // TCD Transfer Attributes 636 #define DMA_TCD2_ATTR *(volatile uint16_t *)0x40009046 // TCD Transfer Attributes
637 #define DMA_TCD2_NBYTES_MLNO *(volatile uint32_t *)0x40009048 // TCD Minor Byte Count, Minor Loop Disabled 637 #define DMA_TCD2_NBYTES_MLNO *(volatile uint32_t *)0x40009048 // TCD Minor Byte Count, Minor Loop Disabled
638 #define DMA_TCD2_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled 638 #define DMA_TCD2_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
639 #define DMA_TCD2_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled 639 #define DMA_TCD2_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
640 #define DMA_TCD2_SLAST *(volatile int32_t *)0x4000904C // TCD Last Source Address Adjustment 640 #define DMA_TCD2_SLAST *(volatile int32_t *)0x4000904C // TCD Last Source Address Adjustment
641 #define DMA_TCD2_DADDR *(volatile void * volatile *)0x40009050 // TCD Destination Address 641 #define DMA_TCD2_DADDR *(volatile void * volatile *)0x40009050 // TCD Destination Address
642 #define DMA_TCD2_DOFF *(volatile int16_t *)0x40009054 // TCD Signed Destination Address Offset 642 #define DMA_TCD2_DOFF *(volatile int16_t *)0x40009054 // TCD Signed Destination Address Offset
643 #define DMA_TCD2_CITER_ELINKYES *(volatile uint16_t *)0x40009056 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled 643 #define DMA_TCD2_CITER_ELINKYES *(volatile uint16_t *)0x40009056 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
644 #define DMA_TCD2_CITER_ELINKNO *(volatile uint16_t *)0x40009056 // ?? 644 #define DMA_TCD2_CITER_ELINKNO *(volatile uint16_t *)0x40009056 // ??
645 #define DMA_TCD2_DLASTSGA *(volatile int32_t *)0x40009058 // TCD Last Destination Address Adjustment/Scatter Gather Address 645 #define DMA_TCD2_DLASTSGA *(volatile int32_t *)0x40009058 // TCD Last Destination Address Adjustment/Scatter Gather Address
646 #define DMA_TCD2_CSR *(volatile uint16_t *)0x4000905C // TCD Control and Status 646 #define DMA_TCD2_CSR *(volatile uint16_t *)0x4000905C // TCD Control and Status
647 #define DMA_TCD2_BITER_ELINKYES *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled 647 #define DMA_TCD2_BITER_ELINKYES *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
648 #define DMA_TCD2_BITER_ELINKNO *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled 648 #define DMA_TCD2_BITER_ELINKNO *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
649 649
650 #define DMA_TCD3_SADDR *(volatile const void * volatile *)0x40009060 // TCD Source Address 650 #define DMA_TCD3_SADDR *(volatile const void * volatile *)0x40009060 // TCD Source Address
651 #define DMA_TCD3_SOFF *(volatile int16_t *)0x40009064 // TCD Signed Source Address Offset 651 #define DMA_TCD3_SOFF *(volatile int16_t *)0x40009064 // TCD Signed Source Address Offset
652 #define DMA_TCD3_ATTR *(volatile uint16_t *)0x40009066 // TCD Transfer Attributes 652 #define DMA_TCD3_ATTR *(volatile uint16_t *)0x40009066 // TCD Transfer Attributes
653 #define DMA_TCD3_NBYTES_MLNO *(volatile uint32_t *)0x40009068 // TCD Minor Byte Count, Minor Loop Disabled 653 #define DMA_TCD3_NBYTES_MLNO *(volatile uint32_t *)0x40009068 // TCD Minor Byte Count, Minor Loop Disabled
654 #define DMA_TCD3_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled 654 #define DMA_TCD3_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
655 #define DMA_TCD3_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled 655 #define DMA_TCD3_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
656 #define DMA_TCD3_SLAST *(volatile int32_t *)0x4000906C // TCD Last Source Address Adjustment 656 #define DMA_TCD3_SLAST *(volatile int32_t *)0x4000906C // TCD Last Source Address Adjustment
657 #define DMA_TCD3_DADDR *(volatile void * volatile *)0x40009070 // TCD Destination Address 657 #define DMA_TCD3_DADDR *(volatile void * volatile *)0x40009070 // TCD Destination Address
658 #define DMA_TCD3_DOFF *(volatile int16_t *)0x40009074 // TCD Signed Destination Address Offset 658 #define DMA_TCD3_DOFF *(volatile int16_t *)0x40009074 // TCD Signed Destination Address Offset
659 #define DMA_TCD3_CITER_ELINKYES *(volatile uint16_t *)0x40009076 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled 659 #define DMA_TCD3_CITER_ELINKYES *(volatile uint16_t *)0x40009076 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
660 #define DMA_TCD3_CITER_ELINKNO *(volatile uint16_t *)0x40009076 // ?? 660 #define DMA_TCD3_CITER_ELINKNO *(volatile uint16_t *)0x40009076 // ??
661 #define DMA_TCD3_DLASTSGA *(volatile int32_t *)0x40009078 // TCD Last Destination Address Adjustment/Scatter Gather Address 661 #define DMA_TCD3_DLASTSGA *(volatile int32_t *)0x40009078 // TCD Last Destination Address Adjustment/Scatter Gather Address
662 #define DMA_TCD3_CSR *(volatile uint16_t *)0x4000907C // TCD Control and Status 662 #define DMA_TCD3_CSR *(volatile uint16_t *)0x4000907C // TCD Control and Status
663 #define DMA_TCD3_BITER_ELINKYES *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled 663 #define DMA_TCD3_BITER_ELINKYES *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled
664 #define DMA_TCD3_BITER_ELINKNO *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled 664 #define DMA_TCD3_BITER_ELINKNO *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled
665 665
666 // Chapter 22: External Watchdog Monitor (EWM) 666 // Chapter 22: External Watchdog Monitor (EWM)
667 #define EWM_CTRL *(volatile uint8_t *)0x40061000 // Control Register 667 #define EWM_CTRL *(volatile uint8_t *)0x40061000 // Control Register
668 #define EWM_SERV *(volatile uint8_t *)0x40061001 // Service Register 668 #define EWM_SERV *(volatile uint8_t *)0x40061001 // Service Register
669 #define EWM_CMPL *(volatile uint8_t *)0x40061002 // Compare Low Register 669 #define EWM_CMPL *(volatile uint8_t *)0x40061002 // Compare Low Register
670 #define EWM_CMPH *(volatile uint8_t *)0x40061003 // Compare High Register 670 #define EWM_CMPH *(volatile uint8_t *)0x40061003 // Compare High Register
671 671
672 // Chapter 23: Watchdog Timer (WDOG) 672 // Chapter 23: Watchdog Timer (WDOG)
673 #define WDOG_STCTRLH *(volatile uint16_t *)0x40052000 // Watchdog Status and Control Register High 673 #define WDOG_STCTRLH *(volatile uint16_t *)0x40052000 // Watchdog Status and Control Register High
674 #define WDOG_STCTRLH_DISTESTWDOG (uint16_t)0x4000 // Allows the WDOG's functional test mode to be disabled permanently. 674 #define WDOG_STCTRLH_DISTESTWDOG (uint16_t)0x4000 // Allows the WDOG's functional test mode to be disabled permanently.
675 #define WDOG_STCTRLH_BYTESEL(n) (uint16_t)(((n) & 3) << 12) // selects the byte to be tested when the watchdog is in the byte test mode. 675 #define WDOG_STCTRLH_BYTESEL(n) (uint16_t)(((n) & 3) << 12) // selects the byte to be tested when the watchdog is in the byte test mode.
676 #define WDOG_STCTRLH_TESTSEL (uint16_t)0x0800 676 #define WDOG_STCTRLH_TESTSEL (uint16_t)0x0800
677 #define WDOG_STCTRLH_TESTWDOG (uint16_t)0x0400 677 #define WDOG_STCTRLH_TESTWDOG (uint16_t)0x0400
678 #define WDOG_STCTRLH_WAITEN (uint16_t)0x0080 678 #define WDOG_STCTRLH_WAITEN (uint16_t)0x0080
679 #define WDOG_STCTRLH_STOPEN (uint16_t)0x0040 679 #define WDOG_STCTRLH_STOPEN (uint16_t)0x0040
680 #define WDOG_STCTRLH_DBGEN (uint16_t)0x0020 680 #define WDOG_STCTRLH_DBGEN (uint16_t)0x0020
681 #define WDOG_STCTRLH_ALLOWUPDATE (uint16_t)0x0010 681 #define WDOG_STCTRLH_ALLOWUPDATE (uint16_t)0x0010
682 #define WDOG_STCTRLH_WINEN (uint16_t)0x0008 682 #define WDOG_STCTRLH_WINEN (uint16_t)0x0008
683 #define WDOG_STCTRLH_IRQRSTEN (uint16_t)0x0004 683 #define WDOG_STCTRLH_IRQRSTEN (uint16_t)0x0004
684 #define WDOG_STCTRLH_CLKSRC (uint16_t)0x0002 684 #define WDOG_STCTRLH_CLKSRC (uint16_t)0x0002
685 #define WDOG_STCTRLH_WDOGEN (uint16_t)0x0001 685 #define WDOG_STCTRLH_WDOGEN (uint16_t)0x0001
686 #define WDOG_STCTRLL *(volatile uint16_t *)0x40052002 // Watchdog Status and Control Register Low 686 #define WDOG_STCTRLL *(volatile uint16_t *)0x40052002 // Watchdog Status and Control Register Low
687 #define WDOG_TOVALH *(volatile uint16_t *)0x40052004 // Watchdog Time-out Value Register High 687 #define WDOG_TOVALH *(volatile uint16_t *)0x40052004 // Watchdog Time-out Value Register High
688 #define WDOG_TOVALL *(volatile uint16_t *)0x40052006 // Watchdog Time-out Value Register Low 688 #define WDOG_TOVALL *(volatile uint16_t *)0x40052006 // Watchdog Time-out Value Register Low
689 #define WDOG_WINH *(volatile uint16_t *)0x40052008 // Watchdog Window Register High 689 #define WDOG_WINH *(volatile uint16_t *)0x40052008 // Watchdog Window Register High
690 #define WDOG_WINL *(volatile uint16_t *)0x4005200A // Watchdog Window Register Low 690 #define WDOG_WINL *(volatile uint16_t *)0x4005200A // Watchdog Window Register Low
691 #define WDOG_REFRESH *(volatile uint16_t *)0x4005200C // Watchdog Refresh register 691 #define WDOG_REFRESH *(volatile uint16_t *)0x4005200C // Watchdog Refresh register
692 #define WDOG_UNLOCK *(volatile uint16_t *)0x4005200E // Watchdog Unlock register 692 #define WDOG_UNLOCK *(volatile uint16_t *)0x4005200E // Watchdog Unlock register
693 #define WDOG_UNLOCK_SEQ1 (uint16_t)0xC520 693 #define WDOG_UNLOCK_SEQ1 (uint16_t)0xC520
694 #define WDOG_UNLOCK_SEQ2 (uint16_t)0xD928 694 #define WDOG_UNLOCK_SEQ2 (uint16_t)0xD928
695 #define WDOG_TMROUTH *(volatile uint16_t *)0x40052010 // Watchdog Timer Output Register High 695 #define WDOG_TMROUTH *(volatile uint16_t *)0x40052010 // Watchdog Timer Output Register High
696 #define WDOG_TMROUTL *(volatile uint16_t *)0x40052012 // Watchdog Timer Output Register Low 696 #define WDOG_TMROUTL *(volatile uint16_t *)0x40052012 // Watchdog Timer Output Register Low
697 #define WDOG_RSTCNT *(volatile uint16_t *)0x40052014 // Watchdog Reset Count register 697 #define WDOG_RSTCNT *(volatile uint16_t *)0x40052014 // Watchdog Reset Count register
698 #define WDOG_PRESC *(volatile uint16_t *)0x40052016 // Watchdog Prescaler register 698 #define WDOG_PRESC *(volatile uint16_t *)0x40052016 // Watchdog Prescaler register
699 699
700 // Chapter 24: Multipurpose Clock Generator (MCG) 700 // Chapter 24: Multipurpose Clock Generator (MCG)
701 #define MCG_C1 *(volatile uint8_t *)0x40064000 // MCG Control 1 Register 701 #define MCG_C1 *(volatile uint8_t *)0x40064000 // MCG Control 1 Register
702 #define MCG_C1_IREFSTEN (uint8_t)0x01 // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. 702 #define MCG_C1_IREFSTEN (uint8_t)0x01 // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
703 #define MCG_C1_IRCLKEN (uint8_t)0x02 // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK. 703 #define MCG_C1_IRCLKEN (uint8_t)0x02 // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.
704 #define MCG_C1_IREFS (uint8_t)0x04 // Internal Reference Select, Selects the reference clock source for the FLL. 704 #define MCG_C1_IREFS (uint8_t)0x04 // Internal Reference Select, Selects the reference clock source for the FLL.
705 #define MCG_C1_FRDIV(n) (uint8_t)(((n) & 0x07) << 3) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL 705 #define MCG_C1_FRDIV(n) (uint8_t)(((n) & 0x07) << 3) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL
706 #define MCG_C1_CLKS(n) (uint8_t)(((n) & 0x03) << 6) // Clock Source Select, Selects the clock source for MCGOUTCLK 706 #define MCG_C1_CLKS(n) (uint8_t)(((n) & 0x03) << 6) // Clock Source Select, Selects the clock source for MCGOUTCLK
707 #define MCG_C2 *(volatile uint8_t *)0x40064001 // MCG Control 2 Register 707 #define MCG_C2 *(volatile uint8_t *)0x40064001 // MCG Control 2 Register
708 #define MCG_C2_IRCS (uint8_t)0x01 // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source. 708 #define MCG_C2_IRCS (uint8_t)0x01 // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.
709 #define MCG_C2_LP (uint8_t)0x02 // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. 709 #define MCG_C2_LP (uint8_t)0x02 // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.
710 #define MCG_C2_EREFS (uint8_t)0x04 // External Reference Select, Selects the source for the external reference clock. 710 #define MCG_C2_EREFS (uint8_t)0x04 // External Reference Select, Selects the source for the external reference clock.
711 #define MCG_C2_HGO0 (uint8_t)0x08 // High Gain Oscillator Select, Controls the crystal oscillator mode of operation 711 #define MCG_C2_HGO0 (uint8_t)0x08 // High Gain Oscillator Select, Controls the crystal oscillator mode of operation
712 #define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator 712 #define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
713 #define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 713 #define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
714 #define MCG_C3 *(volatile uint8_t *)0x40064002 // MCG Control 3 Register 714 #define MCG_C3 *(volatile uint8_t *)0x40064002 // MCG Control 3 Register
715 #define MCG_C3_SCTRIM(n) (uint8_t)(n) // Slow Internal Reference Clock Trim Setting 715 #define MCG_C3_SCTRIM(n) (uint8_t)(n) // Slow Internal Reference Clock Trim Setting
716 #define MCG_C4 *(volatile uint8_t *)0x40064003 // MCG Control 4 Register 716 #define MCG_C4 *(volatile uint8_t *)0x40064003 // MCG Control 4 Register
717 #define MCG_C4_SCFTRIM (uint8_t)0x01 // Slow Internal Reference Clock Fine Trim 717 #define MCG_C4_SCFTRIM (uint8_t)0x01 // Slow Internal Reference Clock Fine Trim
718 #define MCG_C4_FCTRIM(n) (uint8_t)(((n) & 0x0F) << 1) // Fast Internal Reference Clock Trim Setting 718 #define MCG_C4_FCTRIM(n) (uint8_t)(((n) & 0x0F) << 1) // Fast Internal Reference Clock Trim Setting
719 #define MCG_C4_DRST_DRS(n) (uint8_t)(((n) & 0x03) << 5) // DCO Range Select 719 #define MCG_C4_DRST_DRS(n) (uint8_t)(((n) & 0x03) << 5) // DCO Range Select
720 #define MCG_C4_DMX32 (uint8_t)0x80 // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed 720 #define MCG_C4_DMX32 (uint8_t)0x80 // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed
721 #define MCG_C5 *(volatile uint8_t *)0x40064004 // MCG Control 5 Register 721 #define MCG_C5 *(volatile uint8_t *)0x40064004 // MCG Control 5 Register
722 #define MCG_C5_PRDIV0(n) (uint8_t)((n) & 0x1F) // PLL External Reference Divider 722 #define MCG_C5_PRDIV0(n) (uint8_t)((n) & 0x1F) // PLL External Reference Divider
723 #define MCG_C5_PLLSTEN0 (uint8_t)0x20 // PLL Stop Enable 723 #define MCG_C5_PLLSTEN0 (uint8_t)0x20 // PLL Stop Enable
724 #define MCG_C5_PLLCLKEN0 (uint8_t)0x40 // PLL Clock Enable 724 #define MCG_C5_PLLCLKEN0 (uint8_t)0x40 // PLL Clock Enable
725 #define MCG_C6 *(volatile uint8_t *)0x40064005 // MCG Control 6 Register 725 #define MCG_C6 *(volatile uint8_t *)0x40064005 // MCG Control 6 Register
726 #define MCG_C6_VDIV0(n) (uint8_t)((n) & 0x1F) // VCO 0 Divider 726 #define MCG_C6_VDIV0(n) (uint8_t)((n) & 0x1F) // VCO 0 Divider
727 #define MCG_C6_CME0 (uint8_t)0x20 // Clock Monitor Enable 727 #define MCG_C6_CME0 (uint8_t)0x20 // Clock Monitor Enable
728 #define MCG_C6_PLLS (uint8_t)0x40 // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. 728 #define MCG_C6_PLLS (uint8_t)0x40 // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00.
729 #define MCG_C6_LOLIE0 (uint8_t)0x80 // Loss of Lock Interrrupt Enable 729 #define MCG_C6_LOLIE0 (uint8_t)0x80 // Loss of Lock Interrrupt Enable
730 #define MCG_S *(volatile uint8_t *)0x40064006 // MCG Status Register 730 #define MCG_S *(volatile uint8_t *)0x40064006 // MCG Status Register
731 #define MCG_S_IRCST (uint8_t)0x01 // Internal Reference Clock Status 731 #define MCG_S_IRCST (uint8_t)0x01 // Internal Reference Clock Status
732 #define MCG_S_OSCINIT0 (uint8_t)0x02 // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator 732 #define MCG_S_OSCINIT0 (uint8_t)0x02 // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator
733 #define MCG_S_CLKST(n) (uint8_t)(((n) & 0x03) << 2) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL 733 #define MCG_S_CLKST(n) (uint8_t)(((n) & 0x03) << 2) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL
734 #define MCG_S_CLKST_MASK (uint8_t)0x0C 734 #define MCG_S_CLKST_MASK (uint8_t)0x0C
735 #define MCG_S_IREFST (uint8_t)0x10 // Internal Reference Status 735 #define MCG_S_IREFST (uint8_t)0x10 // Internal Reference Status
736 #define MCG_S_PLLST (uint8_t)0x20 // PLL Select Status 736 #define MCG_S_PLLST (uint8_t)0x20 // PLL Select Status
737 #define MCG_S_LOCK0 (uint8_t)0x40 // Lock Status, 0=PLL Unlocked, 1=PLL Locked 737 #define MCG_S_LOCK0 (uint8_t)0x40 // Lock Status, 0=PLL Unlocked, 1=PLL Locked
738 #define MCG_S_LOLS0 (uint8_t)0x80 // Loss of Lock Status 738 #define MCG_S_LOLS0 (uint8_t)0x80 // Loss of Lock Status
739 #define MCG_SC *(volatile uint8_t *)0x40064008 // MCG Status and Control Register 739 #define MCG_SC *(volatile uint8_t *)0x40064008 // MCG Status and Control Register
740 #define MCG_SC_LOCS0 (uint8_t)0x01 // OSC0 Loss of Clock Status 740 #define MCG_SC_LOCS0 (uint8_t)0x01 // OSC0 Loss of Clock Status
741 #define MCG_SC_FCRDIV(n) (uint8_t)(((n) & 0x07) << 1) // Fast Clock Internal Reference Divider 741 #define MCG_SC_FCRDIV(n) (uint8_t)(((n) & 0x07) << 1) // Fast Clock Internal Reference Divider
742 #define MCG_SC_FLTPRSRV (uint8_t)0x10 // FLL Filter Preserve Enable 742 #define MCG_SC_FLTPRSRV (uint8_t)0x10 // FLL Filter Preserve Enable
743 #define MCG_SC_ATMF (uint8_t)0x20 // Automatic Trim Machine Fail Flag 743 #define MCG_SC_ATMF (uint8_t)0x20 // Automatic Trim Machine Fail Flag
744 #define MCG_SC_ATMS (uint8_t)0x40 // Automatic Trim Machine Select 744 #define MCG_SC_ATMS (uint8_t)0x40 // Automatic Trim Machine Select
745 #define MCG_SC_ATME (uint8_t)0x80 // Automatic Trim Machine Enable 745 #define MCG_SC_ATME (uint8_t)0x80 // Automatic Trim Machine Enable
746 #define MCG_ATCVH *(volatile uint8_t *)0x4006400A // MCG Auto Trim Compare Value High Register 746 #define MCG_ATCVH *(volatile uint8_t *)0x4006400A // MCG Auto Trim Compare Value High Register
747 #define MCG_ATCVL *(volatile uint8_t *)0x4006400B // MCG Auto Trim Compare Value Low Register 747 #define MCG_ATCVL *(volatile uint8_t *)0x4006400B // MCG Auto Trim Compare Value Low Register
748 #define MCG_C7 *(volatile uint8_t *)0x4006400C // MCG Control 7 Register 748 #define MCG_C7 *(volatile uint8_t *)0x4006400C // MCG Control 7 Register
749 #define MCG_C8 *(volatile uint8_t *)0x4006400D // MCG Control 8 Register 749 #define MCG_C8 *(volatile uint8_t *)0x4006400D // MCG Control 8 Register
750 750
751 // Chapter 25: Oscillator (OSC) 751 // Chapter 25: Oscillator (OSC)
752 #define OSC0_CR *(volatile uint8_t *)0x40065000 // OSC Control Register 752 #define OSC0_CR *(volatile uint8_t *)0x40065000 // OSC Control Register
753 #define OSC_SC16P (uint8_t)0x01 // Oscillator 16 pF Capacitor Load Configure 753 #define OSC_SC16P (uint8_t)0x01 // Oscillator 16 pF Capacitor Load Configure
754 #define OSC_SC8P (uint8_t)0x02 // Oscillator 8 pF Capacitor Load Configure 754 #define OSC_SC8P (uint8_t)0x02 // Oscillator 8 pF Capacitor Load Configure
755 #define OSC_SC4P (uint8_t)0x04 // Oscillator 4 pF Capacitor Load Configure 755 #define OSC_SC4P (uint8_t)0x04 // Oscillator 4 pF Capacitor Load Configure
756 #define OSC_SC2P (uint8_t)0x08 // Oscillator 2 pF Capacitor Load Configure 756 #define OSC_SC2P (uint8_t)0x08 // Oscillator 2 pF Capacitor Load Configure
757 #define OSC_EREFSTEN (uint8_t)0x20 // External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. 757 #define OSC_EREFSTEN (uint8_t)0x20 // External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.
758 #define OSC_ERCLKEN (uint8_t)0x80 // External Reference Enable, Enables external reference clock (OSCERCLK). 758 #define OSC_ERCLKEN (uint8_t)0x80 // External Reference Enable, Enables external reference clock (OSCERCLK).
759 759
760 // Chapter 27: Flash Memory Controller (FMC) 760 // Chapter 27: Flash Memory Controller (FMC)
761 #define FMC_PFAPR *(volatile uint32_t *)0x4001F000 // Flash Access Protection 761 #define FMC_PFAPR *(volatile uint32_t *)0x4001F000 // Flash Access Protection
762 #define FMC_PFB0CR *(volatile uint32_t *)0x4001F004 // Flash Control 762 #define FMC_PFB0CR *(volatile uint32_t *)0x4001F004 // Flash Control
763 #define FMC_TAGVDW0S0 *(volatile uint32_t *)0x4001F100 // Cache Tag Storage 763 #define FMC_TAGVDW0S0 *(volatile uint32_t *)0x4001F100 // Cache Tag Storage
764 #define FMC_TAGVDW0S1 *(volatile uint32_t *)0x4001F104 // Cache Tag Storage 764 #define FMC_TAGVDW0S1 *(volatile uint32_t *)0x4001F104 // Cache Tag Storage
765 #define FMC_TAGVDW1S0 *(volatile uint32_t *)0x4001F108 // Cache Tag Storage 765 #define FMC_TAGVDW1S0 *(volatile uint32_t *)0x4001F108 // Cache Tag Storage
766 #define FMC_TAGVDW1S1 *(volatile uint32_t *)0x4001F10C // Cache Tag Storage 766 #define FMC_TAGVDW1S1 *(volatile uint32_t *)0x4001F10C // Cache Tag Storage
767 #define FMC_TAGVDW2S0 *(volatile uint32_t *)0x4001F110 // Cache Tag Storage 767 #define FMC_TAGVDW2S0 *(volatile uint32_t *)0x4001F110 // Cache Tag Storage
768 #define FMC_TAGVDW2S1 *(volatile uint32_t *)0x4001F114 // Cache Tag Storage 768 #define FMC_TAGVDW2S1 *(volatile uint32_t *)0x4001F114 // Cache Tag Storage
769 #define FMC_TAGVDW3S0 *(volatile uint32_t *)0x4001F118 // Cache Tag Storage 769 #define FMC_TAGVDW3S0 *(volatile uint32_t *)0x4001F118 // Cache Tag Storage
770 #define FMC_TAGVDW3S1 *(volatile uint32_t *)0x4001F11C // Cache Tag Storage 770 #define FMC_TAGVDW3S1 *(volatile uint32_t *)0x4001F11C // Cache Tag Storage
771 #define FMC_DATAW0S0 *(volatile uint32_t *)0x4001F200 // Cache Data Storage 771 #define FMC_DATAW0S0 *(volatile uint32_t *)0x4001F200 // Cache Data Storage
772 #define FMC_DATAW0S1 *(volatile uint32_t *)0x4001F204 // Cache Data Storage 772 #define FMC_DATAW0S1 *(volatile uint32_t *)0x4001F204 // Cache Data Storage
773 #define FMC_DATAW1S0 *(volatile uint32_t *)0x4001F208 // Cache Data Storage 773 #define FMC_DATAW1S0 *(volatile uint32_t *)0x4001F208 // Cache Data Storage
774 #define FMC_DATAW1S1 *(volatile uint32_t *)0x4001F20C // Cache Data Storage 774 #define FMC_DATAW1S1 *(volatile uint32_t *)0x4001F20C // Cache Data Storage
775 #define FMC_DATAW2S0 *(volatile uint32_t *)0x4001F210 // Cache Data Storage 775 #define FMC_DATAW2S0 *(volatile uint32_t *)0x4001F210 // Cache Data Storage
776 #define FMC_DATAW2S1 *(volatile uint32_t *)0x4001F214 // Cache Data Storage 776 #define FMC_DATAW2S1 *(volatile uint32_t *)0x4001F214 // Cache Data Storage
777 #define FMC_DATAW3S0 *(volatile uint32_t *)0x4001F218 // Cache Data Storage 777 #define FMC_DATAW3S0 *(volatile uint32_t *)0x4001F218 // Cache Data Storage
778 #define FMC_DATAW3S1 *(volatile uint32_t *)0x4001F21C // Cache Data Storage 778 #define FMC_DATAW3S1 *(volatile uint32_t *)0x4001F21C // Cache Data Storage
779 779
780 // Chapter 28: Flash Memory Module (FTFL) 780 // Chapter 28: Flash Memory Module (FTFL)
781 #define FTFL_FSTAT *(volatile uint8_t *)0x40020000 // Flash Status Register 781 #define FTFL_FSTAT *(volatile uint8_t *)0x40020000 // Flash Status Register
782 #define FTFL_FSTAT_CCIF (uint8_t)0x80 // Command Complete Interrupt Flag 782 #define FTFL_FSTAT_CCIF (uint8_t)0x80 // Command Complete Interrupt Flag
783 #define FTFL_FSTAT_RDCOLERR (uint8_t)0x40 // Flash Read Collision Error Flag 783 #define FTFL_FSTAT_RDCOLERR (uint8_t)0x40 // Flash Read Collision Error Flag
784 #define FTFL_FSTAT_ACCERR (uint8_t)0x20 // Flash Access Error Flag 784 #define FTFL_FSTAT_ACCERR (uint8_t)0x20 // Flash Access Error Flag
785 #define FTFL_FSTAT_FPVIOL (uint8_t)0x10 // Flash Protection Violation Flag 785 #define FTFL_FSTAT_FPVIOL (uint8_t)0x10 // Flash Protection Violation Flag
786 #define FTFL_FSTAT_MGSTAT0 (uint8_t)0x01 // Memory Controller Command Completion Status Flag 786 #define FTFL_FSTAT_MGSTAT0 (uint8_t)0x01 // Memory Controller Command Completion Status Flag
787 #define FTFL_FCNFG *(volatile uint8_t *)0x40020001 // Flash Configuration Register 787 #define FTFL_FCNFG *(volatile uint8_t *)0x40020001 // Flash Configuration Register
788 #define FTFL_FCNFG_CCIE (uint8_t)0x80 // Command Complete Interrupt Enable 788 #define FTFL_FCNFG_CCIE (uint8_t)0x80 // Command Complete Interrupt Enable
789 #define FTFL_FCNFG_RDCOLLIE (uint8_t)0x40 // Read Collision Error Interrupt Enable 789 #define FTFL_FCNFG_RDCOLLIE (uint8_t)0x40 // Read Collision Error Interrupt Enable
790 #define FTFL_FCNFG_ERSAREQ (uint8_t)0x20 // Erase All Request 790 #define FTFL_FCNFG_ERSAREQ (uint8_t)0x20 // Erase All Request
791 #define FTFL_FCNFG_ERSSUSP (uint8_t)0x10 // Erase Suspend 791 #define FTFL_FCNFG_ERSSUSP (uint8_t)0x10 // Erase Suspend
792 #define FTFL_FCNFG_PFLSH (uint8_t)0x04 // Flash memory configuration 792 #define FTFL_FCNFG_PFLSH (uint8_t)0x04 // Flash memory configuration
793 #define FTFL_FCNFG_RAMRDY (uint8_t)0x02 // RAM Ready 793 #define FTFL_FCNFG_RAMRDY (uint8_t)0x02 // RAM Ready
794 #define FTFL_FCNFG_EEERDY (uint8_t)0x01 // EEPROM Ready 794 #define FTFL_FCNFG_EEERDY (uint8_t)0x01 // EEPROM Ready
795 #define FTFL_FSEC *(const uint8_t *)0x40020002 // Flash Security Register 795 #define FTFL_FSEC *(const uint8_t *)0x40020002 // Flash Security Register
796 #define FTFL_FOPT *(const uint8_t *)0x40020003 // Flash Option Register 796 #define FTFL_FOPT *(const uint8_t *)0x40020003 // Flash Option Register
797 #define FTFL_FCCOB3 *(volatile uint8_t *)0x40020004 // Flash Common Command Object Registers 797 #define FTFL_FCCOB3 *(volatile uint8_t *)0x40020004 // Flash Common Command Object Registers
798 #define FTFL_FCCOB2 *(volatile uint8_t *)0x40020005 798 #define FTFL_FCCOB2 *(volatile uint8_t *)0x40020005
799 #define FTFL_FCCOB1 *(volatile uint8_t *)0x40020006 799 #define FTFL_FCCOB1 *(volatile uint8_t *)0x40020006
819 #define CRC_CTRL *(volatile uint32_t *)0x40032008 // CRC Control register 819 #define CRC_CTRL *(volatile uint32_t *)0x40032008 // CRC Control register
820 820
821 // Chapter 31: Analog-to-Digital Converter (ADC) 821 // Chapter 31: Analog-to-Digital Converter (ADC)
822 #define ADC0_SC1A *(volatile uint32_t *)0x4003B000 // ADC status and control registers 1 822 #define ADC0_SC1A *(volatile uint32_t *)0x4003B000 // ADC status and control registers 1
823 #define ADC0_SC1B *(volatile uint32_t *)0x4003B004 // ADC status and control registers 1 823 #define ADC0_SC1B *(volatile uint32_t *)0x4003B004 // ADC status and control registers 1
824 #define ADC_SC1_COCO (uint32_t)0x80 // Conversion complete flag 824 #define ADC_SC1_COCO (uint32_t)0x80 // Conversion complete flag
825 #define ADC_SC1_AIEN (uint32_t)0x40 // Interrupt enable 825 #define ADC_SC1_AIEN (uint32_t)0x40 // Interrupt enable
826 #define ADC_SC1_DIFF (uint32_t)0x20 // Differential mode enable 826 #define ADC_SC1_DIFF (uint32_t)0x20 // Differential mode enable
827 #define ADC_SC1_ADCH(n) (uint32_t)((n) & 0x1F) // Input channel select 827 #define ADC_SC1_ADCH(n) (uint32_t)((n) & 0x1F) // Input channel select
828 #define ADC0_CFG1 *(volatile uint32_t *)0x4003B008 // ADC configuration register 1 828 #define ADC0_CFG1 *(volatile uint32_t *)0x4003B008 // ADC configuration register 1
829 #define ADC_CFG1_ADLPC (uint32_t)0x80 // Low-power configuration 829 #define ADC_CFG1_ADLPC (uint32_t)0x80 // Low-power configuration
830 #define ADC_CFG1_ADIV(n) (uint32_t)(((n) & 3) << 5) // Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8 830 #define ADC_CFG1_ADIV(n) (uint32_t)(((n) & 3) << 5) // Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8
831 #define ADC_CFG1_ADLSMP (uint32_t)0x10 // Sample time configuration, 0=Short, 1=Long 831 #define ADC_CFG1_ADLSMP (uint32_t)0x10 // Sample time configuration, 0=Short, 1=Long
832 #define ADC_CFG1_MODE(n) (uint32_t)(((n) & 3) << 2) // Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit 832 #define ADC_CFG1_MODE(n) (uint32_t)(((n) & 3) << 2) // Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit
833 #define ADC_CFG1_ADICLK(n) (uint32_t)(((n) & 3) << 0) // Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async 833 #define ADC_CFG1_ADICLK(n) (uint32_t)(((n) & 3) << 0) // Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async
834 #define ADC0_CFG2 *(volatile uint32_t *)0x4003B00C // Configuration register 2 834 #define ADC0_CFG2 *(volatile uint32_t *)0x4003B00C // Configuration register 2
835 #define ADC_CFG2_MUXSEL (uint32_t)0x10 // 0=a channels, 1=b channels 835 #define ADC_CFG2_MUXSEL (uint32_t)0x10 // 0=a channels, 1=b channels
836 #define ADC_CFG2_ADACKEN (uint32_t)0x08 // async clock enable 836 #define ADC_CFG2_ADACKEN (uint32_t)0x08 // async clock enable
837 #define ADC_CFG2_ADHSC (uint32_t)0x04 // High speed configuration 837 #define ADC_CFG2_ADHSC (uint32_t)0x04 // High speed configuration
838 #define ADC_CFG2_ADLSTS(n) (uint32_t)(((n) & 3) << 0) // Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles 838 #define ADC_CFG2_ADLSTS(n) (uint32_t)(((n) & 3) << 0) // Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles
839 #define ADC0_RA *(volatile uint32_t *)0x4003B010 // ADC data result register 839 #define ADC0_RA *(volatile uint32_t *)0x4003B010 // ADC data result register
840 #define ADC0_RB *(volatile uint32_t *)0x4003B014 // ADC data result register 840 #define ADC0_RB *(volatile uint32_t *)0x4003B014 // ADC data result register
841 #define ADC0_CV1 *(volatile uint32_t *)0x4003B018 // Compare value registers 841 #define ADC0_CV1 *(volatile uint32_t *)0x4003B018 // Compare value registers
842 #define ADC0_CV2 *(volatile uint32_t *)0x4003B01C // Compare value registers 842 #define ADC0_CV2 *(volatile uint32_t *)0x4003B01C // Compare value registers
843 #define ADC0_SC2 *(volatile uint32_t *)0x4003B020 // Status and control register 2 843 #define ADC0_SC2 *(volatile uint32_t *)0x4003B020 // Status and control register 2
844 #define ADC_SC2_ADACT (uint32_t)0x80 // Conversion active 844 #define ADC_SC2_ADACT (uint32_t)0x80 // Conversion active
845 #define ADC_SC2_ADTRG (uint32_t)0x40 // Conversion trigger select, 0=software, 1=hardware 845 #define ADC_SC2_ADTRG (uint32_t)0x40 // Conversion trigger select, 0=software, 1=hardware
846 #define ADC_SC2_ACFE (uint32_t)0x20 // Compare function enable 846 #define ADC_SC2_ACFE (uint32_t)0x20 // Compare function enable
847 #define ADC_SC2_ACFGT (uint32_t)0x10 // Compare function greater than enable 847 #define ADC_SC2_ACFGT (uint32_t)0x10 // Compare function greater than enable
848 #define ADC_SC2_ACREN (uint32_t)0x08 // Compare function range enable 848 #define ADC_SC2_ACREN (uint32_t)0x08 // Compare function range enable
849 #define ADC_SC2_DMAEN (uint32_t)0x04 // DMA enable 849 #define ADC_SC2_DMAEN (uint32_t)0x04 // DMA enable
850 #define ADC_SC2_REFSEL(n) (uint32_t)(((n) & 3) << 0) // Voltage reference, 0=vcc/external, 1=1.2 volts 850 #define ADC_SC2_REFSEL(n) (uint32_t)(((n) & 3) << 0) // Voltage reference, 0=vcc/external, 1=1.2 volts
851 #define ADC0_SC3 *(volatile uint32_t *)0x4003B024 // Status and control register 3 851 #define ADC0_SC3 *(volatile uint32_t *)0x4003B024 // Status and control register 3
852 #define ADC_SC3_CAL (uint32_t)0x80 // Calibration, 1=begin, stays set while cal in progress 852 #define ADC_SC3_CAL (uint32_t)0x80 // Calibration, 1=begin, stays set while cal in progress
853 #define ADC_SC3_CALF (uint32_t)0x40 // Calibration failed flag 853 #define ADC_SC3_CALF (uint32_t)0x40 // Calibration failed flag
854 #define ADC_SC3_ADCO (uint32_t)0x08 // Continuous conversion enable 854 #define ADC_SC3_ADCO (uint32_t)0x08 // Continuous conversion enable
855 #define ADC_SC3_AVGE (uint32_t)0x04 // Hardware average enable 855 #define ADC_SC3_AVGE (uint32_t)0x04 // Hardware average enable
856 #define ADC_SC3_AVGS(n) (uint32_t)(((n) & 3) << 0) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples 856 #define ADC_SC3_AVGS(n) (uint32_t)(((n) & 3) << 0) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples
857 #define ADC0_OFS *(volatile uint32_t *)0x4003B028 // ADC offset correction register 857 #define ADC0_OFS *(volatile uint32_t *)0x4003B028 // ADC offset correction register
858 #define ADC0_PG *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register 858 #define ADC0_PG *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register
859 #define ADC0_MG *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register 859 #define ADC0_MG *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register
860 #define ADC0_CLPD *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register 860 #define ADC0_CLPD *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register
861 #define ADC0_CLPS *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register 861 #define ADC0_CLPS *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register
862 #define ADC0_CLP4 *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register 862 #define ADC0_CLP4 *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register
863 #define ADC0_CLP3 *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register 863 #define ADC0_CLP3 *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register
864 #define ADC0_CLP2 *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register 864 #define ADC0_CLP2 *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register
865 #define ADC0_CLP1 *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register 865 #define ADC0_CLP1 *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register
866 #define ADC0_CLP0 *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register 866 #define ADC0_CLP0 *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register
867 #define ADC0_CLMD *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register 867 #define ADC0_CLMD *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register
868 #define ADC0_CLMS *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register 868 #define ADC0_CLMS *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register
869 #define ADC0_CLM4 *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register 869 #define ADC0_CLM4 *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register
870 #define ADC0_CLM3 *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register 870 #define ADC0_CLM3 *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register
871 #define ADC0_CLM2 *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register 871 #define ADC0_CLM2 *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register
872 #define ADC0_CLM1 *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register 872 #define ADC0_CLM1 *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register
873 #define ADC0_CLM0 *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register 873 #define ADC0_CLM0 *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register
874 874
875 #define ADC1_SC1A *(volatile uint32_t *)0x400BB000 // ADC status and control registers 1 875 #define ADC1_SC1A *(volatile uint32_t *)0x400BB000 // ADC status and control registers 1
876 #define ADC1_SC1B *(volatile uint32_t *)0x400BB004 // ADC status and control registers 1 876 #define ADC1_SC1B *(volatile uint32_t *)0x400BB004 // ADC status and control registers 1
877 #define ADC1_CFG1 *(volatile uint32_t *)0x400BB008 // ADC configuration register 1 877 #define ADC1_CFG1 *(volatile uint32_t *)0x400BB008 // ADC configuration register 1
878 #define ADC1_CFG2 *(volatile uint32_t *)0x400BB00C // Configuration register 2 878 #define ADC1_CFG2 *(volatile uint32_t *)0x400BB00C // Configuration register 2
879 #define ADC1_RA *(volatile uint32_t *)0x400BB010 // ADC data result register 879 #define ADC1_RA *(volatile uint32_t *)0x400BB010 // ADC data result register
880 #define ADC1_RB *(volatile uint32_t *)0x400BB014 // ADC data result register 880 #define ADC1_RB *(volatile uint32_t *)0x400BB014 // ADC data result register
881 #define ADC1_CV1 *(volatile uint32_t *)0x400BB018 // Compare value registers 881 #define ADC1_CV1 *(volatile uint32_t *)0x400BB018 // Compare value registers
882 #define ADC1_CV2 *(volatile uint32_t *)0x400BB01C // Compare value registers 882 #define ADC1_CV2 *(volatile uint32_t *)0x400BB01C // Compare value registers
883 #define ADC1_SC2 *(volatile uint32_t *)0x400BB020 // Status and control register 2 883 #define ADC1_SC2 *(volatile uint32_t *)0x400BB020 // Status and control register 2
884 #define ADC1_SC3 *(volatile uint32_t *)0x400BB024 // Status and control register 3 884 #define ADC1_SC3 *(volatile uint32_t *)0x400BB024 // Status and control register 3
885 #define ADC1_OFS *(volatile uint32_t *)0x400BB028 // ADC offset correction register 885 #define ADC1_OFS *(volatile uint32_t *)0x400BB028 // ADC offset correction register
886 #define ADC1_PG *(volatile uint32_t *)0x400BB02C // ADC plus-side gain register 886 #define ADC1_PG *(volatile uint32_t *)0x400BB02C // ADC plus-side gain register
887 #define ADC1_MG *(volatile uint32_t *)0x400BB030 // ADC minus-side gain register 887 #define ADC1_MG *(volatile uint32_t *)0x400BB030 // ADC minus-side gain register
888 #define ADC1_CLPD *(volatile uint32_t *)0x400BB034 // ADC plus-side general calibration value register 888 #define ADC1_CLPD *(volatile uint32_t *)0x400BB034 // ADC plus-side general calibration value register
889 #define ADC1_CLPS *(volatile uint32_t *)0x400BB038 // ADC plus-side general calibration value register 889 #define ADC1_CLPS *(volatile uint32_t *)0x400BB038 // ADC plus-side general calibration value register
890 #define ADC1_CLP4 *(volatile uint32_t *)0x400BB03C // ADC plus-side general calibration value register 890 #define ADC1_CLP4 *(volatile uint32_t *)0x400BB03C // ADC plus-side general calibration value register
891 #define ADC1_CLP3 *(volatile uint32_t *)0x400BB040 // ADC plus-side general calibration value register 891 #define ADC1_CLP3 *(volatile uint32_t *)0x400BB040 // ADC plus-side general calibration value register
892 #define ADC1_CLP2 *(volatile uint32_t *)0x400BB044 // ADC plus-side general calibration value register 892 #define ADC1_CLP2 *(volatile uint32_t *)0x400BB044 // ADC plus-side general calibration value register
893 #define ADC1_CLP1 *(volatile uint32_t *)0x400BB048 // ADC plus-side general calibration value register 893 #define ADC1_CLP1 *(volatile uint32_t *)0x400BB048 // ADC plus-side general calibration value register
894 #define ADC1_CLP0 *(volatile uint32_t *)0x400BB04C // ADC plus-side general calibration value register 894 #define ADC1_CLP0 *(volatile uint32_t *)0x400BB04C // ADC plus-side general calibration value register
895 #define ADC1_CLMD *(volatile uint32_t *)0x400BB054 // ADC minus-side general calibration value register 895 #define ADC1_CLMD *(volatile uint32_t *)0x400BB054 // ADC minus-side general calibration value register
896 #define ADC1_CLMS *(volatile uint32_t *)0x400BB058 // ADC minus-side general calibration value register 896 #define ADC1_CLMS *(volatile uint32_t *)0x400BB058 // ADC minus-side general calibration value register
897 #define ADC1_CLM4 *(volatile uint32_t *)0x400BB05C // ADC minus-side general calibration value register 897 #define ADC1_CLM4 *(volatile uint32_t *)0x400BB05C // ADC minus-side general calibration value register
898 #define ADC1_CLM3 *(volatile uint32_t *)0x400BB060 // ADC minus-side general calibration value register 898 #define ADC1_CLM3 *(volatile uint32_t *)0x400BB060 // ADC minus-side general calibration value register
899 #define ADC1_CLM2 *(volatile uint32_t *)0x400BB064 // ADC minus-side general calibration value register 899 #define ADC1_CLM2 *(volatile uint32_t *)0x400BB064 // ADC minus-side general calibration value register
900 #define ADC1_CLM1 *(volatile uint32_t *)0x400BB068 // ADC minus-side general calibration value register 900 #define ADC1_CLM1 *(volatile uint32_t *)0x400BB068 // ADC minus-side general calibration value register
901 #define ADC1_CLM0 *(volatile uint32_t *)0x400BB06C // ADC minus-side general calibration value register 901 #define ADC1_CLM0 *(volatile uint32_t *)0x400BB06C // ADC minus-side general calibration value register
902 902
903 #define DAC0_DAT0L *(volatile uint8_t *)0x400CC000 // DAC Data Low Register 903 #define DAC0_DAT0L *(volatile uint8_t *)0x400CC000 // DAC Data Low Register
904 #define DAC0_DATH *(volatile uint8_t *)0x400CC001 // DAC Data High Register 904 #define DAC0_DATH *(volatile uint8_t *)0x400CC001 // DAC Data High Register
905 #define DAC0_DAT1L *(volatile uint8_t *)0x400CC002 // DAC Data Low Register 905 #define DAC0_DAT1L *(volatile uint8_t *)0x400CC002 // DAC Data Low Register
906 #define DAC0_DAT2L *(volatile uint8_t *)0x400CC004 // DAC Data Low Register 906 #define DAC0_DAT2L *(volatile uint8_t *)0x400CC004 // DAC Data Low Register
907 #define DAC0_DAT3L *(volatile uint8_t *)0x400CC006 // DAC Data Low Register 907 #define DAC0_DAT3L *(volatile uint8_t *)0x400CC006 // DAC Data Low Register
908 #define DAC0_DAT4L *(volatile uint8_t *)0x400CC008 // DAC Data Low Register 908 #define DAC0_DAT4L *(volatile uint8_t *)0x400CC008 // DAC Data Low Register
909 #define DAC0_DAT5L *(volatile uint8_t *)0x400CC00A // DAC Data Low Register 909 #define DAC0_DAT5L *(volatile uint8_t *)0x400CC00A // DAC Data Low Register
910 #define DAC0_DAT6L *(volatile uint8_t *)0x400CC00C // DAC Data Low Register 910 #define DAC0_DAT6L *(volatile uint8_t *)0x400CC00C // DAC Data Low Register
911 #define DAC0_DAT7L *(volatile uint8_t *)0x400CC00E // DAC Data Low Register 911 #define DAC0_DAT7L *(volatile uint8_t *)0x400CC00E // DAC Data Low Register
912 #define DAC0_DAT8L *(volatile uint8_t *)0x400CC010 // DAC Data Low Register 912 #define DAC0_DAT8L *(volatile uint8_t *)0x400CC010 // DAC Data Low Register
913 #define DAC0_DAT9L *(volatile uint8_t *)0x400CC012 // DAC Data Low Register 913 #define DAC0_DAT9L *(volatile uint8_t *)0x400CC012 // DAC Data Low Register
914 #define DAC0_DAT10L *(volatile uint8_t *)0x400CC014 // DAC Data Low Register 914 #define DAC0_DAT10L *(volatile uint8_t *)0x400CC014 // DAC Data Low Register
915 #define DAC0_DAT11L *(volatile uint8_t *)0x400CC016 // DAC Data Low Register 915 #define DAC0_DAT11L *(volatile uint8_t *)0x400CC016 // DAC Data Low Register
916 #define DAC0_DAT12L *(volatile uint8_t *)0x400CC018 // DAC Data Low Register 916 #define DAC0_DAT12L *(volatile uint8_t *)0x400CC018 // DAC Data Low Register
917 #define DAC0_DAT13L *(volatile uint8_t *)0x400CC01A // DAC Data Low Register 917 #define DAC0_DAT13L *(volatile uint8_t *)0x400CC01A // DAC Data Low Register
918 #define DAC0_DAT14L *(volatile uint8_t *)0x400CC01C // DAC Data Low Register 918 #define DAC0_DAT14L *(volatile uint8_t *)0x400CC01C // DAC Data Low Register
919 #define DAC0_DAT15L *(volatile uint8_t *)0x400CC01E // DAC Data Low Register 919 #define DAC0_DAT15L *(volatile uint8_t *)0x400CC01E // DAC Data Low Register
920 #define DAC0_SR *(volatile uint8_t *)0x400CC020 // DAC Status Register 920 #define DAC0_SR *(volatile uint8_t *)0x400CC020 // DAC Status Register
921 #define DAC0_C0 *(volatile uint8_t *)0x400CC021 // DAC Control Register 921 #define DAC0_C0 *(volatile uint8_t *)0x400CC021 // DAC Control Register
922 #define DAC_C0_DACEN 0x80 // DAC Enable 922 #define DAC_C0_DACEN 0x80 // DAC Enable
923 #define DAC_C0_DACRFS 0x40 // DAC Reference Select 923 #define DAC_C0_DACRFS 0x40 // DAC Reference Select
924 #define DAC_C0_DACTRGSEL 0x20 // DAC Trigger Select 924 #define DAC_C0_DACTRGSEL 0x20 // DAC Trigger Select
925 #define DAC_C0_DACSWTRG 0x10 // DAC Software Trigger 925 #define DAC_C0_DACSWTRG 0x10 // DAC Software Trigger
926 #define DAC_C0_LPEN 0x08 // DAC Low Power Control 926 #define DAC_C0_LPEN 0x08 // DAC Low Power Control
927 #define DAC_C0_DACBWIEN 0x04 // DAC Buffer Watermark Interrupt Enable 927 #define DAC_C0_DACBWIEN 0x04 // DAC Buffer Watermark Interrupt Enable
928 #define DAC_C0_DACBTIEN 0x02 // DAC Buffer Read Pointer Top Flag Interrupt Enable 928 #define DAC_C0_DACBTIEN 0x02 // DAC Buffer Read Pointer Top Flag Interrupt Enable
929 #define DAC_C0_DACBBIEN 0x01 // DAC Buffer Read Pointer Bottom Flag Interrupt Enable 929 #define DAC_C0_DACBBIEN 0x01 // DAC Buffer Read Pointer Bottom Flag Interrupt Enable
930 #define DAC0_C1 *(volatile uint8_t *)0x400CC022 // DAC Control Register 1 930 #define DAC0_C1 *(volatile uint8_t *)0x400CC022 // DAC Control Register 1
931 #define DAC_C1_DMAEN 0x80 // DMA Enable Select 931 #define DAC_C1_DMAEN 0x80 // DMA Enable Select
932 #define DAC_C1_DACBFWM(n) (((n) & 3) << 3) // DAC Buffer Watermark Select 932 #define DAC_C1_DACBFWM(n) (((n) & 3) << 3) // DAC Buffer Watermark Select
933 #define DAC_C1_DACBFMD(n) (((n) & 3) << 0) // DAC Buffer Work Mode Select 933 #define DAC_C1_DACBFMD(n) (((n) & 3) << 0) // DAC Buffer Work Mode Select
934 #define DAC_C1_DACBFEN 0x00 // DAC Buffer Enable 934 #define DAC_C1_DACBFEN 0x00 // DAC Buffer Enable
935 935
936 #define DAC0_C2 *(volatile uint8_t *)0x400CC023 // DAC Control Register 2 936 #define DAC0_C2 *(volatile uint8_t *)0x400CC023 // DAC Control Register 2
937 #define DAC_C2_DACBFRP(n) (((n) & 15) << 4) // DAC Buffer Read Pointer 937 #define DAC_C2_DACBFRP(n) (((n) & 15) << 4) // DAC Buffer Read Pointer
938 #define DAC_C2_DACBFUP(n) (((n) & 15) << 0) // DAC Buffer Upper Limit 938 #define DAC_C2_DACBFUP(n) (((n) & 15) << 0) // DAC Buffer Upper Limit
939 939
940 940
941 //#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator 941 //#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
942 //#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 942 //#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
943 943
944 // Chapter 32: Comparator (CMP) 944 // Chapter 32: Comparator (CMP)
945 #define CMP0_CR0 *(volatile uint8_t *)0x40073000 // CMP Control Register 0 945 #define CMP0_CR0 *(volatile uint8_t *)0x40073000 // CMP Control Register 0
946 #define CMP0_CR1 *(volatile uint8_t *)0x40073001 // CMP Control Register 1 946 #define CMP0_CR1 *(volatile uint8_t *)0x40073001 // CMP Control Register 1
947 #define CMP0_FPR *(volatile uint8_t *)0x40073002 // CMP Filter Period Register 947 #define CMP0_FPR *(volatile uint8_t *)0x40073002 // CMP Filter Period Register
959 #define VREF_TRM *(volatile uint8_t *)0x40074000 // VREF Trim Register 959 #define VREF_TRM *(volatile uint8_t *)0x40074000 // VREF Trim Register
960 #define VREF_SC *(volatile uint8_t *)0x40074001 // VREF Status and Control Register 960 #define VREF_SC *(volatile uint8_t *)0x40074001 // VREF Status and Control Register
961 961
962 // Chapter 34: Programmable Delay Block (PDB) 962 // Chapter 34: Programmable Delay Block (PDB)
963 #define PDB0_SC *(volatile uint32_t *)0x40036000 // Status and Control Register 963 #define PDB0_SC *(volatile uint32_t *)0x40036000 // Status and Control Register
964 #define PDB_SC_LDMOD(n) (((n) & 3) << 18) // Load Mode Select 964 #define PDB_SC_LDMOD(n) (((n) & 3) << 18) // Load Mode Select
965 #define PDB_SC_PDBEIE 0x00020000 // Sequence Error Interrupt Enable 965 #define PDB_SC_PDBEIE 0x00020000 // Sequence Error Interrupt Enable
966 #define PDB_SC_SWTRIG 0x00010000 // Software Trigger 966 #define PDB_SC_SWTRIG 0x00010000 // Software Trigger
967 #define PDB_SC_DMAEN 0x00008000 // DMA Enable 967 #define PDB_SC_DMAEN 0x00008000 // DMA Enable
968 #define PDB_SC_PRESCALER(n) (((n) & 7) << 12) // Prescaler Divider Select 968 #define PDB_SC_PRESCALER(n) (((n) & 7) << 12) // Prescaler Divider Select
969 #define PDB_SC_TRGSEL(n) (((n) & 15) << 8) // Trigger Input Source Select 969 #define PDB_SC_TRGSEL(n) (((n) & 15) << 8) // Trigger Input Source Select
970 #define PDB_SC_PDBEN 0x00000080 // PDB Enable 970 #define PDB_SC_PDBEN 0x00000080 // PDB Enable
971 #define PDB_SC_PDBIF 0x00000040 // PDB Interrupt Flag 971 #define PDB_SC_PDBIF 0x00000040 // PDB Interrupt Flag
972 #define PDB_SC_PDBIE 0x00000020 // PDB Interrupt Enable. 972 #define PDB_SC_PDBIE 0x00000020 // PDB Interrupt Enable.
973 #define PDB_SC_MULT(n) (((n) & 3) << 2) // Multiplication Factor 973 #define PDB_SC_MULT(n) (((n) & 3) << 2) // Multiplication Factor
974 #define PDB_SC_CONT 0x00000002 // Continuous Mode Enable 974 #define PDB_SC_CONT 0x00000002 // Continuous Mode Enable
975 #define PDB_SC_LDOK 0x00000001 // Load OK 975 #define PDB_SC_LDOK 0x00000001 // Load OK
976 #define PDB0_MOD *(volatile uint32_t *)0x40036004 // Modulus Register 976 #define PDB0_MOD *(volatile uint32_t *)0x40036004 // Modulus Register
977 #define PDB0_CNT *(volatile uint32_t *)0x40036008 // Counter Register 977 #define PDB0_CNT *(volatile uint32_t *)0x40036008 // Counter Register
978 #define PDB0_IDLY *(volatile uint32_t *)0x4003600C // Interrupt Delay Register 978 #define PDB0_IDLY *(volatile uint32_t *)0x4003600C // Interrupt Delay Register
979 #define PDB0_CH0C1 *(volatile uint32_t *)0x40036010 // Channel n Control Register 1 979 #define PDB0_CH0C1 *(volatile uint32_t *)0x40036010 // Channel n Control Register 1
980 #define PDB0_CH0S *(volatile uint32_t *)0x40036014 // Channel n Status Register 980 #define PDB0_CH0S *(volatile uint32_t *)0x40036014 // Channel n Status Register
984 #define PDB0_PO0DLY *(volatile uint32_t *)0x40036194 // Pulse-Out n Delay Register 984 #define PDB0_PO0DLY *(volatile uint32_t *)0x40036194 // Pulse-Out n Delay Register
985 #define PDB0_PO1DLY *(volatile uint32_t *)0x40036198 // Pulse-Out n Delay Register 985 #define PDB0_PO1DLY *(volatile uint32_t *)0x40036198 // Pulse-Out n Delay Register
986 986
987 // Chapter 35: FlexTimer Module (FTM) 987 // Chapter 35: FlexTimer Module (FTM)
988 #define FTM0_SC *(volatile uint32_t *)0x40038000 // Status And Control 988 #define FTM0_SC *(volatile uint32_t *)0x40038000 // Status And Control
989 #define FTM_SC_TOF 0x80 // Timer Overflow Flag 989 #define FTM_SC_TOF 0x80 // Timer Overflow Flag
990 #define FTM_SC_TOIE 0x40 // Timer Overflow Interrupt Enable 990 #define FTM_SC_TOIE 0x40 // Timer Overflow Interrupt Enable
991 #define FTM_SC_CPWMS 0x20 // Center-Aligned PWM Select 991 #define FTM_SC_CPWMS 0x20 // Center-Aligned PWM Select
992 #define FTM_SC_CLKS(n) (((n) & 3) << 3) // Clock Source Selection 992 #define FTM_SC_CLKS(n) (((n) & 3) << 3) // Clock Source Selection
993 #define FTM_SC_PS(n) (((n) & 7) << 0) // Prescale Factor Selection 993 #define FTM_SC_PS(n) (((n) & 7) << 0) // Prescale Factor Selection
994 #define FTM0_CNT *(volatile uint32_t *)0x40038004 // Counter 994 #define FTM0_CNT *(volatile uint32_t *)0x40038004 // Counter
995 #define FTM0_MOD *(volatile uint32_t *)0x40038008 // Modulo 995 #define FTM0_MOD *(volatile uint32_t *)0x40038008 // Modulo
996 #define FTM0_C0SC *(volatile uint32_t *)0x4003800C // Channel 0 Status And Control 996 #define FTM0_C0SC *(volatile uint32_t *)0x4003800C // Channel 0 Status And Control
997 #define FTM0_C0V *(volatile uint32_t *)0x40038010 // Channel 0 Value 997 #define FTM0_C0V *(volatile uint32_t *)0x40038010 // Channel 0 Value
998 #define FTM0_C1SC *(volatile uint32_t *)0x40038014 // Channel 1 Status And Control 998 #define FTM0_C1SC *(volatile uint32_t *)0x40038014 // Channel 1 Status And Control
999 #define FTM0_C1V *(volatile uint32_t *)0x40038018 // Channel 1 Value 999 #define FTM0_C1V *(volatile uint32_t *)0x40038018 // Channel 1 Value
1000 #define FTM0_C2SC *(volatile uint32_t *)0x4003801C // Channel 2 Status And Control 1000 #define FTM0_C2SC *(volatile uint32_t *)0x4003801C // Channel 2 Status And Control
1001 #define FTM0_C2V *(volatile uint32_t *)0x40038020 // Channel 2 Value 1001 #define FTM0_C2V *(volatile uint32_t *)0x40038020 // Channel 2 Value
1002 #define FTM0_C3SC *(volatile uint32_t *)0x40038024 // Channel 3 Status And Control 1002 #define FTM0_C3SC *(volatile uint32_t *)0x40038024 // Channel 3 Status And Control
1003 #define FTM0_C3V *(volatile uint32_t *)0x40038028 // Channel 3 Value 1003 #define FTM0_C3V *(volatile uint32_t *)0x40038028 // Channel 3 Value
1004 #define FTM0_C4SC *(volatile uint32_t *)0x4003802C // Channel 4 Status And Control 1004 #define FTM0_C4SC *(volatile uint32_t *)0x4003802C // Channel 4 Status And Control
1005 #define FTM0_C4V *(volatile uint32_t *)0x40038030 // Channel 4 Value 1005 #define FTM0_C4V *(volatile uint32_t *)0x40038030 // Channel 4 Value
1006 #define FTM0_C5SC *(volatile uint32_t *)0x40038034 // Channel 5 Status And Control 1006 #define FTM0_C5SC *(volatile uint32_t *)0x40038034 // Channel 5 Status And Control
1007 #define FTM0_C5V *(volatile uint32_t *)0x40038038 // Channel 5 Value 1007 #define FTM0_C5V *(volatile uint32_t *)0x40038038 // Channel 5 Value
1008 #define FTM0_C6SC *(volatile uint32_t *)0x4003803C // Channel 6 Status And Control 1008 #define FTM0_C6SC *(volatile uint32_t *)0x4003803C // Channel 6 Status And Control
1009 #define FTM0_C6V *(volatile uint32_t *)0x40038040 // Channel 6 Value 1009 #define FTM0_C6V *(volatile uint32_t *)0x40038040 // Channel 6 Value
1010 #define FTM0_C7SC *(volatile uint32_t *)0x40038044 // Channel 7 Status And Control 1010 #define FTM0_C7SC *(volatile uint32_t *)0x40038044 // Channel 7 Status And Control
1011 #define FTM0_C7V *(volatile uint32_t *)0x40038048 // Channel 7 Value 1011 #define FTM0_C7V *(volatile uint32_t *)0x40038048 // Channel 7 Value
1012 #define FTM0_CNTIN *(volatile uint32_t *)0x4003804C // Counter Initial Value 1012 #define FTM0_CNTIN *(volatile uint32_t *)0x4003804C // Counter Initial Value
1013 #define FTM0_STATUS *(volatile uint32_t *)0x40038050 // Capture And Compare Status 1013 #define FTM0_STATUS *(volatile uint32_t *)0x40038050 // Capture And Compare Status
1014 #define FTM0_MODE *(volatile uint32_t *)0x40038054 // Features Mode Selection 1014 #define FTM0_MODE *(volatile uint32_t *)0x40038054 // Features Mode Selection
1015 #define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable 1015 #define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable
1016 #define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode 1016 #define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode
1017 #define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable 1017 #define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable
1018 #define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode 1018 #define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode
1019 #define FTM_MODE_WPDIS 0x04 // Write Protection Disable 1019 #define FTM_MODE_WPDIS 0x04 // Write Protection Disable
1020 #define FTM_MODE_INIT 0x02 // Initialize The Channels Output 1020 #define FTM_MODE_INIT 0x02 // Initialize The Channels Output
1021 #define FTM_MODE_FTMEN 0x01 // FTM Enable 1021 #define FTM_MODE_FTMEN 0x01 // FTM Enable
1022 #define FTM0_SYNC *(volatile uint32_t *)0x40038058 // Synchronization 1022 #define FTM0_SYNC *(volatile uint32_t *)0x40038058 // Synchronization
1023 #define FTM_SYNC_SWSYNC 0x80 // 1023 #define FTM_SYNC_SWSYNC 0x80 //
1024 #define FTM_SYNC_TRIG2 0x40 // 1024 #define FTM_SYNC_TRIG2 0x40 //
1025 #define FTM_SYNC_TRIG1 0x20 // 1025 #define FTM_SYNC_TRIG1 0x20 //
1026 #define FTM_SYNC_TRIG0 0x10 // 1026 #define FTM_SYNC_TRIG0 0x10 //
1027 #define FTM_SYNC_SYNCHOM 0x08 // 1027 #define FTM_SYNC_SYNCHOM 0x08 //
1028 #define FTM_SYNC_REINIT 0x04 // 1028 #define FTM_SYNC_REINIT 0x04 //
1029 #define FTM_SYNC_CNTMAX 0x02 // 1029 #define FTM_SYNC_CNTMAX 0x02 //
1030 #define FTM_SYNC_CNTMIN 0x01 // 1030 #define FTM_SYNC_CNTMIN 0x01 //
1031 #define FTM0_OUTINIT *(volatile uint32_t *)0x4003805C // Initial State For Channels Output 1031 #define FTM0_OUTINIT *(volatile uint32_t *)0x4003805C // Initial State For Channels Output
1032 #define FTM0_OUTMASK *(volatile uint32_t *)0x40038060 // Output Mask 1032 #define FTM0_OUTMASK *(volatile uint32_t *)0x40038060 // Output Mask
1033 #define FTM0_COMBINE *(volatile uint32_t *)0x40038064 // Function For Linked Channels 1033 #define FTM0_COMBINE *(volatile uint32_t *)0x40038064 // Function For Linked Channels
1034 #define FTM0_DEADTIME *(volatile uint32_t *)0x40038068 // Deadtime Insertion Control 1034 #define FTM0_DEADTIME *(volatile uint32_t *)0x40038068 // Deadtime Insertion Control
1035 #define FTM0_EXTTRIG *(volatile uint32_t *)0x4003806C // FTM External Trigger 1035 #define FTM0_EXTTRIG *(volatile uint32_t *)0x4003806C // FTM External Trigger
1045 #define FTM0_SWOCTRL *(volatile uint32_t *)0x40038094 // FTM Software Output Control 1045 #define FTM0_SWOCTRL *(volatile uint32_t *)0x40038094 // FTM Software Output Control
1046 #define FTM0_PWMLOAD *(volatile uint32_t *)0x40038098 // FTM PWM Load 1046 #define FTM0_PWMLOAD *(volatile uint32_t *)0x40038098 // FTM PWM Load
1047 #define FTM1_SC *(volatile uint32_t *)0x40039000 // Status And Control 1047 #define FTM1_SC *(volatile uint32_t *)0x40039000 // Status And Control
1048 #define FTM1_CNT *(volatile uint32_t *)0x40039004 // Counter 1048 #define FTM1_CNT *(volatile uint32_t *)0x40039004 // Counter
1049 #define FTM1_MOD *(volatile uint32_t *)0x40039008 // Modulo 1049 #define FTM1_MOD *(volatile uint32_t *)0x40039008 // Modulo
1050 #define FTM1_C0SC *(volatile uint32_t *)0x4003900C // Channel 0 Status And Control 1050 #define FTM1_C0SC *(volatile uint32_t *)0x4003900C // Channel 0 Status And Control
1051 #define FTM1_C0V *(volatile uint32_t *)0x40039010 // Channel 0 Value 1051 #define FTM1_C0V *(volatile uint32_t *)0x40039010 // Channel 0 Value
1052 #define FTM1_C1SC *(volatile uint32_t *)0x40039014 // Channel 1 Status And Control 1052 #define FTM1_C1SC *(volatile uint32_t *)0x40039014 // Channel 1 Status And Control
1053 #define FTM1_C1V *(volatile uint32_t *)0x40039018 // Channel 1 Value 1053 #define FTM1_C1V *(volatile uint32_t *)0x40039018 // Channel 1 Value
1054 #define FTM1_CNTIN *(volatile uint32_t *)0x4003904C // Counter Initial Value 1054 #define FTM1_CNTIN *(volatile uint32_t *)0x4003904C // Counter Initial Value
1055 #define FTM1_STATUS *(volatile uint32_t *)0x40039050 // Capture And Compare Status 1055 #define FTM1_STATUS *(volatile uint32_t *)0x40039050 // Capture And Compare Status
1056 #define FTM1_MODE *(volatile uint32_t *)0x40039054 // Features Mode Selection 1056 #define FTM1_MODE *(volatile uint32_t *)0x40039054 // Features Mode Selection
1057 #define FTM1_SYNC *(volatile uint32_t *)0x40039058 // Synchronization 1057 #define FTM1_SYNC *(volatile uint32_t *)0x40039058 // Synchronization
1058 #define FTM1_OUTINIT *(volatile uint32_t *)0x4003905C // Initial State For Channels Output 1058 #define FTM1_OUTINIT *(volatile uint32_t *)0x4003905C // Initial State For Channels Output
1059 #define FTM1_OUTMASK *(volatile uint32_t *)0x40039060 // Output Mask 1059 #define FTM1_OUTMASK *(volatile uint32_t *)0x40039060 // Output Mask
1060 #define FTM1_COMBINE *(volatile uint32_t *)0x40039064 // Function For Linked Channels 1060 #define FTM1_COMBINE *(volatile uint32_t *)0x40039064 // Function For Linked Channels
1061 #define FTM1_DEADTIME *(volatile uint32_t *)0x40039068 // Deadtime Insertion Control 1061 #define FTM1_DEADTIME *(volatile uint32_t *)0x40039068 // Deadtime Insertion Control
1062 #define FTM1_EXTTRIG *(volatile uint32_t *)0x4003906C // FTM External Trigger 1062 #define FTM1_EXTTRIG *(volatile uint32_t *)0x4003906C // FTM External Trigger
1063 #define FTM1_POL *(volatile uint32_t *)0x40039070 // Channels Polarity 1063 #define FTM1_POL *(volatile uint32_t *)0x40039070 // Channels Polarity
1064 #define FTM1_FMS *(volatile uint32_t *)0x40039074 // Fault Mode Status 1064 #define FTM1_FMS *(volatile uint32_t *)0x40039074 // Fault Mode Status
1065 #define FTM1_FILTER *(volatile uint32_t *)0x40039078 // Input Capture Filter Control 1065 #define FTM1_FILTER *(volatile uint32_t *)0x40039078 // Input Capture Filter Control
1066 #define FTM1_FLTCTRL *(volatile uint32_t *)0x4003907C // Fault Control 1066 #define FTM1_FLTCTRL *(volatile uint32_t *)0x4003907C // Fault Control
1067 #define FTM1_QDCTRL *(volatile uint32_t *)0x40039080 // Quadrature Decoder Control And Status 1067 #define FTM1_QDCTRL *(volatile uint32_t *)0x40039080 // Quadrature Decoder Control And Status
1068 #define FTM1_CONF *(volatile uint32_t *)0x40039084 // Configuration 1068 #define FTM1_CONF *(volatile uint32_t *)0x40039084 // Configuration
1069 #define FTM1_FLTPOL *(volatile uint32_t *)0x40039088 // FTM Fault Input Polarity 1069 #define FTM1_FLTPOL *(volatile uint32_t *)0x40039088 // FTM Fault Input Polarity
1070 #define FTM1_SYNCONF *(volatile uint32_t *)0x4003908C // Synchronization Configuration 1070 #define FTM1_SYNCONF *(volatile uint32_t *)0x4003908C // Synchronization Configuration
1071 #define FTM1_INVCTRL *(volatile uint32_t *)0x40039090 // FTM Inverting Control 1071 #define FTM1_INVCTRL *(volatile uint32_t *)0x40039090 // FTM Inverting Control
1072 #define FTM1_SWOCTRL *(volatile uint32_t *)0x40039094 // FTM Software Output Control 1072 #define FTM1_SWOCTRL *(volatile uint32_t *)0x40039094 // FTM Software Output Control
1073 #define FTM1_PWMLOAD *(volatile uint32_t *)0x40039098 // FTM PWM Load 1073 #define FTM1_PWMLOAD *(volatile uint32_t *)0x40039098 // FTM PWM Load
1074 #define FTM2_SC *(volatile uint32_t *)0x400B8000 // Status And Control 1074 #define FTM2_SC *(volatile uint32_t *)0x400B8000 // Status And Control
1075 #define FTM2_CNT *(volatile uint32_t *)0x400B8004 // Counter 1075 #define FTM2_CNT *(volatile uint32_t *)0x400B8004 // Counter
1076 #define FTM2_MOD *(volatile uint32_t *)0x400B8008 // Modulo 1076 #define FTM2_MOD *(volatile uint32_t *)0x400B8008 // Modulo
1077 #define FTM2_C0SC *(volatile uint32_t *)0x400B800C // Channel 0 Status And Control 1077 #define FTM2_C0SC *(volatile uint32_t *)0x400B800C // Channel 0 Status And Control
1078 #define FTM2_C0V *(volatile uint32_t *)0x400B8010 // Channel 0 Value 1078 #define FTM2_C0V *(volatile uint32_t *)0x400B8010 // Channel 0 Value
1079 #define FTM2_C1SC *(volatile uint32_t *)0x400B8014 // Channel 1 Status And Control 1079 #define FTM2_C1SC *(volatile uint32_t *)0x400B8014 // Channel 1 Status And Control
1080 #define FTM2_C1V *(volatile uint32_t *)0x400B8018 // Channel 1 Value 1080 #define FTM2_C1V *(volatile uint32_t *)0x400B8018 // Channel 1 Value
1081 #define FTM2_CNTIN *(volatile uint32_t *)0x400B804C // Counter Initial Value 1081 #define FTM2_CNTIN *(volatile uint32_t *)0x400B804C // Counter Initial Value
1082 #define FTM2_STATUS *(volatile uint32_t *)0x400B8050 // Capture And Compare Status 1082 #define FTM2_STATUS *(volatile uint32_t *)0x400B8050 // Capture And Compare Status
1083 #define FTM2_MODE *(volatile uint32_t *)0x400B8054 // Features Mode Selection 1083 #define FTM2_MODE *(volatile uint32_t *)0x400B8054 // Features Mode Selection
1084 #define FTM2_SYNC *(volatile uint32_t *)0x400B8058 // Synchronization 1084 #define FTM2_SYNC *(volatile uint32_t *)0x400B8058 // Synchronization
1085 #define FTM2_OUTINIT *(volatile uint32_t *)0x400B805C // Initial State For Channels Output 1085 #define FTM2_OUTINIT *(volatile uint32_t *)0x400B805C // Initial State For Channels Output
1086 #define FTM2_OUTMASK *(volatile uint32_t *)0x400B8060 // Output Mask 1086 #define FTM2_OUTMASK *(volatile uint32_t *)0x400B8060 // Output Mask
1087 #define FTM2_COMBINE *(volatile uint32_t *)0x400B8064 // Function For Linked Channels 1087 #define FTM2_COMBINE *(volatile uint32_t *)0x400B8064 // Function For Linked Channels
1088 #define FTM2_DEADTIME *(volatile uint32_t *)0x400B8068 // Deadtime Insertion Control 1088 #define FTM2_DEADTIME *(volatile uint32_t *)0x400B8068 // Deadtime Insertion Control
1089 #define FTM2_EXTTRIG *(volatile uint32_t *)0x400B806C // FTM External Trigger 1089 #define FTM2_EXTTRIG *(volatile uint32_t *)0x400B806C // FTM External Trigger
1090 #define FTM2_POL *(volatile uint32_t *)0x400B8070 // Channels Polarity 1090 #define FTM2_POL *(volatile uint32_t *)0x400B8070 // Channels Polarity
1091 #define FTM2_FMS *(volatile uint32_t *)0x400B8074 // Fault Mode Status 1091 #define FTM2_FMS *(volatile uint32_t *)0x400B8074 // Fault Mode Status
1092 #define FTM2_FILTER *(volatile uint32_t *)0x400B8078 // Input Capture Filter Control 1092 #define FTM2_FILTER *(volatile uint32_t *)0x400B8078 // Input Capture Filter Control
1093 #define FTM2_FLTCTRL *(volatile uint32_t *)0x400B807C // Fault Control 1093 #define FTM2_FLTCTRL *(volatile uint32_t *)0x400B807C // Fault Control
1094 #define FTM2_QDCTRL *(volatile uint32_t *)0x400B8080 // Quadrature Decoder Control And Status 1094 #define FTM2_QDCTRL *(volatile uint32_t *)0x400B8080 // Quadrature Decoder Control And Status
1095 #define FTM2_CONF *(volatile uint32_t *)0x400B8084 // Configuration 1095 #define FTM2_CONF *(volatile uint32_t *)0x400B8084 // Configuration
1096 #define FTM2_FLTPOL *(volatile uint32_t *)0x400B8088 // FTM Fault Input Polarity 1096 #define FTM2_FLTPOL *(volatile uint32_t *)0x400B8088 // FTM Fault Input Polarity
1097 #define FTM2_SYNCONF *(volatile uint32_t *)0x400B808C // Synchronization Configuration 1097 #define FTM2_SYNCONF *(volatile uint32_t *)0x400B808C // Synchronization Configuration
1098 #define FTM2_INVCTRL *(volatile uint32_t *)0x400B8090 // FTM Inverting Control 1098 #define FTM2_INVCTRL *(volatile uint32_t *)0x400B8090 // FTM Inverting Control
1099 #define FTM2_SWOCTRL *(volatile uint32_t *)0x400B8094 // FTM Software Output Control 1099 #define FTM2_SWOCTRL *(volatile uint32_t *)0x400B8094 // FTM Software Output Control
1100 #define FTM2_PWMLOAD *(volatile uint32_t *)0x400B8098 // FTM PWM Load 1100 #define FTM2_PWMLOAD *(volatile uint32_t *)0x400B8098 // FTM PWM Load
1101 1101
1102 // Chapter 36: Periodic Interrupt Timer (PIT) 1102 // Chapter 36: Periodic Interrupt Timer (PIT)
1103 #define PIT_MCR *(volatile uint32_t *)0x40037000 // PIT Module Control Register 1103 #define PIT_MCR *(volatile uint32_t *)0x40037000 // PIT Module Control Register
1104 #define PIT_LDVAL0 *(volatile uint32_t *)0x40037100 // Timer Load Value Register 1104 #define PIT_LDVAL0 *(volatile uint32_t *)0x40037100 // Timer Load Value Register
1105 #define PIT_CVAL0 *(volatile uint32_t *)0x40037104 // Current Timer Value Register 1105 #define PIT_CVAL0 *(volatile uint32_t *)0x40037104 // Current Timer Value Register
1141 // Chapter 39: Real Time Clock (RTC) 1141 // Chapter 39: Real Time Clock (RTC)
1142 #define RTC_TSR *(volatile uint32_t *)0x4003D000 // RTC Time Seconds Register 1142 #define RTC_TSR *(volatile uint32_t *)0x4003D000 // RTC Time Seconds Register
1143 #define RTC_TPR *(volatile uint32_t *)0x4003D004 // RTC Time Prescaler Register 1143 #define RTC_TPR *(volatile uint32_t *)0x4003D004 // RTC Time Prescaler Register
1144 #define RTC_TAR *(volatile uint32_t *)0x4003D008 // RTC Time Alarm Register 1144 #define RTC_TAR *(volatile uint32_t *)0x4003D008 // RTC Time Alarm Register
1145 #define RTC_TCR *(volatile uint32_t *)0x4003D00C // RTC Time Compensation Register 1145 #define RTC_TCR *(volatile uint32_t *)0x4003D00C // RTC Time Compensation Register
1146 #define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter 1146 #define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter
1147 #define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value 1147 #define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value
1148 #define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register 1148 #define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register
1149 #define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register 1149 #define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register
1150 #define RTC_CR *(volatile uint32_t *)0x4003D010 // RTC Control Register 1150 #define RTC_CR *(volatile uint32_t *)0x4003D010 // RTC Control Register
1151 #define RTC_CR_SC2P (uint32_t)0x00002000 // 1151 #define RTC_CR_SC2P (uint32_t)0x00002000 //
1152 #define RTC_CR_SC4P (uint32_t)0x00001000 // 1152 #define RTC_CR_SC4P (uint32_t)0x00001000 //
1153 #define RTC_CR_SC8P (uint32_t)0x00000800 // 1153 #define RTC_CR_SC8P (uint32_t)0x00000800 //
1154 #define RTC_CR_SC16P (uint32_t)0x00000400 // 1154 #define RTC_CR_SC16P (uint32_t)0x00000400 //
1155 #define RTC_CR_CLKO (uint32_t)0x00000200 // 1155 #define RTC_CR_CLKO (uint32_t)0x00000200 //
1156 #define RTC_CR_OSCE (uint32_t)0x00000100 // 1156 #define RTC_CR_OSCE (uint32_t)0x00000100 //
1157 #define RTC_CR_UM (uint32_t)0x00000008 // 1157 #define RTC_CR_UM (uint32_t)0x00000008 //
1158 #define RTC_CR_SUP (uint32_t)0x00000004 // 1158 #define RTC_CR_SUP (uint32_t)0x00000004 //
1159 #define RTC_CR_WPE (uint32_t)0x00000002 // 1159 #define RTC_CR_WPE (uint32_t)0x00000002 //
1160 #define RTC_CR_SWR (uint32_t)0x00000001 // 1160 #define RTC_CR_SWR (uint32_t)0x00000001 //
1161 #define RTC_SR *(volatile uint32_t *)0x4003D014 // RTC Status Register 1161 #define RTC_SR *(volatile uint32_t *)0x4003D014 // RTC Status Register
1162 #define RTC_SR_TCE (uint32_t)0x00000010 // 1162 #define RTC_SR_TCE (uint32_t)0x00000010 //
1163 #define RTC_SR_TAF (uint32_t)0x00000004 // 1163 #define RTC_SR_TAF (uint32_t)0x00000004 //
1164 #define RTC_SR_TOF (uint32_t)0x00000002 // 1164 #define RTC_SR_TOF (uint32_t)0x00000002 //
1165 #define RTC_SR_TIF (uint32_t)0x00000001 // 1165 #define RTC_SR_TIF (uint32_t)0x00000001 //
1166 #define RTC_LR *(volatile uint32_t *)0x4003D018 // RTC Lock Register 1166 #define RTC_LR *(volatile uint32_t *)0x4003D018 // RTC Lock Register
1167 #define RTC_IER *(volatile uint32_t *)0x4003D01C // RTC Interrupt Enable Register 1167 #define RTC_IER *(volatile uint32_t *)0x4003D01C // RTC Interrupt Enable Register
1168 #define RTC_WAR *(volatile uint32_t *)0x4003D800 // RTC Write Access Register 1168 #define RTC_WAR *(volatile uint32_t *)0x4003D800 // RTC Write Access Register
1169 #define RTC_RAR *(volatile uint32_t *)0x4003D804 // RTC Read Access Register 1169 #define RTC_RAR *(volatile uint32_t *)0x4003D804 // RTC Read Access Register
1170 1170
1172 #define USB0_PERID *(const uint8_t *)0x40072000 // Peripheral ID register 1172 #define USB0_PERID *(const uint8_t *)0x40072000 // Peripheral ID register
1173 #define USB0_IDCOMP *(const uint8_t *)0x40072004 // Peripheral ID Complement register 1173 #define USB0_IDCOMP *(const uint8_t *)0x40072004 // Peripheral ID Complement register
1174 #define USB0_REV *(const uint8_t *)0x40072008 // Peripheral Revision register 1174 #define USB0_REV *(const uint8_t *)0x40072008 // Peripheral Revision register
1175 #define USB0_ADDINFO *(volatile uint8_t *)0x4007200C // Peripheral Additional Info register 1175 #define USB0_ADDINFO *(volatile uint8_t *)0x4007200C // Peripheral Additional Info register
1176 #define USB0_OTGISTAT *(volatile uint8_t *)0x40072010 // OTG Interrupt Status register 1176 #define USB0_OTGISTAT *(volatile uint8_t *)0x40072010 // OTG Interrupt Status register
1177 #define USB_OTGISTAT_IDCHG (uint8_t)0x80 // 1177 #define USB_OTGISTAT_IDCHG (uint8_t)0x80 //
1178 #define USB_OTGISTAT_ONEMSEC (uint8_t)0x40 // 1178 #define USB_OTGISTAT_ONEMSEC (uint8_t)0x40 //
1179 #define USB_OTGISTAT_LINE_STATE_CHG (uint8_t)0x20 // 1179 #define USB_OTGISTAT_LINE_STATE_CHG (uint8_t)0x20 //
1180 #define USB_OTGISTAT_SESSVLDCHG (uint8_t)0x08 // 1180 #define USB_OTGISTAT_SESSVLDCHG (uint8_t)0x08 //
1181 #define USB_OTGISTAT_B_SESS_CHG (uint8_t)0x04 // 1181 #define USB_OTGISTAT_B_SESS_CHG (uint8_t)0x04 //
1182 #define USB_OTGISTAT_AVBUSCHG (uint8_t)0x01 // 1182 #define USB_OTGISTAT_AVBUSCHG (uint8_t)0x01 //
1183 #define USB0_OTGICR *(volatile uint8_t *)0x40072014 // OTG Interrupt Control Register 1183 #define USB0_OTGICR *(volatile uint8_t *)0x40072014 // OTG Interrupt Control Register
1184 #define USB_OTGICR_IDEN (uint8_t)0x80 // 1184 #define USB_OTGICR_IDEN (uint8_t)0x80 //
1185 #define USB_OTGICR_ONEMSECEN (uint8_t)0x40 // 1185 #define USB_OTGICR_ONEMSECEN (uint8_t)0x40 //
1186 #define USB_OTGICR_LINESTATEEN (uint8_t)0x20 // 1186 #define USB_OTGICR_LINESTATEEN (uint8_t)0x20 //
1187 #define USB_OTGICR_SESSVLDEN (uint8_t)0x08 // 1187 #define USB_OTGICR_SESSVLDEN (uint8_t)0x08 //
1188 #define USB_OTGICR_BSESSEN (uint8_t)0x04 // 1188 #define USB_OTGICR_BSESSEN (uint8_t)0x04 //
1189 #define USB_OTGICR_AVBUSEN (uint8_t)0x01 // 1189 #define USB_OTGICR_AVBUSEN (uint8_t)0x01 //
1190 #define USB0_OTGSTAT *(volatile uint8_t *)0x40072018 // OTG Status register 1190 #define USB0_OTGSTAT *(volatile uint8_t *)0x40072018 // OTG Status register
1191 #define USB_OTGSTAT_ID (uint8_t)0x80 // 1191 #define USB_OTGSTAT_ID (uint8_t)0x80 //
1192 #define USB_OTGSTAT_ONEMSECEN (uint8_t)0x40 // 1192 #define USB_OTGSTAT_ONEMSECEN (uint8_t)0x40 //
1193 #define USB_OTGSTAT_LINESTATESTABLE (uint8_t)0x20 // 1193 #define USB_OTGSTAT_LINESTATESTABLE (uint8_t)0x20 //
1194 #define USB_OTGSTAT_SESS_VLD (uint8_t)0x08 // 1194 #define USB_OTGSTAT_SESS_VLD (uint8_t)0x08 //
1195 #define USB_OTGSTAT_BSESSEND (uint8_t)0x04 // 1195 #define USB_OTGSTAT_BSESSEND (uint8_t)0x04 //
1196 #define USB_OTGSTAT_AVBUSVLD (uint8_t)0x01 // 1196 #define USB_OTGSTAT_AVBUSVLD (uint8_t)0x01 //
1197 #define USB0_OTGCTL *(volatile uint8_t *)0x4007201C // OTG Control Register 1197 #define USB0_OTGCTL *(volatile uint8_t *)0x4007201C // OTG Control Register
1198 #define USB_OTGCTL_DPHIGH (uint8_t)0x80 // 1198 #define USB_OTGCTL_DPHIGH (uint8_t)0x80 //
1199 #define USB_OTGCTL_DPLOW (uint8_t)0x20 // 1199 #define USB_OTGCTL_DPLOW (uint8_t)0x20 //
1200 #define USB_OTGCTL_DMLOW (uint8_t)0x10 // 1200 #define USB_OTGCTL_DMLOW (uint8_t)0x10 //
1201 #define USB_OTGCTL_OTGEN (uint8_t)0x04 // 1201 #define USB_OTGCTL_OTGEN (uint8_t)0x04 //
1202 #define USB0_ISTAT *(volatile uint8_t *)0x40072080 // Interrupt Status Register 1202 #define USB0_ISTAT *(volatile uint8_t *)0x40072080 // Interrupt Status Register
1203 #define USB_ISTAT_STALL (uint8_t)0x80 // 1203 #define USB_ISTAT_STALL (uint8_t)0x80 //
1204 #define USB_ISTAT_ATTACH (uint8_t)0x40 // 1204 #define USB_ISTAT_ATTACH (uint8_t)0x40 //
1205 #define USB_ISTAT_RESUME (uint8_t)0x20 // 1205 #define USB_ISTAT_RESUME (uint8_t)0x20 //
1206 #define USB_ISTAT_SLEEP (uint8_t)0x10 // 1206 #define USB_ISTAT_SLEEP (uint8_t)0x10 //
1207 #define USB_ISTAT_TOKDNE (uint8_t)0x08 // 1207 #define USB_ISTAT_TOKDNE (uint8_t)0x08 //
1208 #define USB_ISTAT_SOFTOK (uint8_t)0x04 // 1208 #define USB_ISTAT_SOFTOK (uint8_t)0x04 //
1209 #define USB_ISTAT_ERROR (uint8_t)0x02 // 1209 #define USB_ISTAT_ERROR (uint8_t)0x02 //
1210 #define USB_ISTAT_USBRST (uint8_t)0x01 // 1210 #define USB_ISTAT_USBRST (uint8_t)0x01 //
1211 #define USB0_INTEN *(volatile uint8_t *)0x40072084 // Interrupt Enable Register 1211 #define USB0_INTEN *(volatile uint8_t *)0x40072084 // Interrupt Enable Register
1212 #define USB_INTEN_STALLEN (uint8_t)0x80 // 1212 #define USB_INTEN_STALLEN (uint8_t)0x80 //
1213 #define USB_INTEN_ATTACHEN (uint8_t)0x40 // 1213 #define USB_INTEN_ATTACHEN (uint8_t)0x40 //
1214 #define USB_INTEN_RESUMEEN (uint8_t)0x20 // 1214 #define USB_INTEN_RESUMEEN (uint8_t)0x20 //
1215 #define USB_INTEN_SLEEPEN (uint8_t)0x10 // 1215 #define USB_INTEN_SLEEPEN (uint8_t)0x10 //
1216 #define USB_INTEN_TOKDNEEN (uint8_t)0x08 // 1216 #define USB_INTEN_TOKDNEEN (uint8_t)0x08 //
1217 #define USB_INTEN_SOFTOKEN (uint8_t)0x04 // 1217 #define USB_INTEN_SOFTOKEN (uint8_t)0x04 //
1218 #define USB_INTEN_ERROREN (uint8_t)0x02 // 1218 #define USB_INTEN_ERROREN (uint8_t)0x02 //
1219 #define USB_INTEN_USBRSTEN (uint8_t)0x01 // 1219 #define USB_INTEN_USBRSTEN (uint8_t)0x01 //
1220 #define USB0_ERRSTAT *(volatile uint8_t *)0x40072088 // Error Interrupt Status Register 1220 #define USB0_ERRSTAT *(volatile uint8_t *)0x40072088 // Error Interrupt Status Register
1221 #define USB_ERRSTAT_BTSERR (uint8_t)0x80 // 1221 #define USB_ERRSTAT_BTSERR (uint8_t)0x80 //
1222 #define USB_ERRSTAT_DMAERR (uint8_t)0x20 // 1222 #define USB_ERRSTAT_DMAERR (uint8_t)0x20 //
1223 #define USB_ERRSTAT_BTOERR (uint8_t)0x10 // 1223 #define USB_ERRSTAT_BTOERR (uint8_t)0x10 //
1224 #define USB_ERRSTAT_DFN8 (uint8_t)0x08 // 1224 #define USB_ERRSTAT_DFN8 (uint8_t)0x08 //
1225 #define USB_ERRSTAT_CRC16 (uint8_t)0x04 // 1225 #define USB_ERRSTAT_CRC16 (uint8_t)0x04 //
1226 #define USB_ERRSTAT_CRC5EOF (uint8_t)0x02 // 1226 #define USB_ERRSTAT_CRC5EOF (uint8_t)0x02 //
1227 #define USB_ERRSTAT_PIDERR (uint8_t)0x01 // 1227 #define USB_ERRSTAT_PIDERR (uint8_t)0x01 //
1228 #define USB0_ERREN *(volatile uint8_t *)0x4007208C // Error Interrupt Enable Register 1228 #define USB0_ERREN *(volatile uint8_t *)0x4007208C // Error Interrupt Enable Register
1229 #define USB_ERREN_BTSERREN (uint8_t)0x80 // 1229 #define USB_ERREN_BTSERREN (uint8_t)0x80 //
1230 #define USB_ERREN_DMAERREN (uint8_t)0x20 // 1230 #define USB_ERREN_DMAERREN (uint8_t)0x20 //
1231 #define USB_ERREN_BTOERREN (uint8_t)0x10 // 1231 #define USB_ERREN_BTOERREN (uint8_t)0x10 //
1232 #define USB_ERREN_DFN8EN (uint8_t)0x08 // 1232 #define USB_ERREN_DFN8EN (uint8_t)0x08 //
1233 #define USB_ERREN_CRC16EN (uint8_t)0x04 // 1233 #define USB_ERREN_CRC16EN (uint8_t)0x04 //
1234 #define USB_ERREN_CRC5EOFEN (uint8_t)0x02 // 1234 #define USB_ERREN_CRC5EOFEN (uint8_t)0x02 //
1235 #define USB_ERREN_PIDERREN (uint8_t)0x01 // 1235 #define USB_ERREN_PIDERREN (uint8_t)0x01 //
1236 #define USB0_STAT *(volatile uint8_t *)0x40072090 // Status Register 1236 #define USB0_STAT *(volatile uint8_t *)0x40072090 // Status Register
1237 #define USB_STAT_TX (uint8_t)0x08 // 1237 #define USB_STAT_TX (uint8_t)0x08 //
1238 #define USB_STAT_ODD (uint8_t)0x04 // 1238 #define USB_STAT_ODD (uint8_t)0x04 //
1239 #define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) // 1239 #define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) //
1240 #define USB0_CTL *(volatile uint8_t *)0x40072094 // Control Register 1240 #define USB0_CTL *(volatile uint8_t *)0x40072094 // Control Register
1241 #define USB_CTL_JSTATE (uint8_t)0x80 // 1241 #define USB_CTL_JSTATE (uint8_t)0x80 //
1242 #define USB_CTL_SE0 (uint8_t)0x40 // 1242 #define USB_CTL_SE0 (uint8_t)0x40 //
1243 #define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 // 1243 #define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 //
1244 #define USB_CTL_RESET (uint8_t)0x10 // 1244 #define USB_CTL_RESET (uint8_t)0x10 //
1245 #define USB_CTL_HOSTMODEEN (uint8_t)0x08 // 1245 #define USB_CTL_HOSTMODEEN (uint8_t)0x08 //
1246 #define USB_CTL_RESUME (uint8_t)0x04 // 1246 #define USB_CTL_RESUME (uint8_t)0x04 //
1247 #define USB_CTL_ODDRST (uint8_t)0x02 // 1247 #define USB_CTL_ODDRST (uint8_t)0x02 //
1248 #define USB_CTL_USBENSOFEN (uint8_t)0x01 // 1248 #define USB_CTL_USBENSOFEN (uint8_t)0x01 //
1249 #define USB0_ADDR *(volatile uint8_t *)0x40072098 // Address Register 1249 #define USB0_ADDR *(volatile uint8_t *)0x40072098 // Address Register
1250 #define USB0_BDTPAGE1 *(volatile uint8_t *)0x4007209C // BDT Page Register 1 1250 #define USB0_BDTPAGE1 *(volatile uint8_t *)0x4007209C // BDT Page Register 1
1251 #define USB0_FRMNUML *(volatile uint8_t *)0x400720A0 // Frame Number Register Low 1251 #define USB0_FRMNUML *(volatile uint8_t *)0x400720A0 // Frame Number Register Low
1252 #define USB0_FRMNUMH *(volatile uint8_t *)0x400720A4 // Frame Number Register High 1252 #define USB0_FRMNUMH *(volatile uint8_t *)0x400720A4 // Frame Number Register High
1253 #define USB0_TOKEN *(volatile uint8_t *)0x400720A8 // Token Register 1253 #define USB0_TOKEN *(volatile uint8_t *)0x400720A8 // Token Register
1254 #define USB0_SOFTHLD *(volatile uint8_t *)0x400720AC // SOF Threshold Register 1254 #define USB0_SOFTHLD *(volatile uint8_t *)0x400720AC // SOF Threshold Register
1255 #define USB0_BDTPAGE2 *(volatile uint8_t *)0x400720B0 // BDT Page Register 2 1255 #define USB0_BDTPAGE2 *(volatile uint8_t *)0x400720B0 // BDT Page Register 2
1256 #define USB0_BDTPAGE3 *(volatile uint8_t *)0x400720B4 // BDT Page Register 3 1256 #define USB0_BDTPAGE3 *(volatile uint8_t *)0x400720B4 // BDT Page Register 3
1257 #define USB0_ENDPT0 *(volatile uint8_t *)0x400720C0 // Endpoint Control Register 1257 #define USB0_ENDPT0 *(volatile uint8_t *)0x400720C0 // Endpoint Control Register
1258 #define USB_ENDPT_HOSTWOHUB (uint8_t)0x80 // host only, enable low speed 1258 #define USB_ENDPT_HOSTWOHUB (uint8_t)0x80 // host only, enable low speed
1259 #define USB_ENDPT_RETRYDIS (uint8_t)0x40 // host only, set to disable NAK retry 1259 #define USB_ENDPT_RETRYDIS (uint8_t)0x40 // host only, set to disable NAK retry
1260 #define USB_ENDPT_EPCTLDIS (uint8_t)0x10 // 0=control, 1=bulk, interrupt, isync 1260 #define USB_ENDPT_EPCTLDIS (uint8_t)0x10 // 0=control, 1=bulk, interrupt, isync
1261 #define USB_ENDPT_EPRXEN (uint8_t)0x08 // enables the endpoint for RX transfers. 1261 #define USB_ENDPT_EPRXEN (uint8_t)0x08 // enables the endpoint for RX transfers.
1262 #define USB_ENDPT_EPTXEN (uint8_t)0x04 // enables the endpoint for TX transfers. 1262 #define USB_ENDPT_EPTXEN (uint8_t)0x04 // enables the endpoint for TX transfers.
1263 #define USB_ENDPT_EPSTALL (uint8_t)0x02 // set to stall endpoint 1263 #define USB_ENDPT_EPSTALL (uint8_t)0x02 // set to stall endpoint
1264 #define USB_ENDPT_EPHSHK (uint8_t)0x01 // enable handshaking during a transaction, generally set unless Isochronous 1264 #define USB_ENDPT_EPHSHK (uint8_t)0x01 // enable handshaking during a transaction, generally set unless Isochronous
1265 #define USB0_ENDPT1 *(volatile uint8_t *)0x400720C4 // Endpoint Control Register 1265 #define USB0_ENDPT1 *(volatile uint8_t *)0x400720C4 // Endpoint Control Register
1266 #define USB0_ENDPT2 *(volatile uint8_t *)0x400720C8 // Endpoint Control Register 1266 #define USB0_ENDPT2 *(volatile uint8_t *)0x400720C8 // Endpoint Control Register
1267 #define USB0_ENDPT3 *(volatile uint8_t *)0x400720CC // Endpoint Control Register 1267 #define USB0_ENDPT3 *(volatile uint8_t *)0x400720CC // Endpoint Control Register
1268 #define USB0_ENDPT4 *(volatile uint8_t *)0x400720D0 // Endpoint Control Register 1268 #define USB0_ENDPT4 *(volatile uint8_t *)0x400720D0 // Endpoint Control Register
1269 #define USB0_ENDPT5 *(volatile uint8_t *)0x400720D4 // Endpoint Control Register 1269 #define USB0_ENDPT5 *(volatile uint8_t *)0x400720D4 // Endpoint Control Register
1276 #define USB0_ENDPT12 *(volatile uint8_t *)0x400720F0 // Endpoint Control Register 1276 #define USB0_ENDPT12 *(volatile uint8_t *)0x400720F0 // Endpoint Control Register
1277 #define USB0_ENDPT13 *(volatile uint8_t *)0x400720F4 // Endpoint Control Register 1277 #define USB0_ENDPT13 *(volatile uint8_t *)0x400720F4 // Endpoint Control Register
1278 #define USB0_ENDPT14 *(volatile uint8_t *)0x400720F8 // Endpoint Control Register 1278 #define USB0_ENDPT14 *(volatile uint8_t *)0x400720F8 // Endpoint Control Register
1279 #define USB0_ENDPT15 *(volatile uint8_t *)0x400720FC // Endpoint Control Register 1279 #define USB0_ENDPT15 *(volatile uint8_t *)0x400720FC // Endpoint Control Register
1280 #define USB0_USBCTRL *(volatile uint8_t *)0x40072100 // USB Control Register 1280 #define USB0_USBCTRL *(volatile uint8_t *)0x40072100 // USB Control Register
1281 #define USB_USBCTRL_SUSP (uint8_t)0x80 // Places the USB transceiver into the suspend state. 1281 #define USB_USBCTRL_SUSP (uint8_t)0x80 // Places the USB transceiver into the suspend state.
1282 #define USB_USBCTRL_PDE (uint8_t)0x40 // Enables the weak pulldowns on the USB transceiver. 1282 #define USB_USBCTRL_PDE (uint8_t)0x40 // Enables the weak pulldowns on the USB transceiver.
1283 #define USB0_OBSERVE *(volatile uint8_t *)0x40072104 // USB OTG Observe Register 1283 #define USB0_OBSERVE *(volatile uint8_t *)0x40072104 // USB OTG Observe Register
1284 #define USB_OBSERVE_DPPU (uint8_t)0x80 // 1284 #define USB_OBSERVE_DPPU (uint8_t)0x80 //
1285 #define USB_OBSERVE_DPPD (uint8_t)0x40 // 1285 #define USB_OBSERVE_DPPD (uint8_t)0x40 //
1286 #define USB_OBSERVE_DMPD (uint8_t)0x10 // 1286 #define USB_OBSERVE_DMPD (uint8_t)0x10 //
1287 #define USB0_CONTROL *(volatile uint8_t *)0x40072108 // USB OTG Control Register 1287 #define USB0_CONTROL *(volatile uint8_t *)0x40072108 // USB OTG Control Register
1288 #define USB_CONTROL_DPPULLUPNONOTG (uint8_t)0x10 // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode. 1288 #define USB_CONTROL_DPPULLUPNONOTG (uint8_t)0x10 // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.
1289 #define USB0_USBTRC0 *(volatile uint8_t *)0x4007210C // USB Transceiver Control Register 0 1289 #define USB0_USBTRC0 *(volatile uint8_t *)0x4007210C // USB Transceiver Control Register 0
1290 #define USB_USBTRC_USBRESET (uint8_t)0x80 // 1290 #define USB_USBTRC_USBRESET (uint8_t)0x80 //
1291 #define USB_USBTRC_USBRESMEN (uint8_t)0x20 // 1291 #define USB_USBTRC_USBRESMEN (uint8_t)0x20 //
1292 #define USB_USBTRC_SYNC_DET (uint8_t)0x02 // 1292 #define USB_USBTRC_SYNC_DET (uint8_t)0x02 //
1293 #define USB_USBTRC_USB_RESUME_INT (uint8_t)0x01 // 1293 #define USB_USBTRC_USB_RESUME_INT (uint8_t)0x01 //
1294 #define USB0_USBFRMADJUST *(volatile uint8_t *)0x40072114 // Frame Adjust Register 1294 #define USB0_USBFRMADJUST *(volatile uint8_t *)0x40072114 // Frame Adjust Register
1295 1295
1296 // Chapter 41: USB Device Charger Detection Module (USBDCD) 1296 // Chapter 41: USB Device Charger Detection Module (USBDCD)
1297 #define USBDCD_CONTROL *(volatile uint32_t *)0x40035000 // Control register 1297 #define USBDCD_CONTROL *(volatile uint32_t *)0x40035000 // Control register
1298 #define USBDCD_CLOCK *(volatile uint32_t *)0x40035004 // Clock register 1298 #define USBDCD_CLOCK *(volatile uint32_t *)0x40035004 // Clock register
1301 #define USBDCD_TIMER1 *(volatile uint32_t *)0x40035014 // TIMER1 register 1301 #define USBDCD_TIMER1 *(volatile uint32_t *)0x40035014 // TIMER1 register
1302 #define USBDCD_TIMER2 *(volatile uint32_t *)0x40035018 // TIMER2 register 1302 #define USBDCD_TIMER2 *(volatile uint32_t *)0x40035018 // TIMER2 register
1303 1303
1304 // Chapter 43: SPI (DSPI) 1304 // Chapter 43: SPI (DSPI)
1305 #define SPI0_MCR *(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register 1305 #define SPI0_MCR *(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register
1306 #define SPI_MCR_MSTR (uint32_t)0x80000000 // Master/Slave Mode Select 1306 #define SPI_MCR_MSTR (uint32_t)0x80000000 // Master/Slave Mode Select
1307 #define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 // 1307 #define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 //
1308 #define SPI_MCR_DCONF(n) (((n) & 3) << 28) // 1308 #define SPI_MCR_DCONF(n) (((n) & 3) << 28) //
1309 #define SPI_MCR_FRZ (uint32_t)0x08000000 // 1309 #define SPI_MCR_FRZ (uint32_t)0x08000000 //
1310 #define SPI_MCR_MTFE (uint32_t)0x04000000 // 1310 #define SPI_MCR_MTFE (uint32_t)0x04000000 //
1311 #define SPI_MCR_ROOE (uint32_t)0x01000000 // 1311 #define SPI_MCR_ROOE (uint32_t)0x01000000 //
1312 #define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) // 1312 #define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) //
1313 #define SPI_MCR_DOZE (uint32_t)0x00008000 // 1313 #define SPI_MCR_DOZE (uint32_t)0x00008000 //
1314 #define SPI_MCR_MDIS (uint32_t)0x00004000 // 1314 #define SPI_MCR_MDIS (uint32_t)0x00004000 //
1315 #define SPI_MCR_DIS_TXF (uint32_t)0x00002000 // 1315 #define SPI_MCR_DIS_TXF (uint32_t)0x00002000 //
1316 #define SPI_MCR_DIS_RXF (uint32_t)0x00001000 // 1316 #define SPI_MCR_DIS_RXF (uint32_t)0x00001000 //
1317 #define SPI_MCR_CLR_TXF (uint32_t)0x00000800 // 1317 #define SPI_MCR_CLR_TXF (uint32_t)0x00000800 //
1318 #define SPI_MCR_CLR_RXF (uint32_t)0x00000400 // 1318 #define SPI_MCR_CLR_RXF (uint32_t)0x00000400 //
1319 #define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) // 1319 #define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) //
1320 #define SPI_MCR_HALT (uint32_t)0x00000001 // 1320 #define SPI_MCR_HALT (uint32_t)0x00000001 //
1321 #define SPI0_TCR *(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register 1321 #define SPI0_TCR *(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register
1322 #define SPI0_CTAR0 *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode 1322 #define SPI0_CTAR0 *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode
1323 #define SPI_CTAR_DBR (uint32_t)0x80000000 // Double Baud Rate 1323 #define SPI_CTAR_DBR (uint32_t)0x80000000 // Double Baud Rate
1324 #define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1) 1324 #define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1)
1325 #define SPI_CTAR_CPOL (uint32_t)0x04000000 // Clock Polarity 1325 #define SPI_CTAR_CPOL (uint32_t)0x04000000 // Clock Polarity
1326 #define SPI_CTAR_CPHA (uint32_t)0x02000000 // Clock Phase 1326 #define SPI_CTAR_CPHA (uint32_t)0x02000000 // Clock Phase
1327 #define SPI_CTAR_LSBFE (uint32_t)0x01000000 // LSB First 1327 #define SPI_CTAR_LSBFE (uint32_t)0x01000000 // LSB First
1328 #define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler 1328 #define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler
1329 #define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler 1329 #define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler
1330 #define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler 1330 #define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler
1331 #define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler 1331 #define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler
1332 #define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler 1332 #define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler
1333 #define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler 1333 #define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler
1334 #define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler 1334 #define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler
1335 #define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler 1335 #define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler
1336 #define SPI0_CTAR0_SLAVE *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode 1336 #define SPI0_CTAR0_SLAVE *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode
1337 #define SPI0_CTAR1 *(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode 1337 #define SPI0_CTAR1 *(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode
1338 #define SPI0_SR *(volatile uint32_t *)0x4002C02C // DSPI Status Register 1338 #define SPI0_SR *(volatile uint32_t *)0x4002C02C // DSPI Status Register
1339 #define SPI_SR_TCF (uint32_t)0x80000000 // Transfer Complete Flag 1339 #define SPI_SR_TCF (uint32_t)0x80000000 // Transfer Complete Flag
1340 #define SPI_SR_TXRXS (uint32_t)0x40000000 // TX and RX Status 1340 #define SPI_SR_TXRXS (uint32_t)0x40000000 // TX and RX Status
1341 #define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag 1341 #define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag
1342 #define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag 1342 #define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag
1343 #define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag 1343 #define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag
1344 #define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag 1344 #define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag
1345 #define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag 1345 #define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag
1346 #define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register 1346 #define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register
1347 #define SPI_RSER_TCF_RE (uint32_t)0x80000000 // Transmission Complete Request Enable 1347 #define SPI_RSER_TCF_RE (uint32_t)0x80000000 // Transmission Complete Request Enable
1348 #define SPI_RSER_EOQF_RE (uint32_t)0x10000000 // DSPI Finished Request Request Enable 1348 #define SPI_RSER_EOQF_RE (uint32_t)0x10000000 // DSPI Finished Request Request Enable
1349 #define SPI_RSER_TFUF_RE (uint32_t)0x08000000 // Transmit FIFO Underflow Request Enable 1349 #define SPI_RSER_TFUF_RE (uint32_t)0x08000000 // Transmit FIFO Underflow Request Enable
1350 #define SPI_RSER_TFFF_RE (uint32_t)0x02000000 // Transmit FIFO Fill Request Enable 1350 #define SPI_RSER_TFFF_RE (uint32_t)0x02000000 // Transmit FIFO Fill Request Enable
1351 #define SPI_RSER_TFFF_DIRS (uint32_t)0x01000000 // Transmit FIFO FIll Dma or Interrupt Request Select 1351 #define SPI_RSER_TFFF_DIRS (uint32_t)0x01000000 // Transmit FIFO FIll Dma or Interrupt Request Select
1352 #define SPI_RSER_RFOF_RE (uint32_t)0x00080000 // Receive FIFO Overflow Request Enable 1352 #define SPI_RSER_RFOF_RE (uint32_t)0x00080000 // Receive FIFO Overflow Request Enable
1353 #define SPI_RSER_RFDF_RE (uint32_t)0x00020000 // Receive FIFO Drain Request Enable 1353 #define SPI_RSER_RFDF_RE (uint32_t)0x00020000 // Receive FIFO Drain Request Enable
1354 #define SPI_RSER_RFDF_DIRS (uint32_t)0x00010000 // Receive FIFO Drain DMA or Interrupt Request Select 1354 #define SPI_RSER_RFDF_DIRS (uint32_t)0x00010000 // Receive FIFO Drain DMA or Interrupt Request Select
1355 #define SPI0_PUSHR *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode 1355 #define SPI0_PUSHR *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode
1356 #define SPI_PUSHR_CONT (uint32_t)0x80000000 // 1356 #define SPI_PUSHR_CONT (uint32_t)0x80000000 //
1357 #define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) // 1357 #define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) //
1358 #define SPI_PUSHR_EOQ (uint32_t)0x08000000 // 1358 #define SPI_PUSHR_EOQ (uint32_t)0x08000000 //
1359 #define SPI_PUSHR_CTCNT (uint32_t)0x04000000 // 1359 #define SPI_PUSHR_CTCNT (uint32_t)0x04000000 //
1360 #define SPI_PUSHR_PCS(n) (((n) & 31) << 16) // 1360 #define SPI_PUSHR_PCS(n) (((n) & 31) << 16) //
1361 #define SPI0_PUSHR_SLAVE *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode 1361 #define SPI0_PUSHR_SLAVE *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode
1362 #define SPI0_POPR *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register 1362 #define SPI0_POPR *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register
1363 #define SPI0_TXFR0 *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers 1363 #define SPI0_TXFR0 *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers
1364 #define SPI0_TXFR1 *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers 1364 #define SPI0_TXFR1 *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers
1365 #define SPI0_TXFR2 *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers 1365 #define SPI0_TXFR2 *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers
1366 #define SPI0_TXFR3 *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers 1366 #define SPI0_TXFR3 *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers
1367 #define SPI0_RXFR0 *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers 1367 #define SPI0_RXFR0 *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers
1368 #define SPI0_RXFR1 *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers 1368 #define SPI0_RXFR1 *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers
1369 #define SPI0_RXFR2 *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers 1369 #define SPI0_RXFR2 *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers
1370 #define SPI0_RXFR3 *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers 1370 #define SPI0_RXFR3 *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers
1371 typedef struct { 1371 typedef struct {
1372 volatile uint32_t MCR; // 0 1372 volatile uint32_t MCR; // 0
1373 volatile uint32_t unused1;// 4 1373 volatile uint32_t unused1;// 4
1374 volatile uint32_t TCR; // 8 1374 volatile uint32_t TCR; // 8
1375 volatile uint32_t CTAR0; // c 1375 volatile uint32_t CTAR0; // c
1376 volatile uint32_t CTAR1; // 10 1376 volatile uint32_t CTAR1; // 10
1377 volatile uint32_t CTAR2; // 14 1377 volatile uint32_t CTAR2; // 14
1378 volatile uint32_t CTAR3; // 18 1378 volatile uint32_t CTAR3; // 18
1379 volatile uint32_t CTAR4; // 1c 1379 volatile uint32_t CTAR4; // 1c
1380 volatile uint32_t CTAR5; // 20 1380 volatile uint32_t CTAR5; // 20
1381 volatile uint32_t CTAR6; // 24 1381 volatile uint32_t CTAR6; // 24
1382 volatile uint32_t CTAR7; // 28 1382 volatile uint32_t CTAR7; // 28
1383 volatile uint32_t SR; // 2c 1383 volatile uint32_t SR; // 2c
1384 volatile uint32_t RSER; // 30 1384 volatile uint32_t RSER; // 30
1385 volatile uint32_t PUSHR; // 34 1385 volatile uint32_t PUSHR; // 34
1386 volatile uint32_t POPR; // 38 1386 volatile uint32_t POPR; // 38
1387 volatile uint32_t TXFR[16]; // 3c 1387 volatile uint32_t TXFR[16]; // 3c
1388 volatile uint32_t RXFR[16]; // 7c 1388 volatile uint32_t RXFR[16]; // 7c
1389 } SPI_t; 1389 } SPI_t;
1390 #define SPI0 (*(SPI_t *)0x4002C000) 1390 #define SPI0 (*(SPI_t *)0x4002C000)
1391 1391
1392 // Chapter 44: Inter-Integrated Circuit (I2C) 1392 // Chapter 44: Inter-Integrated Circuit (I2C)
1393 #define I2C0_A1 *(volatile uint8_t *)0x40066000 // I2C Address Register 1 1393 #define I2C0_A1 *(volatile uint8_t *)0x40066000 // I2C Address Register 1
1394 #define I2C0_F *(volatile uint8_t *)0x40066001 // I2C Frequency Divider register 1394 #define I2C0_F *(volatile uint8_t *)0x40066001 // I2C Frequency Divider register
1395 #define I2C0_C1 *(volatile uint8_t *)0x40066002 // I2C Control Register 1 1395 #define I2C0_C1 *(volatile uint8_t *)0x40066002 // I2C Control Register 1
1396 #define I2C_C1_IICEN (uint8_t)0x80 // I2C Enable 1396 #define I2C_C1_IICEN (uint8_t)0x80 // I2C Enable
1397 #define I2C_C1_IICIE (uint8_t)0x40 // I2C Interrupt Enable 1397 #define I2C_C1_IICIE (uint8_t)0x40 // I2C Interrupt Enable
1398 #define I2C_C1_MST (uint8_t)0x20 // Master Mode Select 1398 #define I2C_C1_MST (uint8_t)0x20 // Master Mode Select
1399 #define I2C_C1_TX (uint8_t)0x10 // Transmit Mode Select 1399 #define I2C_C1_TX (uint8_t)0x10 // Transmit Mode Select
1400 #define I2C_C1_TXAK (uint8_t)0x08 // Transmit Acknowledge Enable 1400 #define I2C_C1_TXAK (uint8_t)0x08 // Transmit Acknowledge Enable
1401 #define I2C_C1_RSTA (uint8_t)0x04 // Repeat START 1401 #define I2C_C1_RSTA (uint8_t)0x04 // Repeat START
1402 #define I2C_C1_WUEN (uint8_t)0x02 // Wakeup Enable 1402 #define I2C_C1_WUEN (uint8_t)0x02 // Wakeup Enable
1403 #define I2C_C1_DMAEN (uint8_t)0x01 // DMA Enable 1403 #define I2C_C1_DMAEN (uint8_t)0x01 // DMA Enable
1404 #define I2C0_S *(volatile uint8_t *)0x40066003 // I2C Status register 1404 #define I2C0_S *(volatile uint8_t *)0x40066003 // I2C Status register
1405 #define I2C_S_TCF (uint8_t)0x80 // Transfer Complete Flag 1405 #define I2C_S_TCF (uint8_t)0x80 // Transfer Complete Flag
1406 #define I2C_S_IAAS (uint8_t)0x40 // Addressed As A Slave 1406 #define I2C_S_IAAS (uint8_t)0x40 // Addressed As A Slave
1407 #define I2C_S_BUSY (uint8_t)0x20 // Bus Busy 1407 #define I2C_S_BUSY (uint8_t)0x20 // Bus Busy
1408 #define I2C_S_ARBL (uint8_t)0x10 // Arbitration Lost 1408 #define I2C_S_ARBL (uint8_t)0x10 // Arbitration Lost
1409 #define I2C_S_RAM (uint8_t)0x08 // Range Address Match 1409 #define I2C_S_RAM (uint8_t)0x08 // Range Address Match
1410 #define I2C_S_SRW (uint8_t)0x04 // Slave Read/Write 1410 #define I2C_S_SRW (uint8_t)0x04 // Slave Read/Write
1411 #define I2C_S_IICIF (uint8_t)0x02 // Interrupt Flag 1411 #define I2C_S_IICIF (uint8_t)0x02 // Interrupt Flag
1412 #define I2C_S_RXAK (uint8_t)0x01 // Receive Acknowledge 1412 #define I2C_S_RXAK (uint8_t)0x01 // Receive Acknowledge
1413 #define I2C0_D *(volatile uint8_t *)0x40066004 // I2C Data I/O register 1413 #define I2C0_D *(volatile uint8_t *)0x40066004 // I2C Data I/O register
1414 #define I2C0_C2 *(volatile uint8_t *)0x40066005 // I2C Control Register 2 1414 #define I2C0_C2 *(volatile uint8_t *)0x40066005 // I2C Control Register 2
1415 #define I2C_C2_GCAEN (uint8_t)0x80 // General Call Address Enable 1415 #define I2C_C2_GCAEN (uint8_t)0x80 // General Call Address Enable
1416 #define I2C_C2_ADEXT (uint8_t)0x40 // Address Extension 1416 #define I2C_C2_ADEXT (uint8_t)0x40 // Address Extension
1417 #define I2C_C2_HDRS (uint8_t)0x20 // High Drive Select 1417 #define I2C_C2_HDRS (uint8_t)0x20 // High Drive Select
1418 #define I2C_C2_SBRC (uint8_t)0x10 // Slave Baud Rate Control 1418 #define I2C_C2_SBRC (uint8_t)0x10 // Slave Baud Rate Control
1419 #define I2C_C2_RMEN (uint8_t)0x08 // Range Address Matching Enable 1419 #define I2C_C2_RMEN (uint8_t)0x08 // Range Address Matching Enable
1420 #define I2C_C2_AD(n) ((n) & 7) // Slave Address, upper 3 bits 1420 #define I2C_C2_AD(n) ((n) & 7) // Slave Address, upper 3 bits
1421 #define I2C0_FLT *(volatile uint8_t *)0x40066006 // I2C Programmable Input Glitch Filter register 1421 #define I2C0_FLT *(volatile uint8_t *)0x40066006 // I2C Programmable Input Glitch Filter register
1422 #define I2C0_RA *(volatile uint8_t *)0x40066007 // I2C Range Address register 1422 #define I2C0_RA *(volatile uint8_t *)0x40066007 // I2C Range Address register
1423 #define I2C0_SMB *(volatile uint8_t *)0x40066008 // I2C SMBus Control and Status register 1423 #define I2C0_SMB *(volatile uint8_t *)0x40066008 // I2C SMBus Control and Status register
1424 #define I2C0_A2 *(volatile uint8_t *)0x40066009 // I2C Address Register 2 1424 #define I2C0_A2 *(volatile uint8_t *)0x40066009 // I2C Address Register 2
1425 #define I2C0_SLTH *(volatile uint8_t *)0x4006600A // I2C SCL Low Timeout Register High 1425 #define I2C0_SLTH *(volatile uint8_t *)0x4006600A // I2C SCL Low Timeout Register High
1427 1427
1428 // Chapter 45: Universal Asynchronous Receiver/Transmitter (UART) 1428 // Chapter 45: Universal Asynchronous Receiver/Transmitter (UART)
1429 #define UART0_BDH *(volatile uint8_t *)0x4006A000 // UART Baud Rate Registers: High 1429 #define UART0_BDH *(volatile uint8_t *)0x4006A000 // UART Baud Rate Registers: High
1430 #define UART0_BDL *(volatile uint8_t *)0x4006A001 // UART Baud Rate Registers: Low 1430 #define UART0_BDL *(volatile uint8_t *)0x4006A001 // UART Baud Rate Registers: Low
1431 #define UART0_C1 *(volatile uint8_t *)0x4006A002 // UART Control Register 1 1431 #define UART0_C1 *(volatile uint8_t *)0x4006A002 // UART Control Register 1
1432 #define UART_C1_LOOPS (uint8_t)0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input 1432 #define UART_C1_LOOPS (uint8_t)0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input
1433 #define UART_C1_UARTSWAI (uint8_t)0x40 // UART Stops in Wait Mode 1433 #define UART_C1_UARTSWAI (uint8_t)0x40 // UART Stops in Wait Mode
1434 #define UART_C1_RSRC (uint8_t)0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input 1434 #define UART_C1_RSRC (uint8_t)0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input
1435 #define UART_C1_M (uint8_t)0x10 // 9-bit or 8-bit Mode Select 1435 #define UART_C1_M (uint8_t)0x10 // 9-bit or 8-bit Mode Select
1436 #define UART_C1_WAKE (uint8_t)0x08 // Determines which condition wakes the UART 1436 #define UART_C1_WAKE (uint8_t)0x08 // Determines which condition wakes the UART
1437 #define UART_C1_ILT (uint8_t)0x04 // Idle Line Type Select 1437 #define UART_C1_ILT (uint8_t)0x04 // Idle Line Type Select
1438 #define UART_C1_PE (uint8_t)0x02 // Parity Enable 1438 #define UART_C1_PE (uint8_t)0x02 // Parity Enable
1439 #define UART_C1_PT (uint8_t)0x01 // Parity Type, 0=even, 1=odd 1439 #define UART_C1_PT (uint8_t)0x01 // Parity Type, 0=even, 1=odd
1440 #define UART0_C2 *(volatile uint8_t *)0x4006A003 // UART Control Register 2 1440 #define UART0_C2 *(volatile uint8_t *)0x4006A003 // UART Control Register 2
1441 #define UART_C2_TIE (uint8_t)0x80 // Transmitter Interrupt or DMA Transfer Enable. 1441 #define UART_C2_TIE (uint8_t)0x80 // Transmitter Interrupt or DMA Transfer Enable.
1442 #define UART_C2_TCIE (uint8_t)0x40 // Transmission Complete Interrupt Enable 1442 #define UART_C2_TCIE (uint8_t)0x40 // Transmission Complete Interrupt Enable
1443 #define UART_C2_RIE (uint8_t)0x20 // Receiver Full Interrupt or DMA Transfer Enable 1443 #define UART_C2_RIE (uint8_t)0x20 // Receiver Full Interrupt or DMA Transfer Enable
1444 #define UART_C2_ILIE (uint8_t)0x10 // Idle Line Interrupt Enable 1444 #define UART_C2_ILIE (uint8_t)0x10 // Idle Line Interrupt Enable
1445 #define UART_C2_TE (uint8_t)0x08 // Transmitter Enable 1445 #define UART_C2_TE (uint8_t)0x08 // Transmitter Enable
1446 #define UART_C2_RE (uint8_t)0x04 // Receiver Enable 1446 #define UART_C2_RE (uint8_t)0x04 // Receiver Enable
1447 #define UART_C2_RWU (uint8_t)0x02 // Receiver Wakeup Control 1447 #define UART_C2_RWU (uint8_t)0x02 // Receiver Wakeup Control
1448 #define UART_C2_SBK (uint8_t)0x01 // Send Break 1448 #define UART_C2_SBK (uint8_t)0x01 // Send Break
1449 #define UART0_S1 *(volatile uint8_t *)0x4006A004 // UART Status Register 1 1449 #define UART0_S1 *(volatile uint8_t *)0x4006A004 // UART Status Register 1
1450 #define UART_S1_TDRE (uint8_t)0x80 // Transmit Data Register Empty Flag 1450 #define UART_S1_TDRE (uint8_t)0x80 // Transmit Data Register Empty Flag
1451 #define UART_S1_TC (uint8_t)0x40 // Transmit Complete Flag 1451 #define UART_S1_TC (uint8_t)0x40 // Transmit Complete Flag
1452 #define UART_S1_RDRF (uint8_t)0x20 // Receive Data Register Full Flag 1452 #define UART_S1_RDRF (uint8_t)0x20 // Receive Data Register Full Flag
1453 #define UART_S1_IDLE (uint8_t)0x10 // Idle Line Flag 1453 #define UART_S1_IDLE (uint8_t)0x10 // Idle Line Flag
1454 #define UART_S1_OR (uint8_t)0x08 // Receiver Overrun Flag 1454 #define UART_S1_OR (uint8_t)0x08 // Receiver Overrun Flag
1455 #define UART_S1_NF (uint8_t)0x04 // Noise Flag 1455 #define UART_S1_NF (uint8_t)0x04 // Noise Flag
1456 #define UART_S1_FE (uint8_t)0x02 // Framing Error Flag 1456 #define UART_S1_FE (uint8_t)0x02 // Framing Error Flag
1457 #define UART_S1_PF (uint8_t)0x01 // Parity Error Flag 1457 #define UART_S1_PF (uint8_t)0x01 // Parity Error Flag
1458 #define UART0_S2 *(volatile uint8_t *)0x4006A005 // UART Status Register 2 1458 #define UART0_S2 *(volatile uint8_t *)0x4006A005 // UART Status Register 2
1459 #define UART0_C3 *(volatile uint8_t *)0x4006A006 // UART Control Register 3 1459 #define UART0_C3 *(volatile uint8_t *)0x4006A006 // UART Control Register 3
1460 #define UART0_D *(volatile uint8_t *)0x4006A007 // UART Data Register 1460 #define UART0_D *(volatile uint8_t *)0x4006A007 // UART Data Register
1461 #define UART0_MA1 *(volatile uint8_t *)0x4006A008 // UART Match Address Registers 1 1461 #define UART0_MA1 *(volatile uint8_t *)0x4006A008 // UART Match Address Registers 1
1462 #define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2 1462 #define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2
1463 #define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4 1463 #define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4
1464 #define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5 1464 #define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5
1465 #define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register 1465 #define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register
1466 #define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register 1466 #define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register
1467 #define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register 1467 #define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register
1468 #define UART0_PFIFO *(volatile uint8_t *)0x4006A010 // UART FIFO Parameters 1468 #define UART0_PFIFO *(volatile uint8_t *)0x4006A010 // UART FIFO Parameters
1469 #define UART_PFIFO_TXFE (uint8_t)0x80 1469 #define UART_PFIFO_TXFE (uint8_t)0x80
1470 #define UART_PFIFO_TXFIFOSIZE (uint8_t)0x70 1470 #define UART_PFIFO_TXFIFOSIZE (uint8_t)0x70
1471 #define UART_PFIFO_RXFE (uint8_t)0x08 1471 #define UART_PFIFO_RXFE (uint8_t)0x08
1472 #define UART_PFIFO_RXFIFOSIZE (uint8_t)0x07 1472 #define UART_PFIFO_RXFIFOSIZE (uint8_t)0x07
1473 #define UART0_CFIFO *(volatile uint8_t *)0x4006A011 // UART FIFO Control Register 1473 #define UART0_CFIFO *(volatile uint8_t *)0x4006A011 // UART FIFO Control Register
1474 #define UART_CFIFO_TXFLUSH (uint8_t)0x80 // 1474 #define UART_CFIFO_TXFLUSH (uint8_t)0x80 //
1475 #define UART_CFIFO_RXFLUSH (uint8_t)0x40 // 1475 #define UART_CFIFO_RXFLUSH (uint8_t)0x40 //
1476 #define UART_CFIFO_RXOFE (uint8_t)0x04 // 1476 #define UART_CFIFO_RXOFE (uint8_t)0x04 //
1477 #define UART_CFIFO_TXOFE (uint8_t)0x02 // 1477 #define UART_CFIFO_TXOFE (uint8_t)0x02 //
1478 #define UART_CFIFO_RXUFE (uint8_t)0x01 // 1478 #define UART_CFIFO_RXUFE (uint8_t)0x01 //
1479 #define UART0_SFIFO *(volatile uint8_t *)0x4006A012 // UART FIFO Status Register 1479 #define UART0_SFIFO *(volatile uint8_t *)0x4006A012 // UART FIFO Status Register
1480 #define UART_SFIFO_TXEMPT (uint8_t)0x80 1480 #define UART_SFIFO_TXEMPT (uint8_t)0x80
1481 #define UART_SFIFO_RXEMPT (uint8_t)0x40 1481 #define UART_SFIFO_RXEMPT (uint8_t)0x40
1482 #define UART_SFIFO_RXOF (uint8_t)0x04 1482 #define UART_SFIFO_RXOF (uint8_t)0x04
1483 #define UART_SFIFO_TXOF (uint8_t)0x02 1483 #define UART_SFIFO_TXOF (uint8_t)0x02
1484 #define UART_SFIFO_RXUF (uint8_t)0x01 1484 #define UART_SFIFO_RXUF (uint8_t)0x01
1485 #define UART0_TWFIFO *(volatile uint8_t *)0x4006A013 // UART FIFO Transmit Watermark 1485 #define UART0_TWFIFO *(volatile uint8_t *)0x4006A013 // UART FIFO Transmit Watermark
1486 #define UART0_TCFIFO *(volatile uint8_t *)0x4006A014 // UART FIFO Transmit Count 1486 #define UART0_TCFIFO *(volatile uint8_t *)0x4006A014 // UART FIFO Transmit Count
1487 #define UART0_RWFIFO *(volatile uint8_t *)0x4006A015 // UART FIFO Receive Watermark 1487 #define UART0_RWFIFO *(volatile uint8_t *)0x4006A015 // UART FIFO Receive Watermark
1488 #define UART0_RCFIFO *(volatile uint8_t *)0x4006A016 // UART FIFO Receive Count 1488 #define UART0_RCFIFO *(volatile uint8_t *)0x4006A016 // UART FIFO Receive Count
1489 #define UART0_C7816 *(volatile uint8_t *)0x4006A018 // UART 7816 Control Register 1489 #define UART0_C7816 *(volatile uint8_t *)0x4006A018 // UART 7816 Control Register
1608 #define UART2_CPW *(volatile uint8_t *)0x4006C02F // UART CEA709.1-B Collision Pulse Width 1608 #define UART2_CPW *(volatile uint8_t *)0x4006C02F // UART CEA709.1-B Collision Pulse Width
1609 #define UART2_RIDT *(volatile uint8_t *)0x4006C030 // UART CEA709.1-B Receive Indeterminate Time 1609 #define UART2_RIDT *(volatile uint8_t *)0x4006C030 // UART CEA709.1-B Receive Indeterminate Time
1610 #define UART2_TIDT *(volatile uint8_t *)0x4006C031 // UART CEA709.1-B Transmit Indeterminate Time 1610 #define UART2_TIDT *(volatile uint8_t *)0x4006C031 // UART CEA709.1-B Transmit Indeterminate Time
1611 1611
1612 // Chapter 46: Synchronous Audio Interface (SAI) 1612 // Chapter 46: Synchronous Audio Interface (SAI)
1613 #define I2S0_TCSR *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register 1613 #define I2S0_TCSR *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register
1614 #define I2S_TCSR_TE (uint32_t)0x80000000 // Transmitter Enable 1614 #define I2S_TCSR_TE (uint32_t)0x80000000 // Transmitter Enable
1615 #define I2S_TCSR_STOPE (uint32_t)0x40000000 // Transmitter Enable in Stop mode 1615 #define I2S_TCSR_STOPE (uint32_t)0x40000000 // Transmitter Enable in Stop mode
1616 #define I2S_TCSR_DBGE (uint32_t)0x20000000 // Transmitter Enable in Debug mode 1616 #define I2S_TCSR_DBGE (uint32_t)0x20000000 // Transmitter Enable in Debug mode
1617 #define I2S_TCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable 1617 #define I2S_TCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable
1618 #define I2S_TCSR_FR (uint32_t)0x02000000 // FIFO Reset 1618 #define I2S_TCSR_FR (uint32_t)0x02000000 // FIFO Reset
1619 #define I2S_TCSR_SR (uint32_t)0x01000000 // Software Reset 1619 #define I2S_TCSR_SR (uint32_t)0x01000000 // Software Reset
1620 #define I2S_TCSR_WSF (uint32_t)0x00100000 // Word Start Flag 1620 #define I2S_TCSR_WSF (uint32_t)0x00100000 // Word Start Flag
1621 #define I2S_TCSR_SEF (uint32_t)0x00080000 // Sync Error Flag 1621 #define I2S_TCSR_SEF (uint32_t)0x00080000 // Sync Error Flag
1622 #define I2S_TCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun) 1622 #define I2S_TCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun)
1623 #define I2S_TCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty) 1623 #define I2S_TCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty)
1624 #define I2S_TCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready) 1624 #define I2S_TCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready)
1625 #define I2S_TCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable 1625 #define I2S_TCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable
1626 #define I2S_TCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable 1626 #define I2S_TCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable
1627 #define I2S_TCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable 1627 #define I2S_TCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable
1628 #define I2S_TCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable 1628 #define I2S_TCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable
1629 #define I2S_TCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable 1629 #define I2S_TCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable
1630 #define I2S_TCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable 1630 #define I2S_TCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable
1631 #define I2S_TCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable 1631 #define I2S_TCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable
1632 #define I2S0_TCR1 *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register 1632 #define I2S0_TCR1 *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register
1633 #define I2S_TCR1_TFW(n) ((uint32_t)n & 0x03) // Transmit FIFO watermark 1633 #define I2S_TCR1_TFW(n) ((uint32_t)n & 0x03) // Transmit FIFO watermark
1634 #define I2S0_TCR2 *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register 1634 #define I2S0_TCR2 *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register
1635 #define I2S_TCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2 1635 #define I2S_TCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
1636 #define I2S_TCR2_BCD ((uint32_t)1<<24) // Bit clock direction 1636 #define I2S_TCR2_BCD ((uint32_t)1<<24) // Bit clock direction
1637 #define I2S_TCR2_BCP ((uint32_t)1<<25) // Bit clock polarity 1637 #define I2S_TCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
1638 #define I2S_TCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK 1638 #define I2S_TCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
1639 #define I2S_TCR2_BCI ((uint32_t)1<<28) // Bit clock input 1639 #define I2S_TCR2_BCI ((uint32_t)1<<28) // Bit clock input
1640 #define I2S_TCR2_BCS ((uint32_t)1<<29) // Bit clock swap 1640 #define I2S_TCR2_BCS ((uint32_t)1<<29) // Bit clock swap
1641 #define I2S_TCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver 1641 #define I2S_TCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
1642 #define I2S0_TCR3 *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register 1642 #define I2S0_TCR3 *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register
1643 #define I2S_TCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration 1643 #define I2S_TCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
1644 #define I2S_TCR3_TCE ((uint32_t)0x10000) // transmit channel enable 1644 #define I2S_TCR3_TCE ((uint32_t)0x10000) // transmit channel enable
1645 #define I2S0_TCR4 *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register 1645 #define I2S0_TCR4 *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register
1646 #define I2S_TCR4_FSD ((uint32_t)1) // Frame Sync Direction 1646 #define I2S_TCR4_FSD ((uint32_t)1) // Frame Sync Direction
1647 #define I2S_TCR4_FSP ((uint32_t)2) // Frame Sync Polarity 1647 #define I2S_TCR4_FSP ((uint32_t)2) // Frame Sync Polarity
1648 #define I2S_TCR4_FSE ((uint32_t)8) // Frame Sync Early 1648 #define I2S_TCR4_FSE ((uint32_t)8) // Frame Sync Early
1649 #define I2S_TCR4_MF ((uint32_t)0x10) // MSB First 1649 #define I2S_TCR4_MF ((uint32_t)0x10) // MSB First
1650 #define I2S_TCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width 1650 #define I2S_TCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
1651 #define I2S_TCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size 1651 #define I2S_TCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
1652 #define I2S0_TCR5 *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register 1652 #define I2S0_TCR5 *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register
1653 #define I2S_TCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted 1653 #define I2S_TCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
1654 #define I2S_TCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width 1654 #define I2S_TCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
1655 #define I2S_TCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width 1655 #define I2S_TCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
1656 #define I2S0_TDR0 *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register 1656 #define I2S0_TDR0 *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register
1657 #define I2S0_TFR0 *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register 1657 #define I2S0_TFR0 *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register
1658 #define I2S_TFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer 1658 #define I2S_TFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
1659 #define I2S_TFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer 1659 #define I2S_TFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
1660 #define I2S0_TMR *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register 1660 #define I2S0_TMR *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register
1661 #define I2S_TMR_TWM(n) ((uint32_t)n & 0xFFFFFFFF) 1661 #define I2S_TMR_TWM(n) ((uint32_t)n & 0xFFFFFFFF)
1662 #define I2S0_RCSR *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register 1662 #define I2S0_RCSR *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register
1663 #define I2S_RCSR_RE (uint32_t)0x80000000 // Receiver Enable 1663 #define I2S_RCSR_RE (uint32_t)0x80000000 // Receiver Enable
1664 #define I2S_RCSR_STOPE (uint32_t)0x40000000 // Receiver Enable in Stop mode 1664 #define I2S_RCSR_STOPE (uint32_t)0x40000000 // Receiver Enable in Stop mode
1665 #define I2S_RCSR_DBGE (uint32_t)0x20000000 // Receiver Enable in Debug mode 1665 #define I2S_RCSR_DBGE (uint32_t)0x20000000 // Receiver Enable in Debug mode
1666 #define I2S_RCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable 1666 #define I2S_RCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable
1667 #define I2S_RCSR_FR (uint32_t)0x02000000 // FIFO Reset 1667 #define I2S_RCSR_FR (uint32_t)0x02000000 // FIFO Reset
1668 #define I2S_RCSR_SR (uint32_t)0x01000000 // Software Reset 1668 #define I2S_RCSR_SR (uint32_t)0x01000000 // Software Reset
1669 #define I2S_RCSR_WSF (uint32_t)0x00100000 // Word Start Flag 1669 #define I2S_RCSR_WSF (uint32_t)0x00100000 // Word Start Flag
1670 #define I2S_RCSR_SEF (uint32_t)0x00080000 // Sync Error Flag 1670 #define I2S_RCSR_SEF (uint32_t)0x00080000 // Sync Error Flag
1671 #define I2S_RCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun) 1671 #define I2S_RCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun)
1672 #define I2S_RCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty) 1672 #define I2S_RCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty)
1673 #define I2S_RCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready) 1673 #define I2S_RCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready)
1674 #define I2S_RCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable 1674 #define I2S_RCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable
1675 #define I2S_RCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable 1675 #define I2S_RCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable
1676 #define I2S_RCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable 1676 #define I2S_RCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable
1677 #define I2S_RCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable 1677 #define I2S_RCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable
1678 #define I2S_RCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable 1678 #define I2S_RCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable
1679 #define I2S_RCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable 1679 #define I2S_RCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable
1680 #define I2S_RCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable 1680 #define I2S_RCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable
1681 #define I2S0_RCR1 *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register 1681 #define I2S0_RCR1 *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register
1682 #define I2S_RCR1_RFW(n) ((uint32_t)n & 0x03) // Receive FIFO watermark 1682 #define I2S_RCR1_RFW(n) ((uint32_t)n & 0x03) // Receive FIFO watermark
1683 #define I2S0_RCR2 *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register 1683 #define I2S0_RCR2 *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register
1684 #define I2S_RCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2 1684 #define I2S_RCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
1685 #define I2S_RCR2_BCD ((uint32_t)1<<24) // Bit clock direction 1685 #define I2S_RCR2_BCD ((uint32_t)1<<24) // Bit clock direction
1686 #define I2S_RCR2_BCP ((uint32_t)1<<25) // Bit clock polarity 1686 #define I2S_RCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
1687 #define I2S_RCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK 1687 #define I2S_RCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
1688 #define I2S_RCR2_BCI ((uint32_t)1<<28) // Bit clock input 1688 #define I2S_RCR2_BCI ((uint32_t)1<<28) // Bit clock input
1689 #define I2S_RCR2_BCS ((uint32_t)1<<29) // Bit clock swap 1689 #define I2S_RCR2_BCS ((uint32_t)1<<29) // Bit clock swap
1690 #define I2S_RCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver 1690 #define I2S_RCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
1691 #define I2S0_RCR3 *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register 1691 #define I2S0_RCR3 *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register
1692 #define I2S_RCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration 1692 #define I2S_RCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
1693 #define I2S_RCR3_RCE ((uint32_t)0x10000) // receive channel enable 1693 #define I2S_RCR3_RCE ((uint32_t)0x10000) // receive channel enable
1694 #define I2S0_RCR4 *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register 1694 #define I2S0_RCR4 *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register
1695 #define I2S_RCR4_FSD ((uint32_t)1) // Frame Sync Direction 1695 #define I2S_RCR4_FSD ((uint32_t)1) // Frame Sync Direction
1696 #define I2S_RCR4_FSP ((uint32_t)2) // Frame Sync Polarity 1696 #define I2S_RCR4_FSP ((uint32_t)2) // Frame Sync Polarity
1697 #define I2S_RCR4_FSE ((uint32_t)8) // Frame Sync Early 1697 #define I2S_RCR4_FSE ((uint32_t)8) // Frame Sync Early
1698 #define I2S_RCR4_MF ((uint32_t)0x10) // MSB First 1698 #define I2S_RCR4_MF ((uint32_t)0x10) // MSB First
1699 #define I2S_RCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width 1699 #define I2S_RCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
1700 #define I2S_RCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size 1700 #define I2S_RCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
1701 #define I2S0_RCR5 *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register 1701 #define I2S0_RCR5 *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register
1702 #define I2S_RCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted 1702 #define I2S_RCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
1703 #define I2S_RCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width 1703 #define I2S_RCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
1704 #define I2S_RCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width 1704 #define I2S_RCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
1705 #define I2S0_RDR0 *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register 1705 #define I2S0_RDR0 *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register
1706 #define I2S0_RFR0 *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register 1706 #define I2S0_RFR0 *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register
1707 #define I2S_RFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer 1707 #define I2S_RFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
1708 #define I2S_RFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer 1708 #define I2S_RFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
1709 #define I2S0_RMR *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register 1709 #define I2S0_RMR *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register
1710 #define I2S_RMR_RWM(n) ((uint32_t)n & 0xFFFFFFFF) 1710 #define I2S_RMR_RWM(n) ((uint32_t)n & 0xFFFFFFFF)
1711 #define I2S0_MCR *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register 1711 #define I2S0_MCR *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register
1712 #define I2S_MCR_DUF ((uint32_t)1<<31) // Divider Update Flag 1712 #define I2S_MCR_DUF ((uint32_t)1<<31) // Divider Update Flag
1713 #define I2S_MCR_MOE ((uint32_t)1<<30) // MCLK Output Enable 1713 #define I2S_MCR_MOE ((uint32_t)1<<30) // MCLK Output Enable
1714 #define I2S_MCR_MICS(n) ((uint32_t)(n & 3)<<24) // MCLK Input Clock Select 1714 #define I2S_MCR_MICS(n) ((uint32_t)(n & 3)<<24) // MCLK Input Clock Select
1715 #define I2S0_MDR *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register 1715 #define I2S0_MDR *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register
1716 #define I2S_MDR_FRACT(n) ((uint32_t)(n & 0xff)<<12) // MCLK Fraction 1716 #define I2S_MDR_FRACT(n) ((uint32_t)(n & 0xff)<<12) // MCLK Fraction
1717 #define I2S_MDR_DIVIDE(n) ((uint32_t)(n & 0xfff)) // MCLK Divide 1717 #define I2S_MDR_DIVIDE(n) ((uint32_t)(n & 0xfff)) // MCLK Divide
1718 1718
1719 // Chapter 47: General-Purpose Input/Output (GPIO) 1719 // Chapter 47: General-Purpose Input/Output (GPIO)
1720 #define GPIOA_PDOR *(volatile uint32_t *)0x400FF000 // Port Data Output Register 1720 #define GPIOA_PDOR *(volatile uint32_t *)0x400FF000 // Port Data Output Register
1721 #define GPIOA_PSOR *(volatile uint32_t *)0x400FF004 // Port Set Output Register 1721 #define GPIOA_PSOR *(volatile uint32_t *)0x400FF004 // Port Set Output Register
1722 #define GPIOA_PCOR *(volatile uint32_t *)0x400FF008 // Port Clear Output Register 1722 #define GPIOA_PCOR *(volatile uint32_t *)0x400FF008 // Port Clear Output Register
1748 #define GPIOE_PDIR *(volatile uint32_t *)0x400FF110 // Port Data Input Register 1748 #define GPIOE_PDIR *(volatile uint32_t *)0x400FF110 // Port Data Input Register
1749 #define GPIOE_PDDR *(volatile uint32_t *)0x400FF114 // Port Data Direction Register 1749 #define GPIOE_PDDR *(volatile uint32_t *)0x400FF114 // Port Data Direction Register
1750 1750
1751 // Chapter 48: Touch sense input (TSI) 1751 // Chapter 48: Touch sense input (TSI)
1752 #define TSI0_GENCS *(volatile uint32_t *)0x40045000 // General Control and Status Register 1752 #define TSI0_GENCS *(volatile uint32_t *)0x40045000 // General Control and Status Register
1753 #define TSI_GENCS_LPCLKS (uint32_t)0x10000000 // 1753 #define TSI_GENCS_LPCLKS (uint32_t)0x10000000 //
1754 #define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) // 1754 #define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) //
1755 #define TSI_GENCS_NSCN(n) (((n) & 31) << 19) // 1755 #define TSI_GENCS_NSCN(n) (((n) & 31) << 19) //
1756 #define TSI_GENCS_PS(n) (((n) & 7) << 16) // 1756 #define TSI_GENCS_PS(n) (((n) & 7) << 16) //
1757 #define TSI_GENCS_EOSF (uint32_t)0x00008000 // 1757 #define TSI_GENCS_EOSF (uint32_t)0x00008000 //
1758 #define TSI_GENCS_OUTRGF (uint32_t)0x00004000 // 1758 #define TSI_GENCS_OUTRGF (uint32_t)0x00004000 //
1759 #define TSI_GENCS_EXTERF (uint32_t)0x00002000 // 1759 #define TSI_GENCS_EXTERF (uint32_t)0x00002000 //
1760 #define TSI_GENCS_OVRF (uint32_t)0x00001000 // 1760 #define TSI_GENCS_OVRF (uint32_t)0x00001000 //
1761 #define TSI_GENCS_SCNIP (uint32_t)0x00000200 // 1761 #define TSI_GENCS_SCNIP (uint32_t)0x00000200 //
1762 #define TSI_GENCS_SWTS (uint32_t)0x00000100 // 1762 #define TSI_GENCS_SWTS (uint32_t)0x00000100 //
1763 #define TSI_GENCS_TSIEN (uint32_t)0x00000080 // 1763 #define TSI_GENCS_TSIEN (uint32_t)0x00000080 //
1764 #define TSI_GENCS_TSIIE (uint32_t)0x00000040 // 1764 #define TSI_GENCS_TSIIE (uint32_t)0x00000040 //
1765 #define TSI_GENCS_ERIE (uint32_t)0x00000020 // 1765 #define TSI_GENCS_ERIE (uint32_t)0x00000020 //
1766 #define TSI_GENCS_ESOR (uint32_t)0x00000010 // 1766 #define TSI_GENCS_ESOR (uint32_t)0x00000010 //
1767 #define TSI_GENCS_STM (uint32_t)0x00000002 // 1767 #define TSI_GENCS_STM (uint32_t)0x00000002 //
1768 #define TSI_GENCS_STPE (uint32_t)0x00000001 // 1768 #define TSI_GENCS_STPE (uint32_t)0x00000001 //
1769 #define TSI0_SCANC *(volatile uint32_t *)0x40045004 // SCAN Control Register 1769 #define TSI0_SCANC *(volatile uint32_t *)0x40045004 // SCAN Control Register
1770 #define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) // 1770 #define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) //
1771 #define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) // 1771 #define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) //
1772 #define TSI_SCANC_SMOD(n) (((n) & 255) << 8) // 1772 #define TSI_SCANC_SMOD(n) (((n) & 255) << 8) //
1773 #define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) // 1773 #define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) //
1774 #define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) // 1774 #define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) //
1775 #define TSI0_PEN *(volatile uint32_t *)0x40045008 // Pin Enable Register 1775 #define TSI0_PEN *(volatile uint32_t *)0x40045008 // Pin Enable Register
1776 #define TSI0_WUCNTR *(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register 1776 #define TSI0_WUCNTR *(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register
1777 #define TSI0_CNTR1 *(volatile uint32_t *)0x40045100 // Counter Register 1777 #define TSI0_CNTR1 *(volatile uint32_t *)0x40045100 // Counter Register
1778 #define TSI0_CNTR3 *(volatile uint32_t *)0x40045104 // Counter Register 1778 #define TSI0_CNTR3 *(volatile uint32_t *)0x40045104 // Counter Register
1779 #define TSI0_CNTR5 *(volatile uint32_t *)0x40045108 // Counter Register 1779 #define TSI0_CNTR5 *(volatile uint32_t *)0x40045108 // Counter Register
1783 #define TSI0_CNTR13 *(volatile uint32_t *)0x40045118 // Counter Register 1783 #define TSI0_CNTR13 *(volatile uint32_t *)0x40045118 // Counter Register
1784 #define TSI0_CNTR15 *(volatile uint32_t *)0x4004511C // Counter Register 1784 #define TSI0_CNTR15 *(volatile uint32_t *)0x4004511C // Counter Register
1785 #define TSI0_THRESHOLD *(volatile uint32_t *)0x40045120 // Low Power Channel Threshold Register 1785 #define TSI0_THRESHOLD *(volatile uint32_t *)0x40045120 // Low Power Channel Threshold Register
1786 1786
1787 // Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750) 1787 // Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750)
1788 #define NVIC_ENABLE_IRQ(n) (*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31))) 1788 #define NVIC_ENABLE_IRQ(n) (*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31)))
1789 #define NVIC_DISABLE_IRQ(n) (*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31))) 1789 #define NVIC_DISABLE_IRQ(n) (*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31)))
1790 #define NVIC_SET_PENDING(n) (*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31))) 1790 #define NVIC_SET_PENDING(n) (*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31)))
1791 #define NVIC_CLEAR_PENDING(n) (*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31))) 1791 #define NVIC_CLEAR_PENDING(n) (*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31)))
1792 1792
1793 #define NVIC_ISER0 *(volatile uint32_t *)0xE000E100 1793 #define NVIC_ISER0 *(volatile uint32_t *)0xE000E100
1794 #define NVIC_ISER1 *(volatile uint32_t *)0xE000E104 1794 #define NVIC_ISER1 *(volatile uint32_t *)0xE000E104
1795 #define NVIC_ICER0 *(volatile uint32_t *)0xE000E180 1795 #define NVIC_ICER0 *(volatile uint32_t *)0xE000E180
1796 #define NVIC_ICER1 *(volatile uint32_t *)0xE000E184 1796 #define NVIC_ICER1 *(volatile uint32_t *)0xE000E184
1797 1797
1798 // 0 = highest priority 1798 // 0 = highest priority
1799 // Cortex-M4: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240 1799 // Cortex-M4: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240
1800 // Cortex-M0: 0,64,128,192 1800 // Cortex-M0: 0,64,128,192
1801 #define NVIC_SET_PRIORITY(irqnum, priority) (*((volatile uint8_t *)0xE000E400 + (irqnum)) = (uint8_t)(priority)) 1801 #define NVIC_SET_PRIORITY(irqnum, priority) (*((volatile uint8_t *)0xE000E400 + (irqnum)) = (uint8_t)(priority))
1802 #define NVIC_GET_PRIORITY(irqnum) (*((uint8_t *)0xE000E400 + (irqnum))) 1802 #define NVIC_GET_PRIORITY(irqnum) (*((uint8_t *)0xE000E400 + (irqnum)))
1803 1803
1804 #if defined(_mk20dx128_) || defined(_mk20dx128vlf5_) 1804 #if defined(_mk20dx128_) || defined(_mk20dx128vlf5_)
1805 #define IRQ_DMA_CH0 0 1805 #define IRQ_DMA_CH0 0
1806 #define IRQ_DMA_CH1 1 1806 #define IRQ_DMA_CH1 1
1807 #define IRQ_DMA_CH2 2 1807 #define IRQ_DMA_CH2 2
1808 #define IRQ_DMA_CH3 3 1808 #define IRQ_DMA_CH3 3
1809 #define IRQ_DMA_ERROR 4 1809 #define IRQ_DMA_ERROR 4
1810 #define IRQ_FTFL_COMPLETE 6 1810 #define IRQ_FTFL_COMPLETE 6
1811 #define IRQ_FTFL_COLLISION 7 1811 #define IRQ_FTFL_COLLISION 7
1812 #define IRQ_LOW_VOLTAGE 8 1812 #define IRQ_LOW_VOLTAGE 8
1813 #define IRQ_LLWU 9 1813 #define IRQ_LLWU 9
1814 #define IRQ_WDOG 10 1814 #define IRQ_WDOG 10
1815 #define IRQ_I2C0 11 1815 #define IRQ_I2C0 11
1816 #define IRQ_SPI0 12 1816 #define IRQ_SPI0 12
1817 #define IRQ_I2S0_TX 13 1817 #define IRQ_I2S0_TX 13
1818 #define IRQ_I2S0_RX 14 1818 #define IRQ_I2S0_RX 14
1819 #define IRQ_UART0_LON 15 1819 #define IRQ_UART0_LON 15
1820 #define IRQ_UART0_STATUS 16 1820 #define IRQ_UART0_STATUS 16
1821 #define IRQ_UART0_ERROR 17 1821 #define IRQ_UART0_ERROR 17
1822 #define IRQ_UART1_STATUS 18 1822 #define IRQ_UART1_STATUS 18
1823 #define IRQ_UART1_ERROR 19 1823 #define IRQ_UART1_ERROR 19
1824 #define IRQ_UART2_STATUS 20 1824 #define IRQ_UART2_STATUS 20
1825 #define IRQ_UART2_ERROR 21 1825 #define IRQ_UART2_ERROR 21
1826 #define IRQ_ADC0 22 1826 #define IRQ_ADC0 22
1827 #define IRQ_CMP0 23 1827 #define IRQ_CMP0 23
1828 #define IRQ_CMP1 24 1828 #define IRQ_CMP1 24
1829 #define IRQ_FTM0 25 1829 #define IRQ_FTM0 25
1830 #define IRQ_FTM1 26 1830 #define IRQ_FTM1 26
1831 #define IRQ_CMT 27 1831 #define IRQ_CMT 27
1832 #define IRQ_RTC_ALARM 28 1832 #define IRQ_RTC_ALARM 28
1833 #define IRQ_RTC_SECOND 29 1833 #define IRQ_RTC_SECOND 29
1834 #define IRQ_PIT_CH0 30 1834 #define IRQ_PIT_CH0 30
1835 #define IRQ_PIT_CH1 31 1835 #define IRQ_PIT_CH1 31
1836 #define IRQ_PIT_CH2 32 1836 #define IRQ_PIT_CH2 32
1837 #define IRQ_PIT_CH3 33 1837 #define IRQ_PIT_CH3 33
1838 #define IRQ_PDB 34 1838 #define IRQ_PDB 34
1839 #define IRQ_USBOTG 35 1839 #define IRQ_USBOTG 35
1840 #define IRQ_USBDCD 36 1840 #define IRQ_USBDCD 36
1841 #define IRQ_TSI 37 1841 #define IRQ_TSI 37
1842 #define IRQ_MCG 38 1842 #define IRQ_MCG 38
1843 #define IRQ_LPTMR 39 1843 #define IRQ_LPTMR 39
1844 #define IRQ_PORTA 40 1844 #define IRQ_PORTA 40
1845 #define IRQ_PORTB 41 1845 #define IRQ_PORTB 41
1846 #define IRQ_PORTC 42 1846 #define IRQ_PORTC 42
1847 #define IRQ_PORTD 43 1847 #define IRQ_PORTD 43
1848 #define IRQ_PORTE 44 1848 #define IRQ_PORTE 44
1849 #define IRQ_SOFTWARE 45 1849 #define IRQ_SOFTWARE 45
1850 #define NVIC_NUM_INTERRUPTS 46 1850 #define NVIC_NUM_INTERRUPTS 46
1851 1851
1852 #elif defined(_mk20dx256_) || defined(_mk20dx256vlh7_) 1852 #elif defined(_mk20dx256_) || defined(_mk20dx256vlh7_)
1853 #define IRQ_DMA_CH0 0 1853 #define IRQ_DMA_CH0 0
1854 #define IRQ_DMA_CH1 1 1854 #define IRQ_DMA_CH1 1
1855 #define IRQ_DMA_CH2 2 1855 #define IRQ_DMA_CH2 2
1856 #define IRQ_DMA_CH3 3 1856 #define IRQ_DMA_CH3 3
1857 #define IRQ_DMA_CH4 4 1857 #define IRQ_DMA_CH4 4
1858 #define IRQ_DMA_CH5 5 1858 #define IRQ_DMA_CH5 5
1859 #define IRQ_DMA_CH6 6 1859 #define IRQ_DMA_CH6 6
1860 #define IRQ_DMA_CH7 7 1860 #define IRQ_DMA_CH7 7
1861 #define IRQ_DMA_CH8 8 1861 #define IRQ_DMA_CH8 8
1862 #define IRQ_DMA_CH9 9 1862 #define IRQ_DMA_CH9 9
1863 #define IRQ_DMA_CH10 10 1863 #define IRQ_DMA_CH10 10
1864 #define IRQ_DMA_CH11 11 1864 #define IRQ_DMA_CH11 11
1865 #define IRQ_DMA_CH12 12 1865 #define IRQ_DMA_CH12 12
1866 #define IRQ_DMA_CH13 13 1866 #define IRQ_DMA_CH13 13
1867 #define IRQ_DMA_CH14 14 1867 #define IRQ_DMA_CH14 14
1868 #define IRQ_DMA_CH15 15 1868 #define IRQ_DMA_CH15 15
1869 #define IRQ_DMA_ERROR 16 1869 #define IRQ_DMA_ERROR 16
1870 #define IRQ_FTFL_COMPLETE 18 1870 #define IRQ_FTFL_COMPLETE 18
1871 #define IRQ_FTFL_COLLISION 19 1871 #define IRQ_FTFL_COLLISION 19
1872 #define IRQ_LOW_VOLTAGE 20 1872 #define IRQ_LOW_VOLTAGE 20
1873 #define IRQ_LLWU 21 1873 #define IRQ_LLWU 21
1874 #define IRQ_WDOG 22 1874 #define IRQ_WDOG 22
1875 #define IRQ_I2C0 24 1875 #define IRQ_I2C0 24
1876 #define IRQ_I2C1 25 1876 #define IRQ_I2C1 25
1877 #define IRQ_SPI0 26 1877 #define IRQ_SPI0 26
1878 #define IRQ_SPI1 27 1878 #define IRQ_SPI1 27
1879 #define IRQ_CAN_MESSAGE 29 1879 #define IRQ_CAN_MESSAGE 29
1880 #define IRQ_CAN_BUS_OFF 30 1880 #define IRQ_CAN_BUS_OFF 30
1881 #define IRQ_CAN_ERROR 31 1881 #define IRQ_CAN_ERROR 31
1882 #define IRQ_CAN_TX_WARN 32 1882 #define IRQ_CAN_TX_WARN 32
1883 #define IRQ_CAN_RX_WARN 33 1883 #define IRQ_CAN_RX_WARN 33
1884 #define IRQ_CAN_WAKEUP 34 1884 #define IRQ_CAN_WAKEUP 34
1885 #define IRQ_I2S0_TX 35 1885 #define IRQ_I2S0_TX 35
1886 #define IRQ_I2S0_RX 36 1886 #define IRQ_I2S0_RX 36
1887 #define IRQ_UART0_LON 44 1887 #define IRQ_UART0_LON 44
1888 #define IRQ_UART0_STATUS 45 1888 #define IRQ_UART0_STATUS 45
1889 #define IRQ_UART0_ERROR 46 1889 #define IRQ_UART0_ERROR 46
1890 #define IRQ_UART1_STATUS 47 1890 #define IRQ_UART1_STATUS 47
1891 #define IRQ_UART1_ERROR 48 1891 #define IRQ_UART1_ERROR 48
1892 #define IRQ_UART2_STATUS 49 1892 #define IRQ_UART2_STATUS 49
1893 #define IRQ_UART2_ERROR 50 1893 #define IRQ_UART2_ERROR 50
1894 #define IRQ_ADC0 57 1894 #define IRQ_ADC0 57
1895 #define IRQ_ADC1 58 1895 #define IRQ_ADC1 58
1896 #define IRQ_CMP0 59 1896 #define IRQ_CMP0 59
1897 #define IRQ_CMP1 60 1897 #define IRQ_CMP1 60
1898 #define IRQ_CMP2 61 1898 #define IRQ_CMP2 61
1899 #define IRQ_FTM0 62 1899 #define IRQ_FTM0 62
1900 #define IRQ_FTM1 63 1900 #define IRQ_FTM1 63
1901 #define IRQ_FTM2 64 1901 #define IRQ_FTM2 64
1902 #define IRQ_CMT 65 1902 #define IRQ_CMT 65
1903 #define IRQ_RTC_ALARM 66 1903 #define IRQ_RTC_ALARM 66
1904 #define IRQ_RTC_SECOND 67 1904 #define IRQ_RTC_SECOND 67
1905 #define IRQ_PIT_CH0 68 1905 #define IRQ_PIT_CH0 68
1906 #define IRQ_PIT_CH1 69 1906 #define IRQ_PIT_CH1 69
1907 #define IRQ_PIT_CH2 70 1907 #define IRQ_PIT_CH2 70
1908 #define IRQ_PIT_CH3 71 1908 #define IRQ_PIT_CH3 71
1909 #define IRQ_PDB 72 1909 #define IRQ_PDB 72
1910 #define IRQ_USBOTG 73 1910 #define IRQ_USBOTG 73
1911 #define IRQ_USBDCD 74 1911 #define IRQ_USBDCD 74
1912 #define IRQ_DAC0 81 1912 #define IRQ_DAC0 81
1913 #define IRQ_TSI 83 1913 #define IRQ_TSI 83
1914 #define IRQ_MCG 84 1914 #define IRQ_MCG 84
1915 #define IRQ_LPTMR 85 1915 #define IRQ_LPTMR 85
1916 #define IRQ_PORTA 87 1916 #define IRQ_PORTA 87
1917 #define IRQ_PORTB 88 1917 #define IRQ_PORTB 88
1918 #define IRQ_PORTC 89 1918 #define IRQ_PORTC 89
1919 #define IRQ_PORTD 90 1919 #define IRQ_PORTD 90
1920 #define IRQ_PORTE 91 1920 #define IRQ_PORTE 91
1921 #define IRQ_SOFTWARE 94 1921 #define IRQ_SOFTWARE 94
1922 #define NVIC_NUM_INTERRUPTS 95 1922 #define NVIC_NUM_INTERRUPTS 95
1923 1923
1924 #endif 1924 #endif
1925 1925
1926 1926
1927 1927
1928 1928
1929 1929
1930 #define __disable_irq() asm volatile("CPSID i"); 1930 #define __disable_irq() asm volatile("CPSID i");
1931 #define __enable_irq() asm volatile("CPSIE i"); 1931 #define __enable_irq() asm volatile("CPSIE i");
1932 1932
1933 // System Control Space (SCS), ARMv7 ref manual, B3.2, page 708 1933 // System Control Space (SCS), ARMv7 ref manual, B3.2, page 708
1934 #define SCB_CPUID *(const uint32_t *)0xE000ED00 // CPUID Base Register 1934 #define SCB_CPUID *(const uint32_t *)0xE000ED00 // CPUID Base Register
1935 #define SCB_ICSR *(volatile uint32_t *)0xE000ED04 // Interrupt Control and State 1935 #define SCB_ICSR *(volatile uint32_t *)0xE000ED04 // Interrupt Control and State
1936 #define SCB_ICSR_PENDSTSET (uint32_t)0x04000000 1936 #define SCB_ICSR_PENDSTSET (uint32_t)0x04000000
1937 #define SCB_VTOR *(volatile uint32_t *)0xE000ED08 // Vector Table Offset 1937 #define SCB_VTOR *(volatile uint32_t *)0xE000ED08 // Vector Table Offset
1938 #define SCB_AIRCR *(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control 1938 #define SCB_AIRCR *(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control
1939 #define SCB_SCR *(volatile uint32_t *)0xE000ED10 // System Control Register 1939 #define SCB_SCR *(volatile uint32_t *)0xE000ED10 // System Control Register
1940 #define SCB_CCR *(volatile uint32_t *)0xE000ED14 // Configuration and Control 1940 #define SCB_CCR *(volatile uint32_t *)0xE000ED14 // Configuration and Control
1941 #define SCB_SHPR1 *(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1 1941 #define SCB_SHPR1 *(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1
1942 #define SCB_SHPR2 *(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2 1942 #define SCB_SHPR2 *(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2
1943 #define SCB_SHPR3 *(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3 1943 #define SCB_SHPR3 *(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3
1944 #define SCB_SHCSR *(volatile uint32_t *)0xE000ED24 // System Handler Control and State 1944 #define SCB_SHCSR *(volatile uint32_t *)0xE000ED24 // System Handler Control and State
1945 #define SCB_CFSR *(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register 1945 #define SCB_CFSR *(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register
1946 #define SCB_HFSR *(volatile uint32_t *)0xE000ED2C // HardFault Status 1946 #define SCB_HFSR *(volatile uint32_t *)0xE000ED2C // HardFault Status
1947 #define SCB_DFSR *(volatile uint32_t *)0xE000ED30 // Debug Fault Status 1947 #define SCB_DFSR *(volatile uint32_t *)0xE000ED30 // Debug Fault Status
1948 #define SCB_MMFAR *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address 1948 #define SCB_MMFAR *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address
1949 1949
1950 #define SYST_CSR *(volatile uint32_t *)0xE000E010 // SysTick Control and Status 1950 #define SYST_CSR *(volatile uint32_t *)0xE000E010 // SysTick Control and Status
1951 #define SYST_CSR_COUNTFLAG (uint32_t)0x00010000 1951 #define SYST_CSR_COUNTFLAG (uint32_t)0x00010000
1952 #define SYST_CSR_CLKSOURCE (uint32_t)0x00000004 1952 #define SYST_CSR_CLKSOURCE (uint32_t)0x00000004
1953 #define SYST_CSR_TICKINT (uint32_t)0x00000002 1953 #define SYST_CSR_TICKINT (uint32_t)0x00000002
1954 #define SYST_CSR_ENABLE (uint32_t)0x00000001 1954 #define SYST_CSR_ENABLE (uint32_t)0x00000001
1955 #define SYST_RVR *(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register 1955 #define SYST_RVR *(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register
1956 #define SYST_CVR *(volatile uint32_t *)0xE000E018 // SysTick Current Value Register 1956 #define SYST_CVR *(volatile uint32_t *)0xE000E018 // SysTick Current Value Register
1957 #define SYST_CALIB *(const uint32_t *)0xE000E01C // SysTick Calibration Value 1957 #define SYST_CALIB *(const uint32_t *)0xE000E01C // SysTick Calibration Value
1958 1958
1959 1959
1960 #define ARM_DEMCR *(volatile uint32_t *)0xE000EDFC // Debug Exception and Monitor Control 1960 #define ARM_DEMCR *(volatile uint32_t *)0xE000EDFC // Debug Exception and Monitor Control
1961 #define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks 1961 #define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks
1962 #define ARM_DWT_CTRL *(volatile uint32_t *)0xE0001000 // DWT control register 1962 #define ARM_DWT_CTRL *(volatile uint32_t *)0xE0001000 // DWT control register
1963 #define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count 1963 #define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count
1964 #define ARM_DWT_CYCCNT *(volatile uint32_t *)0xE0001004 // Cycle count register 1964 #define ARM_DWT_CYCCNT *(volatile uint32_t *)0xE0001004 // Cycle count register
1965 1965
1966 // Other 1966 // Other